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Apply the following automated changes to try to eliminate no-longer-needed sys/cdefs.h includes as well as now-empty blank lines in a row. Remove /^#if.*\n#endif.*\n#include\s+<sys/cdefs.h>.*\n/ Remove /\n+#include\s+<sys/cdefs.h>.*\n+#if.*\n#endif.*\n+/ Remove /\n+#if.*\n#endif.*\n+/ Remove /^#if.*\n#endif.*\n/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/types.h>/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/param.h>/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/capsicum.h>/ Sponsored by: Netflix
159 lines
4.2 KiB
C
159 lines
4.2 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2021 Alstom Group.
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* Copyright (c) 2021 Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ENETC_H_
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#define _ENETC_H_
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#include <sys/param.h>
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#include <dev/enetc/enetc_hw.h>
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struct enetc_softc;
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struct enetc_rx_queue {
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struct enetc_softc *sc;
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uint16_t qid;
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union enetc_rx_bd *ring;
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uint64_t ring_paddr;
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struct if_irq irq;
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bool enabled;
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};
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struct enetc_tx_queue {
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struct enetc_softc *sc;
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union enetc_tx_bd *ring;
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uint64_t ring_paddr;
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qidx_t cidx;
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struct if_irq irq;
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};
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struct enetc_ctrl_queue {
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qidx_t pidx;
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struct iflib_dma_info dma;
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struct enetc_cbd *ring;
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struct if_irq irq;
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};
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struct enetc_softc {
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device_t dev;
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struct mtx mii_lock;
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if_ctx_t ctx;
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if_softc_ctx_t shared;
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#define tx_num_queues shared->isc_ntxqsets
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#define rx_num_queues shared->isc_nrxqsets
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#define tx_queue_size shared->isc_ntxd[0]
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#define rx_queue_size shared->isc_nrxd[0]
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struct resource *regs;
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device_t miibus;
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struct enetc_tx_queue *tx_queues;
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struct enetc_rx_queue *rx_queues;
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struct enetc_ctrl_queue ctrl_queue;
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/* Default RX queue configuration. */
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uint32_t rbmr;
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/*
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* Hardware VLAN hash based filtering uses a 64bit bitmap.
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* We need to know how many vids are in given position to
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* know when to remove the bit from the bitmap.
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*/
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#define VLAN_BITMAP_SIZE 64
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uint8_t vlan_bitmap[64];
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struct if_irq admin_irq;
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int phy_addr;
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struct ifmedia fixed_ifmedia;
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bool fixed_link;
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};
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#define ENETC_RD4(sc, reg) \
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bus_read_4((sc)->regs, reg)
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#define ENETC_WR4(sc, reg, value) \
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bus_write_4((sc)->regs, reg, value)
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#define ENETC_PORT_RD8(sc, reg) \
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bus_read_8((sc)->regs, ENETC_PORT_BASE + (reg))
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#define ENETC_PORT_RD4(sc, reg) \
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bus_read_4((sc)->regs, ENETC_PORT_BASE + (reg))
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#define ENETC_PORT_WR4(sc, reg, value) \
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bus_write_4((sc)->regs, ENETC_PORT_BASE + (reg), value)
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#define ENETC_PORT_RD2(sc, reg) \
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bus_read_2((sc)->regs, ENETC_PORT_BASE + (reg))
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#define ENETC_PORT_WR2(sc, reg, value) \
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bus_write_2((sc)->regs, ENETC_PORT_BASE + (reg), value)
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#define ENETC_TXQ_RD4(sc, q, reg) \
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ENETC_RD4((sc), ENETC_BDR(TX, q, reg))
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#define ENETC_TXQ_WR4(sc, q, reg, value) \
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ENETC_WR4((sc), ENETC_BDR(TX, q, reg), value)
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#define ENETC_RXQ_RD4(sc, q, reg) \
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ENETC_RD4((sc), ENETC_BDR(RX, q, reg))
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#define ENETC_RXQ_WR4(sc, q, reg, value) \
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ENETC_WR4((sc), ENETC_BDR(RX, q, reg), value)
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/* Device constants */
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#define ENETC_MAX_FRAME_LEN 9600
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#define ENETC_MAX_QUEUES 4
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/* Max supported nr of descriptors per frame. */
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#define ENETC_MAX_SCATTER 15
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/*
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* Up to 4096 transmit/receive descriptors are supported,
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* their number has to be a multiple of 64.
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*/
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#define ENETC_MIN_DESC 64
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#define ENETC_MAX_DESC 4096
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#define ENETC_DEFAULT_DESC 512
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#define ENETC_DESC_ALIGN 64
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/* Rings have to be 128B aligned. */
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#define ENETC_RING_ALIGN 128
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#define ENETC_MSIX_COUNT 32
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#define ENETC_RX_INTR_PKT_THR 16
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/* Rx threshold irq timeout, 100us */
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#define ENETC_RX_INTR_TIME_THR ((100ULL * ENETC_CLK) / 1000000ULL)
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#define ENETC_RX_IP_ALIGN 2
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#endif
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