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304 lines
7.2 KiB
C
304 lines
7.2 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright © 2021-2022 Bjoern A. Zeeb
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/endian.h>
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#include <sys/socket.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include "memac_mdio.h"
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#include "miibus_if.h"
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/* #define MEMAC_MDIO_DEBUG */
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/* -------------------------------------------------------------------------- */
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int
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memacphy_miibus_readreg(device_t dev, int phy, int reg)
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{
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return (MIIBUS_READREG(device_get_parent(dev), phy, reg));
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}
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int
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memacphy_miibus_writereg(device_t dev, int phy, int reg, int data)
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{
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return (MIIBUS_WRITEREG(device_get_parent(dev), phy, reg, data));
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}
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void
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memacphy_miibus_statchg(struct memacphy_softc_common *sc)
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{
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if (sc->dpnidev != NULL)
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MIIBUS_STATCHG(sc->dpnidev);
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}
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int
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memacphy_set_ni_dev(struct memacphy_softc_common *sc, device_t nidev)
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{
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if (nidev == NULL)
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return (EINVAL);
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#if defined(MEMAC_MDIO_DEBUG)
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if (bootverbose)
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device_printf(sc->dev, "setting nidev %p (%s)\n",
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nidev, device_get_nameunit(nidev));
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#endif
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if (sc->dpnidev != NULL)
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return (EBUSY);
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sc->dpnidev = nidev;
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return (0);
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}
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int
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memacphy_get_phy_loc(struct memacphy_softc_common *sc, int *phy_loc)
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{
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int error;
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if (phy_loc == NULL)
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return (EINVAL);
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if (sc->phy == -1) {
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*phy_loc = MII_PHY_ANY;
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error = ENODEV;
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} else {
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*phy_loc = sc->phy;
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error = 0;
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}
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#if defined(MEMAC_MDIO_DEBUG)
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if (bootverbose)
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device_printf(sc->dev, "returning phy_loc %d, error %d\n",
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*phy_loc, error);
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#endif
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return (error);
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}
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/* -------------------------------------------------------------------------- */
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/*
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* MDIO Ethernet Management Interface Registers (internal PCS MDIO PHY)
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* 0x0030 MDIO Configuration Register (MDIO_CFG)
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* 0x0034 MDIO Control Register (MDIO_CTL)
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* 0x0038 MDIO Data Register (MDIO_DATA)
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* 0x003c MDIO Register Address Register (MDIO_ADDR)
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*
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* External MDIO interfaces
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* 0x0030 External MDIO Configuration Register (EMDIO_CFG)
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* 0x0034 External MDIO Control Register (EMDIO_CTL)
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* 0x0038 External MDIO Data Register (EMDIO_DATA)
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* 0x003c External MDIO Register Address Register (EMDIO_ADDR)
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*/
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#define MDIO_CFG 0x00030
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#define MDIO_CFG_MDIO_RD_ER (1 << 1)
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#define MDIO_CFG_ENC45 (1 << 6)
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#define MDIO_CFG_BUSY (1 << 31)
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#define MDIO_CTL 0x00034
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#define MDIO_CTL_READ (1 << 15)
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#define MDIO_CTL_PORT_ADDR(_x) (((_x) & 0x1f) << 5)
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#define MDIO_CTL_DEV_ADDR(_x) ((_x) & 0x1f)
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#define MDIO_DATA 0x00038
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#define MDIO_ADDR 0x0003c
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static uint32_t
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memac_read_4(struct memac_mdio_softc_common *sc, uint32_t reg)
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{
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uint32_t v, r;
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v = bus_read_4(sc->mem_res, reg);
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if (sc->is_little_endian)
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r = le32toh(v);
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else
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r = be32toh(v);
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return (r);
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}
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static void
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memac_write_4(struct memac_mdio_softc_common *sc, uint32_t reg, uint32_t val)
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{
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uint32_t v;
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if (sc->is_little_endian)
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v = htole32(val);
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else
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v = htobe32(val);
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bus_write_4(sc->mem_res, reg, v);
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}
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static uint32_t
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memac_miibus_wait_no_busy(struct memac_mdio_softc_common *sc)
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{
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uint32_t count, val;
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for (count = 1000; count > 0; count--) {
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val = memac_read_4(sc, MDIO_CFG);
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if ((val & MDIO_CFG_BUSY) == 0)
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break;
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DELAY(1);
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}
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if (count == 0)
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return (0xffff);
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return (0);
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}
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int
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memac_miibus_readreg(struct memac_mdio_softc_common *sc, int phy, int reg)
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{
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uint32_t cfg, ctl, val;
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/* Set proper Clause 45 mode. */
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cfg = memac_read_4(sc, MDIO_CFG);
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/* XXX 45 support? */
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cfg &= ~MDIO_CFG_ENC45; /* Use Clause 22 */
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memac_write_4(sc, MDIO_CFG, cfg);
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val = memac_miibus_wait_no_busy(sc);
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if (val != 0)
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return (0xffff);
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/* To whom do we want to talk to.. */
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ctl = MDIO_CTL_PORT_ADDR(phy) | MDIO_CTL_DEV_ADDR(reg);
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/* XXX do we need two writes for this to work reliably? */
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memac_write_4(sc, MDIO_CTL, ctl | MDIO_CTL_READ);
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val = memac_miibus_wait_no_busy(sc);
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if (val != 0)
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return (0xffff);
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cfg = memac_read_4(sc, MDIO_CFG);
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if (cfg & MDIO_CFG_MDIO_RD_ER)
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return (0xffff);
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val = memac_read_4(sc, MDIO_DATA);
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val &= 0xffff;
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#if defined(MEMAC_MDIO_DEBUG)
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device_printf(sc->dev, "phy read %d:%d = %#06x\n", phy, reg, val);
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#endif
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return (val);
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}
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int
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memac_miibus_writereg(struct memac_mdio_softc_common *sc, int phy, int reg, int data)
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{
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uint32_t cfg, ctl, val;
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#if defined(MEMAC_MDIO_DEBUG)
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device_printf(sc->dev, "phy write %d:%d\n", phy, reg);
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#endif
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/* Set proper Clause 45 mode. */
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cfg = memac_read_4(sc, MDIO_CFG);
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/* XXX 45 support? */
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cfg &= ~MDIO_CFG_ENC45; /* Use Clause 22 */
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memac_write_4(sc, MDIO_CFG, cfg);
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val = memac_miibus_wait_no_busy(sc);
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if (val != 0)
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return (0xffff);
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/* To whom do we want to talk to.. */
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ctl = MDIO_CTL_PORT_ADDR(phy) | MDIO_CTL_DEV_ADDR(reg);
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memac_write_4(sc, MDIO_CTL, ctl);
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memac_write_4(sc, MDIO_DATA, data & 0xffff);
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val = memac_miibus_wait_no_busy(sc);
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if (val != 0)
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return (0xffff);
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return (0);
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}
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ssize_t
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memac_mdio_get_property(device_t dev, device_t child, const char *propname,
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void *propvalue, size_t size, device_property_type_t type)
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{
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return (bus_generic_get_property(dev, child, propname, propvalue, size, type));
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}
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int
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memac_mdio_read_ivar(device_t dev, device_t child, int index, uintptr_t *result)
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{
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return (BUS_READ_IVAR(device_get_parent(dev), dev, index, result));
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}
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int
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memac_mdio_generic_attach(struct memac_mdio_softc_common *sc)
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{
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int rid;
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
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&rid, RF_ACTIVE | RF_SHAREABLE);
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if (sc->mem_res == NULL) {
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device_printf(sc->dev, "%s: cannot allocate mem resource\n",
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__func__);
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return (ENXIO);
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}
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sc->is_little_endian = device_has_property(sc->dev, "little-endian");
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return (0);
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}
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int
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memac_mdio_generic_detach(struct memac_mdio_softc_common *sc)
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{
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if (sc->mem_res != NULL)
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bus_release_resource(sc->dev, SYS_RES_MEMORY,
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rman_get_rid(sc->mem_res), sc->mem_res);
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return (0);
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}
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