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92 lines
3.6 KiB
C
92 lines
3.6 KiB
C
/*-
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* SPDX-License-Identifier: ISC
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*
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* Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
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* Copyright (c) 2010 Broadcom Corporation
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* All rights reserved.
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*
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* Portions of this file were derived from the sbchipc.h header contributed by
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* Broadcom to to the Linux staging repository, as well as later revisions of
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* sbchipc.h distributed with the Asus RT-N16 firmware source code release.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
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* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
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* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _BHND_BHNDREG_H_
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#define _BHND_BHNDREG_H_
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/**
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* The default address at which the ChipCommon core is mapped on all siba(4)
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* devices, and most (all?) bcma(4) devices.
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*/
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#define BHND_DEFAULT_CHIPC_ADDR 0x18000000
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/**
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* The standard size of a primary BHND_PORT_DEVICE or BHND_PORT_AGENT
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* register block.
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*/
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#define BHND_DEFAULT_CORE_SIZE 0x1000
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/**
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* The standard size of the siba(4) and bcma(4) enumeration space.
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*/
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#define BHND_DEFAULT_ENUM_SIZE 0x00100000
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/*
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* Common per-core clock control/status register available on PMU-equipped
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* devices.
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*
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* Clock Mode Name Description
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* High Throughput (HT) Full bandwidth, low latency. Generally supplied
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* from PLL.
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* Active Low Power (ALP) Register access, low speed DMA.
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* Idle Low Power (ILP) No interconnect activity, or if long latency
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* is permitted.
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*/
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#define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */
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#define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */
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#define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */
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#define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */
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#define BHND_CCS_FORCE_MASK 0x0000000F
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#define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */
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#define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */
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#define BHND_CCS_AREQ_MASK 0x00000018
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#define BHND_CCS_FORCEHWREQOFF 0x00000020 /**< Force HW Clock Request Off */
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#define BHND_CCS_ERSRC_REQ_MASK 0x00000700 /**< external resource requests */
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#define BHND_CCS_ERSRC_REQ_SHIFT 8
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#define BHND_CCS_ERSRC_MAX 2 /**< maximum ERSRC value (corresponding to bits 0-2) */
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#define BHND_CCS_ALPAVAIL 0x00010000 /**< ALP is available */
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#define BHND_CCS_HTAVAIL 0x00020000 /**< HT is available */
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#define BHND_CCS_AVAIL_MASK 0x00030000
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#define BHND_CCS_BP_ON_APL 0x00040000 /**< RO: Backplane is running on ALP clock */
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#define BHND_CCS_BP_ON_HT 0x00080000 /**< RO: Backplane is running on HT clock */
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#define BHND_CCS_ERSRC_STS_MASK 0x07000000 /**< external resource status */
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#define BHND_CCS_ERSRC_STS_SHIFT 24
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#define BHND_CCS0_HTAVAIL 0x00010000 /**< HT avail in chipc and pcmcia on 4328a0 */
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#define BHND_CCS0_ALPAVAIL 0x00020000 /**< ALP avail in chipc and pcmcia on 4328a0 */
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#define BHND_CCS_GET_FLAG(_value, _flag) \
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(((_value) & _flag) != 0)
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#define BHND_CCS_GET_BITS(_value, _field) \
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(((_value) & _field ## _MASK) >> _field ## _SHIFT)
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#define BHND_CCS_SET_BITS(_value, _field) \
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(((_value) << _field ## _SHIFT) & _field ## _MASK)
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#endif /* _BHND_BHNDREG_H_ */
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