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566 lines
16 KiB
C
566 lines
16 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/ata.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/stdarg.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/ata/ata-all.h>
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#include <dev/ata/ata-pci.h>
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#include <ata_if.h>
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/* local prototypes */
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static int ata_via_chipinit(device_t dev);
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static int ata_via_ch_attach(device_t dev);
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static int ata_via_ch_detach(device_t dev);
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static void ata_via_reset(device_t dev);
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static int ata_via_status(device_t dev);
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static int ata_via_old_setmode(device_t dev, int target, int mode);
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static void ata_via_southbridge_fixup(device_t dev);
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static int ata_via_new_setmode(device_t dev, int target, int mode);
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static int ata_via_sata_ch_attach(device_t dev);
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static int ata_via_sata_getrev(device_t dev, int target);
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static int ata_via_sata_setmode(device_t dev, int target, int mode);
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static void ata_via_sata_reset(device_t dev);
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static int ata_via_sata_scr_read(device_t dev, int port, int reg,
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u_int32_t *result);
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static int ata_via_sata_scr_write(device_t dev, int port, int reg,
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u_int32_t value);
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static int ata_via_sata_status(device_t dev);
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/* misc defines */
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#define VIA33 0
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#define VIA66 1
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#define VIA100 2
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#define VIA133 3
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#define VIACLK 0x01
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#define VIABUG 0x02
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#define VIABAR 0x04
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#define VIASATA 0x10
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/*
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* VIA Technologies Inc. chipset support functions
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*/
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static int
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ata_via_probe(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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static const struct ata_chip_id ids[] =
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{{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" },
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{ ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" },
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{ ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" },
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{ ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" },
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{ ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"},
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{ ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" },
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{ ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" },
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{ ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" },
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{ ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" },
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{ ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" },
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{ ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" },
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{ ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" },
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{ ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
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{ ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" },
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{ ATA_VIA8237S, 0x00, VIA133, 0x00, ATA_UDMA6, "8237S" },
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{ ATA_VIA8237_5372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
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{ ATA_VIA8237_7372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
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{ ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" },
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{ ATA_VIACX700, 0x00, VIA133, VIASATA, ATA_SA150, "CX700" },
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{ ATA_VIAVX800, 0x00, VIA133, VIASATA, ATA_SA150, "VX800" },
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{ ATA_VIAVX855, 0x00, VIA133, 0x00, ATA_UDMA6, "VX855" },
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{ ATA_VIAVX900, 0x00, VIA133, VIASATA, ATA_SA300, "VX900" },
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{ 0, 0, 0, 0, 0, 0 }};
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static const struct ata_chip_id new_ids[] =
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{{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" },
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{ ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" },
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{ ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" },
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{ ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" },
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{ ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" },
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{ ATA_VIA8237_5372, 0x00, 7, 0x00, ATA_SA300, "8237" },
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{ ATA_VIA8237_7372, 0x00, 7, 0x00, ATA_SA300, "8237" },
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{ 0, 0, 0, 0, 0, 0 }};
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if (pci_get_vendor(dev) != ATA_VIA_ID)
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return ENXIO;
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if (pci_get_devid(dev) == ATA_VIA82C571 ||
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pci_get_devid(dev) == ATA_VIACX700IDE ||
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pci_get_devid(dev) == ATA_VIASATAIDE ||
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pci_get_devid(dev) == ATA_VIASATAIDE2 ||
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pci_get_devid(dev) == ATA_VIASATAIDE3) {
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if (!(ctlr->chip = ata_find_chip(dev, ids, -99)))
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return ENXIO;
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}
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else {
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if (!(ctlr->chip = ata_match_chip(dev, new_ids)))
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return ENXIO;
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}
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ata_set_desc(dev);
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ctlr->chipinit = ata_via_chipinit;
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return (BUS_PROBE_LOW_PRIORITY);
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}
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static int
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ata_via_chipinit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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if (ata_setup_interrupt(dev, ata_generic_intr))
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return ENXIO;
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/* 2 SATA with "SATA registers" at PCI config space + PATA on secondary */
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if (ctlr->chip->cfg2 & VIASATA) {
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ctlr->ch_attach = ata_via_sata_ch_attach;
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ctlr->setmode = ata_via_sata_setmode;
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ctlr->getrev = ata_via_sata_getrev;
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ctlr->reset = ata_via_sata_reset;
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return 0;
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}
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/* Legacy SATA/SATA+PATA with SATA registers in BAR(5). */
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if (ctlr->chip->max_dma >= ATA_SA150) {
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ctlr->r_type2 = SYS_RES_IOPORT;
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ctlr->r_rid2 = PCIR_BAR(5);
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if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
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&ctlr->r_rid2, RF_ACTIVE))) {
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ctlr->ch_attach = ata_via_ch_attach;
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ctlr->ch_detach = ata_via_ch_detach;
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ctlr->reset = ata_via_reset;
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}
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if (ctlr->chip->cfg2 & VIABAR) {
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ctlr->channels = 3;
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ctlr->setmode = ata_via_new_setmode;
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} else
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ctlr->setmode = ata_sata_setmode;
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ctlr->getrev = ata_sata_getrev;
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return 0;
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}
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/* prepare for ATA-66 on the 82C686a and 82C596b */
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if (ctlr->chip->cfg2 & VIACLK)
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pci_write_config(dev, 0x50, 0x030b030b, 4);
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/* the southbridge might need the data corruption fix */
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if (ctlr->chip->cfg2 & VIABUG)
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ata_via_southbridge_fixup(dev);
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/* set fifo configuration half'n'half */
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pci_write_config(dev, 0x43,
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(pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
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/* set status register read retry */
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pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
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/* set DMA read & end-of-sector fifo flush */
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pci_write_config(dev, 0x46,
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(pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
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/* set sector size */
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pci_write_config(dev, 0x60, DEV_BSIZE, 2);
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pci_write_config(dev, 0x68, DEV_BSIZE, 2);
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ctlr->setmode = ata_via_old_setmode;
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return 0;
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}
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static int
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ata_via_ch_attach(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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/* newer SATA chips has resources in one BAR for each channel */
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if (ctlr->chip->cfg2 & VIABAR) {
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struct resource *r_io;
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int i, rid;
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ata_pci_dmainit(dev);
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rid = PCIR_BAR(ch->unit);
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if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
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SYS_RES_IOPORT,
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&rid, RF_ACTIVE)))
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return ENXIO;
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for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
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ch->r_io[i].res = r_io;
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ch->r_io[i].offset = i;
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}
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ch->r_io[ATA_CONTROL].res = r_io;
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ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
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ch->r_io[ATA_IDX_ADDR].res = r_io;
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ata_default_registers(dev);
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for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
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ch->r_io[i].res = ctlr->r_res1;
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ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
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}
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ata_pci_hw(dev);
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if (ch->unit >= 2)
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return 0;
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}
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else {
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/* setup the usual register normal pci style */
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if (ata_pci_ch_attach(dev))
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return ENXIO;
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}
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ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
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ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
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ch->r_io[ATA_SERROR].res = ctlr->r_res2;
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ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
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ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
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ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
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ch->hw.status = ata_via_status;
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ch->flags |= ATA_NO_SLAVE;
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ch->flags |= ATA_SATA;
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ch->flags |= ATA_PERIODIC_POLL;
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ata_sata_scr_write(ch, -1, ATA_SERROR, 0xffffffff);
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return 0;
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}
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static int
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ata_via_ch_detach(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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/* newer SATA chips has resources in one BAR for each channel */
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if (ctlr->chip->cfg2 & VIABAR) {
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int rid;
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rid = PCIR_BAR(ch->unit);
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bus_release_resource(device_get_parent(dev),
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SYS_RES_IOPORT, rid, ch->r_io[ATA_CONTROL].res);
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ata_pci_dmafini(dev);
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}
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else {
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/* setup the usual register normal pci style */
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if (ata_pci_ch_detach(dev))
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return ENXIO;
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}
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return 0;
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}
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static void
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ata_via_reset(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1))
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ata_generic_reset(dev);
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else {
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if (ata_sata_phy_reset(dev, -1, 1))
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ata_generic_reset(dev);
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else
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ch->devices = 0;
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}
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}
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static int
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ata_via_status(device_t dev)
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{
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ata_sata_phy_check_events(dev, -1);
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return (ata_pci_status(dev));
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}
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static int
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ata_via_new_setmode(device_t dev, int target, int mode)
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{
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device_t parent = device_get_parent(dev);
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struct ata_pci_controller *ctlr = device_get_softc(parent);
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struct ata_channel *ch = device_get_softc(dev);
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if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) {
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int piomode;
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static const uint8_t pio_timings[] =
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{ 0xa8, 0x65, 0x65, 0x32, 0x20 };
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static const uint8_t dma_timings[] =
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{ 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 };
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/* This chip can't do WDMA. */
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if (mode >= ATA_WDMA0 && mode < ATA_UDMA0)
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mode = ATA_PIO4;
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if (mode >= ATA_UDMA0) {
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pci_write_config(parent, 0xb3,
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dma_timings[mode & ATA_MODE_MASK], 1);
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piomode = ATA_PIO4;
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} else
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piomode = mode;
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pci_write_config(parent, 0xab, pio_timings[ata_mode2idx(piomode)], 1);
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} else
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mode = ata_sata_setmode(dev, target, mode);
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return (mode);
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}
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static int
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ata_via_old_setmode(device_t dev, int target, int mode)
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{
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device_t parent = device_get_parent(dev);
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struct ata_pci_controller *ctlr = device_get_softc(parent);
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struct ata_channel *ch = device_get_softc(dev);
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int devno = (ch->unit << 1) + target;
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int reg = 0x53 - devno;
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int piomode;
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static const uint8_t timings[] =
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{ 0xa8, 0x65, 0x42, 0x22, 0x20, 0xa8, 0x22, 0x20 };
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static const uint8_t modes[][7] = {
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{ 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
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{ 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
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{ 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
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{ 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 } }; /* VIA ATA133 */
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mode = min(mode, ctlr->chip->max_dma);
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/* Set UDMA timings */
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if (mode >= ATA_UDMA0) {
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pci_write_config(parent, reg,
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modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
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piomode = ATA_PIO4;
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} else {
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pci_write_config(parent, reg, 0x8b, 1);
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piomode = mode;
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}
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/* Set WDMA/PIO timings */
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pci_write_config(parent, reg - 0x08,timings[ata_mode2idx(piomode)], 1);
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return (mode);
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}
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|
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static void
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ata_via_southbridge_fixup(device_t dev)
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{
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device_t *children;
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int nchildren, i;
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if (device_get_children(device_get_parent(dev), &children, &nchildren))
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return;
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for (i = 0; i < nchildren; i++) {
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if (pci_get_devid(children[i]) == ATA_VIA8363 ||
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pci_get_devid(children[i]) == ATA_VIA8371 ||
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pci_get_devid(children[i]) == ATA_VIA8662 ||
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pci_get_devid(children[i]) == ATA_VIA8361) {
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u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
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if ((reg76 & 0xf0) != 0xd0) {
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|
device_printf(dev,
|
|
"Correcting VIA config for southbridge data corruption bug\n");
|
|
pci_write_config(children[i], 0x75, 0x80, 1);
|
|
pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
free(children, M_TEMP);
|
|
}
|
|
|
|
static int
|
|
ata_via_sata_ch_attach(device_t dev)
|
|
{
|
|
struct ata_channel *ch = device_get_softc(dev);
|
|
|
|
if (ata_pci_ch_attach(dev))
|
|
return ENXIO;
|
|
if (ch->unit == 0) {
|
|
ch->hw.status = ata_via_sata_status;
|
|
ch->hw.pm_read = ata_via_sata_scr_read;
|
|
ch->hw.pm_write = ata_via_sata_scr_write;
|
|
ch->flags |= ATA_PERIODIC_POLL;
|
|
ch->flags |= ATA_SATA;
|
|
ata_sata_scr_write(ch, 0, ATA_SERROR, 0xffffffff);
|
|
ata_sata_scr_write(ch, 1, ATA_SERROR, 0xffffffff);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ata_via_sata_getrev(device_t dev, int target)
|
|
{
|
|
device_t parent = device_get_parent(dev);
|
|
struct ata_channel *ch = device_get_softc(dev);
|
|
|
|
if (ch->unit == 0) {
|
|
if (pci_read_config(parent, 0xa0 + target, 1) & 0x10)
|
|
return (2);
|
|
else
|
|
return (1);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ata_via_sata_setmode(device_t dev, int target, int mode)
|
|
{
|
|
struct ata_channel *ch = device_get_softc(dev);
|
|
|
|
if (ch->unit == 0)
|
|
return (mode);
|
|
return (ata_via_old_setmode(dev, target, mode));
|
|
}
|
|
|
|
static void
|
|
ata_via_sata_reset(device_t dev)
|
|
{
|
|
struct ata_channel *ch = device_get_softc(dev);
|
|
int devs, count;
|
|
uint8_t status;
|
|
|
|
if (ch->unit == 0) {
|
|
devs = ata_sata_phy_reset(dev, 0, 0);
|
|
count = 0;
|
|
do {
|
|
ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA |
|
|
ATA_DEV(ATA_MASTER));
|
|
DELAY(1000);
|
|
status = ATA_IDX_INB(ch, ATA_STATUS);
|
|
count++;
|
|
} while (status & ATA_S_BUSY && count < 100);
|
|
|
|
devs += ata_sata_phy_reset(dev, 1, 0);
|
|
count = 0;
|
|
do {
|
|
ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA |
|
|
ATA_DEV(ATA_SLAVE));
|
|
DELAY(1000);
|
|
status = ATA_IDX_INB(ch, ATA_STATUS);
|
|
count++;
|
|
} while (status & ATA_S_BUSY && count < 100);
|
|
} else
|
|
devs = 1;
|
|
if (devs)
|
|
ata_generic_reset(dev);
|
|
else
|
|
ch->devices = 0;
|
|
}
|
|
|
|
static int
|
|
ata_via_sata_scr_read(device_t dev, int port, int reg, u_int32_t *result)
|
|
{
|
|
device_t parent;
|
|
uint32_t val;
|
|
|
|
parent = device_get_parent(dev);
|
|
port = (port == 1) ? 1 : 0;
|
|
switch (reg) {
|
|
case ATA_SSTATUS:
|
|
val = pci_read_config(parent, 0xa0 + port, 1);
|
|
*result = val & 0x03;
|
|
if (*result != ATA_SS_DET_NO_DEVICE) {
|
|
if (val & 0x04)
|
|
*result |= ATA_SS_IPM_PARTIAL;
|
|
else if (val & 0x08)
|
|
*result |= ATA_SS_IPM_SLUMBER;
|
|
else
|
|
*result |= ATA_SS_IPM_ACTIVE;
|
|
if (val & 0x10)
|
|
*result |= ATA_SS_SPD_GEN2;
|
|
else
|
|
*result |= ATA_SS_SPD_GEN1;
|
|
}
|
|
break;
|
|
case ATA_SERROR:
|
|
*result = pci_read_config(parent, 0xa8 + port * 4, 4);
|
|
break;
|
|
case ATA_SCONTROL:
|
|
val = pci_read_config(parent, 0xa4 + port, 1);
|
|
*result = 0;
|
|
if (val & 0x01)
|
|
*result |= ATA_SC_DET_RESET;
|
|
if (val & 0x02)
|
|
*result |= ATA_SC_DET_DISABLE;
|
|
if (val & 0x04)
|
|
*result |= ATA_SC_IPM_DIS_PARTIAL;
|
|
if (val & 0x08)
|
|
*result |= ATA_SC_IPM_DIS_SLUMBER;
|
|
break;
|
|
default:
|
|
return (EINVAL);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ata_via_sata_scr_write(device_t dev, int port, int reg, u_int32_t value)
|
|
{
|
|
device_t parent;
|
|
uint32_t val;
|
|
|
|
parent = device_get_parent(dev);
|
|
port = (port == 1) ? 1 : 0;
|
|
switch (reg) {
|
|
case ATA_SERROR:
|
|
pci_write_config(parent, 0xa8 + port * 4, value, 4);
|
|
break;
|
|
case ATA_SCONTROL:
|
|
val = 0;
|
|
if (value & ATA_SC_DET_RESET)
|
|
val |= 0x01;
|
|
if (value & ATA_SC_DET_DISABLE)
|
|
val |= 0x02;
|
|
if (value & ATA_SC_IPM_DIS_PARTIAL)
|
|
val |= 0x04;
|
|
if (value & ATA_SC_IPM_DIS_SLUMBER)
|
|
val |= 0x08;
|
|
pci_write_config(parent, 0xa4 + port, val, 1);
|
|
break;
|
|
default:
|
|
return (EINVAL);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ata_via_sata_status(device_t dev)
|
|
{
|
|
|
|
ata_sata_phy_check_events(dev, 0);
|
|
ata_sata_phy_check_events(dev, 1);
|
|
return (ata_pci_status(dev));
|
|
}
|
|
|
|
ATA_DECLARE_DRIVER(ata_via);
|