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148 lines
5.6 KiB
C
148 lines
5.6 KiB
C
/*-
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* Copyright (c) 2016 Andriy Gapon <avg@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* The following registers, bits and magic values are defined in Register
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* Reference Guide documents for SB600, SB7x0, SB8x0, SB9x0 southbridges and
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* various versions of Fusion Controller Hubs (FCHs). FCHs integrated into
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* CPUs are documented in BIOS and Kernel Development Guide documents for
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* the corresponding processor families.
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*
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* At present there are three classes of supported chipsets:
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* - SB600 and S7x0 southbridges where the SMBus controller device has
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* a PCI Device ID of 0x43851002 and a revision less than 0x40
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* - several types of southbridges and FCHs:
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* o SB8x0, SB9x0 southbridges where the SMBus controller device has a PCI
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* Device ID of 0x43851002 and a revision greater than or equal to 0x40
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* o FCHs where the controller has an ID of 0x780b1022 and a revision less
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* than 0x41 (various variants of "Hudson" and "Bolton" as well as FCHs
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* integrated into processors, e.g. "Kabini")
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* o FCHs where the controller has an ID of 0x790b1022 and a revision less
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* than 0x49
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* - several types of FCHs:
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* o FCHs where the SMBus controller device has a PCI Device ID of 0x780b1022
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* and a revision greater than or equal to 0x41 (integrated into "Mullins"
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* processors, code named "ML")
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* o FCHs where the controller has an ID of 0x790b1022 and a revision greater
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* than or equal to 0x49 (integrated into "Carrizo" processors, code named
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* "KERNCZ" or "CZ")
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*
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* The register definitions are compatible within the classes and may be
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* incompatible across them.
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*/
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/*
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* IO registers for accessing the PMIO space.
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* See SB7xx RRG 2.3.3.1.1, for instance.
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*/
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#define AMDSB_PMIO_INDEX 0xcd6
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#define AMDSB_PMIO_DATA (PMIO_INDEX + 1)
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#define AMDSB_PMIO_WIDTH 2
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/*
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* SB7x0 and compatible registers in the PMIO space.
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* See SB7xx RRG 2.3.3.2.
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*/
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#define AMDSB_PM_RESET_STATUS0 0x44
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#define AMDSB_PM_RESET_STATUS1 0x45
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#define AMDSB_WD_RST_STS 0x02
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#define AMDSB_PM_WDT_CTRL 0x69
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#define AMDSB_WDT_DISABLE 0x01
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#define AMDSB_WDT_RES_MASK (0x02 | 0x04)
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#define AMDSB_WDT_RES_32US 0x00
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#define AMDSB_WDT_RES_10MS 0x02
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#define AMDSB_WDT_RES_100MS 0x04
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#define AMDSB_WDT_RES_1S 0x06
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#define AMDSB_PM_WDT_BASE_LSB 0x6c
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#define AMDSB_PM_WDT_BASE_MSB 0x6f
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/*
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* SB8x0 and compatible registers in the PMIO space.
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* See SB8xx RRG 2.3.3, for instance.
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*/
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#define AMDSB8_PM_SMBUS_EN 0x2c
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#define AMDSB8_SMBUS_EN 0x01
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#define AMDSB8_SMBUS_ADDR_MASK 0xffe0u
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#define AMDSB8_PM_WDT_EN 0x48
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#define AMDSB8_WDT_DEC_EN 0x01
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#define AMDSB8_WDT_DISABLE 0x02
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#define AMDSB8_PM_WDT_CTRL 0x4c
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#define AMDSB8_WDT_32KHZ 0x00
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#define AMDSB8_WDT_1HZ 0x03
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#define AMDSB8_WDT_RES_MASK 0x03
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#define AMDSB8_PM_RESET_STATUS 0xc0 /* 32 bit wide */
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#define AMDSB8_WD_RST_STS 0x2000000
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#define AMDSB8_PM_RESET_CTRL 0xc4
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#define AMDSB8_RST_STS_DIS 0x04
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/*
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* Newer FCH registers in the PMIO space.
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* See BKDG for Family 16h Models 30h-3Fh 3.26.13 PMx00 and PMx04.
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*/
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#define AMDFCH41_PM_DECODE_EN0 0x00
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#define AMDFCH41_SMBUS_EN 0x10
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#define AMDFCH41_WDT_EN 0x80
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#define AMDFCH41_PM_DECODE_EN1 0x01
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#define AMDFCH41_PM_DECODE_EN3 0x03
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#define AMDFCH41_WDT_RES_MASK 0x03
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#define AMDFCH41_WDT_RES_32US 0x00
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#define AMDFCH41_WDT_RES_10MS 0x01
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#define AMDFCH41_WDT_RES_100MS 0x02
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#define AMDFCH41_WDT_RES_1S 0x03
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#define AMDFCH41_WDT_EN_MASK 0x0c
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#define AMDFCH41_WDT_ENABLE 0x00
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#define AMDFCH41_PM_ISA_CTRL 0x04
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#define AMDFCH41_MMIO_EN 0x02
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/*
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* Fixed MMIO addresses for accessing Watchdog and SMBus registers.
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* See BKDG for Family 16h Models 30h-3Fh 3.26.13 PMx00 and PMx04.
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*/
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#define AMDFCH41_WDT_FIXED_ADDR 0xfeb00000u
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#define AMDFCH41_MMIO_ADDR 0xfed80000u
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#define AMDFCH41_MMIO_SMBUS_OFF 0x0a00
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#define AMDFCH41_MMIO_WDT_OFF 0x0b00
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/*
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* PCI Device IDs and revisions.
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* SB600 RRG 2.3.1.1,
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* SB7xx RRG 2.3.1.1,
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* SB8xx RRG 2.3.1,
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* BKDG for Family 15h Models 60h-6Fh 3.26.6.1,
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* BKDG for Family 15h Models 70h-7Fh 3.26.6.1,
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* BKDG for Family 16h Models 00h-0Fh 3.26.7.1,
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* BKDG for Family 16h Models 30h-3Fh 3.26.7.1.
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* Also, see i2c-piix4 aka piix4_smbus Linux driver.
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*/
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#define AMDSB_SMBUS_DEVID 0x43851002
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#define AMDSB8_SMBUS_REVID 0x40
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#define AMDFCH_SMBUS_DEVID 0x780b1022
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#define AMDFCH41_SMBUS_REVID 0x41
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#define AMDCZ_SMBUS_DEVID 0x790b1022
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#define AMDCZ49_SMBUS_REVID 0x49
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#define HYGONCZ_SMBUS_DEVID 0x790b1d94
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