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99 lines
4.2 KiB
C
99 lines
4.2 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2012 Bjoern A. Zeeb
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-11-C-0249)
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* ("MRC2"), as part of the DARPA MRC research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Altera, Embedded Peripherals IP, User Guide, v. 11.0, June 2011.
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* UG-01085-11.0.
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*/
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#ifndef _A_API_H
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#define _A_API_H
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/* Table 16-1. Memory Map. */
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#define A_ONCHIP_FIFO_MEM_CORE_DATA 0x00
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#define A_ONCHIP_FIFO_MEM_CORE_METADATA 0x04
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#define A_ONCHIP_FIFO_MEM_CORE_SOP (1<<0)
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#define A_ONCHIP_FIFO_MEM_CORE_EOP (1<<1)
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#define A_ONCHIP_FIFO_MEM_CORE_EMPTY_MASK 0x000000f7
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#define A_ONCHIP_FIFO_MEM_CORE_EMPTY_SHIFT 2
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/* Reserved (1<<7) */
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#define A_ONCHIP_FIFO_MEM_CORE_CHANNEL_MASK 0x0000ff00
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#define A_ONCHIP_FIFO_MEM_CORE_CHANNEL_SHIFT 8
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#define A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK 0x00ff0000
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#define A_ONCHIP_FIFO_MEM_CORE_ERROR_SHIFT 16
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/* Reserved 0xff000000 */
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/* Table 16-3. FIFO Status Register Memory Map. */
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#define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_FILL_LEVEL 0x00
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#define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_I_STATUS 0x04
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#define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_EVENT 0x08
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#define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_INT_ENABLE 0x0c
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#define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_ALMOSTFULL 0x10
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#define A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_ALMOSTEMPTY 0x14
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/* Table 16-5. Status Bit Field Descriptions. */
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#define A_ONCHIP_FIFO_MEM_CORE_STATUS_FULL (1<<0)
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#define A_ONCHIP_FIFO_MEM_CORE_STATUS_EMPTY (1<<1)
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#define A_ONCHIP_FIFO_MEM_CORE_STATUS_ALMOSTFULL (1<<2)
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#define A_ONCHIP_FIFO_MEM_CORE_STATUS_ALMOSTEMPTY (1<<3)
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#define A_ONCHIP_FIFO_MEM_CORE_STATUS_OVERFLOW (1<<4)
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#define A_ONCHIP_FIFO_MEM_CORE_STATUS_UNDERFLOW (1<<5)
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/* Table 16-6. Event Bit Field Descriptions. */
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/* XXX Datasheet has incorrect bit fields. Validate. */
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#define A_ONCHIP_FIFO_MEM_CORE_EVENT_FULL (1<<0)
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#define A_ONCHIP_FIFO_MEM_CORE_EVENT_EMPTY (1<<1)
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#define A_ONCHIP_FIFO_MEM_CORE_EVENT_ALMOSTFULL (1<<2)
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#define A_ONCHIP_FIFO_MEM_CORE_EVENT_ALMOSTEMPTY (1<<3)
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#define A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW (1<<4)
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#define A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW (1<<5)
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/* Table 16-7. InterruptEnable Bit Field Descriptions. */
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/* XXX Datasheet has incorrect bit fields. Validate. */
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#define A_ONCHIP_FIFO_MEM_CORE_INTR_FULL (1<<0)
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#define A_ONCHIP_FIFO_MEM_CORE_INTR_EMPTY (1<<1)
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#define A_ONCHIP_FIFO_MEM_CORE_INTR_ALMOSTFULL (1<<2)
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#define A_ONCHIP_FIFO_MEM_CORE_INTR_ALMOSTEMPTY (1<<3)
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#define A_ONCHIP_FIFO_MEM_CORE_INTR_OVERFLOW (1<<4)
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#define A_ONCHIP_FIFO_MEM_CORE_INTR_UNDERFLOW (1<<5)
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#define A_ONCHIP_FIFO_MEM_CORE_INTR_ALL \
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(A_ONCHIP_FIFO_MEM_CORE_INTR_EMPTY| \
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A_ONCHIP_FIFO_MEM_CORE_INTR_FULL| \
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A_ONCHIP_FIFO_MEM_CORE_INTR_ALMOSTEMPTY| \
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A_ONCHIP_FIFO_MEM_CORE_INTR_ALMOSTFULL| \
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A_ONCHIP_FIFO_MEM_CORE_INTR_OVERFLOW| \
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A_ONCHIP_FIFO_MEM_CORE_INTR_UNDERFLOW)
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#endif /* _A_API_H */
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/* end */
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