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47e073941f
To support virtual machines on arm64 add the vmm code. This is based on earlier work by Mihai Carabas and Alexandru Elisei at University Politehnica of Bucharest, with further work by myself and Mark Johnston. All AArch64 CPUs should work, however only the GICv3 interrupt controller is supported. There is initial support to allow the GICv2 to be supported in the future. Only pure Armv8.0 virtualisation is supported, the Virtualization Host Extensions are not currently used. With a separate userspace patch and U-Boot port FreeBSD guests are able to boot to multiuser mode, and the hypervisor can be tested with the kvm unit tests. Linux partially boots, but hangs before entering userspace. Other operating systems are untested. Sponsored by: Arm Ltd Sponsored by: Innovate UK Sponsored by: The FreeBSD Foundation Sponsored by: University Politehnica of Bucharest Differential Revision: https://reviews.freebsd.org/D37428
178 lines
6 KiB
C
178 lines
6 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (C) 2018 Alexandru Elisei <alexandru.elisei@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <machine/armreg.h>
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#include <machine/cpu.h>
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#include <machine/hypervisor.h>
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#include "arm64.h"
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#include "reset.h"
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/*
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* Make the architecturally UNKNOWN value 0. As a bonus, we don't have to
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* manually set all those RES0 fields.
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*/
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#define ARCH_UNKNOWN 0
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#define set_arch_unknown(reg) (memset(&(reg), ARCH_UNKNOWN, sizeof(reg)))
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void
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reset_vm_el01_regs(void *vcpu)
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{
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struct hypctx *el2ctx;
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el2ctx = vcpu;
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set_arch_unknown(el2ctx->tf);
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set_arch_unknown(el2ctx->actlr_el1);
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set_arch_unknown(el2ctx->afsr0_el1);
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set_arch_unknown(el2ctx->afsr1_el1);
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set_arch_unknown(el2ctx->amair_el1);
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set_arch_unknown(el2ctx->contextidr_el1);
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set_arch_unknown(el2ctx->cpacr_el1);
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set_arch_unknown(el2ctx->csselr_el1);
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set_arch_unknown(el2ctx->elr_el1);
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set_arch_unknown(el2ctx->esr_el1);
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set_arch_unknown(el2ctx->far_el1);
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set_arch_unknown(el2ctx->mair_el1);
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set_arch_unknown(el2ctx->mdccint_el1);
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set_arch_unknown(el2ctx->mdscr_el1);
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set_arch_unknown(el2ctx->par_el1);
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/*
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* Guest starts with:
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* ~SCTLR_M: MMU off
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* ~SCTLR_C: data cache off
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* SCTLR_CP15BEN: memory barrier instruction enable from EL0; RAO/WI
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* ~SCTLR_I: instruction cache off
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*/
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el2ctx->sctlr_el1 = SCTLR_RES1;
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el2ctx->sctlr_el1 &= ~SCTLR_M & ~SCTLR_C & ~SCTLR_I;
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el2ctx->sctlr_el1 |= SCTLR_CP15BEN;
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set_arch_unknown(el2ctx->sp_el0);
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set_arch_unknown(el2ctx->tcr_el1);
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set_arch_unknown(el2ctx->tpidr_el0);
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set_arch_unknown(el2ctx->tpidr_el1);
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set_arch_unknown(el2ctx->tpidrro_el0);
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set_arch_unknown(el2ctx->ttbr0_el1);
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set_arch_unknown(el2ctx->ttbr1_el1);
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set_arch_unknown(el2ctx->vbar_el1);
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set_arch_unknown(el2ctx->spsr_el1);
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set_arch_unknown(el2ctx->dbgbcr_el1);
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set_arch_unknown(el2ctx->dbgbvr_el1);
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set_arch_unknown(el2ctx->dbgwcr_el1);
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set_arch_unknown(el2ctx->dbgwvr_el1);
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el2ctx->pmcr_el0 = READ_SPECIALREG(pmcr_el0) & PMCR_N_MASK;
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/* PMCR_LC is unknown when AArch32 is supported or RES1 otherwise */
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el2ctx->pmcr_el0 |= PMCR_LC;
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set_arch_unknown(el2ctx->pmccntr_el0);
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set_arch_unknown(el2ctx->pmccfiltr_el0);
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set_arch_unknown(el2ctx->pmcntenset_el0);
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set_arch_unknown(el2ctx->pmintenset_el1);
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set_arch_unknown(el2ctx->pmovsset_el0);
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set_arch_unknown(el2ctx->pmuserenr_el0);
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memset(el2ctx->pmevcntr_el0, 0, sizeof(el2ctx->pmevcntr_el0));
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memset(el2ctx->pmevtyper_el0, 0, sizeof(el2ctx->pmevtyper_el0));
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}
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void
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reset_vm_el2_regs(void *vcpu)
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{
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struct hypctx *el2ctx;
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uint64_t cpu_aff, vcpuid;
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el2ctx = vcpu;
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vcpuid = vcpu_vcpuid(el2ctx->vcpu);
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/*
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* Set the Hypervisor Configuration Register:
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*
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* HCR_RW: use AArch64 for EL1
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* HCR_TID3: handle ID registers in the vmm to privide a common
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* set of featers on all vcpus
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* HCR_TWI: Trap WFI to the hypervisor
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* HCR_BSU_IS: barrier instructions apply to the inner shareable
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* domain
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* HCR_FB: broadcast maintenance operations
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* HCR_AMO: route physical SError interrupts to EL2
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* HCR_IMO: route physical IRQ interrupts to EL2
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* HCR_FMO: route physical FIQ interrupts to EL2
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* HCR_SWIO: turn set/way invalidate into set/way clean and
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* invalidate
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* HCR_VM: use stage 2 translation
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*/
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el2ctx->hcr_el2 = HCR_RW | HCR_TID3 | HCR_TWI | HCR_BSU_IS | HCR_FB |
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HCR_AMO | HCR_IMO | HCR_FMO | HCR_SWIO | HCR_VM;
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/* TODO: Trap all extensions we don't support */
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el2ctx->mdcr_el2 = 0;
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/* PMCR_EL0.N is read from MDCR_EL2.HPMN */
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el2ctx->mdcr_el2 |= (el2ctx->pmcr_el0 & PMCR_N_MASK) >> PMCR_N_SHIFT;
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el2ctx->vmpidr_el2 = VMPIDR_EL2_RES1;
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/* The guest will detect a multi-core, single-threaded CPU */
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el2ctx->vmpidr_el2 &= ~VMPIDR_EL2_U & ~VMPIDR_EL2_MT;
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/*
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* Generate the guest MPIDR value. We only support 16 CPUs at affinity
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* level 0 to simplify the vgicv3 driver (see writing sgi1r_el1).
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*/
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cpu_aff = (vcpuid & 0xf) << MPIDR_AFF0_SHIFT |
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((vcpuid >> 4) & 0xff) << MPIDR_AFF1_SHIFT |
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((vcpuid >> 12) & 0xff) << MPIDR_AFF2_SHIFT |
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((vcpuid >> 20) & 0xff) << MPIDR_AFF3_SHIFT;
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el2ctx->vmpidr_el2 |= cpu_aff;
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/* Use the same CPU identification information as the host */
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el2ctx->vpidr_el2 = CPU_IMPL_TO_MIDR(CPU_IMPL_ARM);
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el2ctx->vpidr_el2 |= CPU_VAR_TO_MIDR(0);
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el2ctx->vpidr_el2 |= CPU_ARCH_TO_MIDR(0xf);
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el2ctx->vpidr_el2 |= CPU_PART_TO_MIDR(CPU_PART_FOUNDATION);
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el2ctx->vpidr_el2 |= CPU_REV_TO_MIDR(0);
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/*
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* Don't trap accesses to CPACR_EL1, trace, SVE, Advanced SIMD
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* and floating point functionality to EL2.
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*/
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el2ctx->cptr_el2 = CPTR_RES1;
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/*
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* Disable interrupts in the guest. The guest OS will re-enable
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* them.
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*/
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el2ctx->tf.tf_spsr = PSR_D | PSR_A | PSR_I | PSR_F;
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/* Use the EL1 stack when taking exceptions to EL1 */
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el2ctx->tf.tf_spsr |= PSR_M_EL1h;
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}
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