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This will be used to implement parts of bhyve's gdb stub. Three VM capabilities are added, similar to amd64 without monitor mode. Two cause breakpoint and single-step exceptions to be raised to EL2 and then down to bhyve. One lets the gdb stub mask hardware interrupts while single-stepping, since otherwise the guest will handle a timer interrupt before executing the target instruction and thus fail to make progress. Reviewed by: bnovkov, andrew Sponsored by: Innovate UK Differential Revision: https://reviews.freebsd.org/D44739
175 lines
6.6 KiB
C
175 lines
6.6 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (C) 2015 Mihai Carabas <mihai.carabas@gmail.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _VMM_ARM64_H_
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#define _VMM_ARM64_H_
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#include <machine/reg.h>
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#include <machine/hypervisor.h>
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#include <machine/pcpu.h>
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#include "mmu.h"
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#include "io/vgic_v3.h"
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#include "io/vtimer.h"
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struct vgic_v3;
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struct vgic_v3_cpu;
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/*
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* Per-vCPU hypervisor state.
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*/
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struct hypctx {
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struct trapframe tf;
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/*
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* EL1 control registers.
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*/
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uint64_t elr_el1; /* Exception Link Register */
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uint64_t sp_el0; /* Stack pointer */
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uint64_t tpidr_el0; /* EL0 Software ID Register */
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uint64_t tpidrro_el0; /* Read-only Thread ID Register */
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uint64_t tpidr_el1; /* EL1 Software ID Register */
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uint64_t vbar_el1; /* Vector Base Address Register */
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uint64_t actlr_el1; /* Auxiliary Control Register */
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uint64_t afsr0_el1; /* Auxiliary Fault Status Register 0 */
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uint64_t afsr1_el1; /* Auxiliary Fault Status Register 1 */
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uint64_t amair_el1; /* Auxiliary Memory Attribute Indirection Register */
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uint64_t contextidr_el1; /* Current Process Identifier */
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uint64_t cpacr_el1; /* Architectural Feature Access Control Register */
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uint64_t csselr_el1; /* Cache Size Selection Register */
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uint64_t esr_el1; /* Exception Syndrome Register */
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uint64_t far_el1; /* Fault Address Register */
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uint64_t mair_el1; /* Memory Attribute Indirection Register */
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uint64_t mdccint_el1; /* Monitor DCC Interrupt Enable Register */
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uint64_t mdscr_el1; /* Monitor Debug System Control Register */
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uint64_t par_el1; /* Physical Address Register */
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uint64_t sctlr_el1; /* System Control Register */
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uint64_t tcr_el1; /* Translation Control Register */
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uint64_t tcr2_el1; /* Translation Control Register 2 */
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uint64_t ttbr0_el1; /* Translation Table Base Register 0 */
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uint64_t ttbr1_el1; /* Translation Table Base Register 1 */
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uint64_t spsr_el1; /* Saved Program Status Register */
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uint64_t pmcr_el0; /* Performance Monitors Control Register */
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uint64_t pmccntr_el0;
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uint64_t pmccfiltr_el0;
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uint64_t pmcntenset_el0;
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uint64_t pmintenset_el1;
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uint64_t pmovsset_el0;
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uint64_t pmselr_el0;
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uint64_t pmuserenr_el0;
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uint64_t pmevcntr_el0[31];
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uint64_t pmevtyper_el0[31];
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uint64_t dbgbcr_el1[16]; /* Debug Breakpoint Control Registers */
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uint64_t dbgbvr_el1[16]; /* Debug Breakpoint Value Registers */
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uint64_t dbgwcr_el1[16]; /* Debug Watchpoint Control Registers */
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uint64_t dbgwvr_el1[16]; /* Debug Watchpoint Value Registers */
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/* EL2 control registers */
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uint64_t cptr_el2; /* Architectural Feature Trap Register */
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uint64_t hcr_el2; /* Hypervisor Configuration Register */
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uint64_t mdcr_el2; /* Monitor Debug Configuration Register */
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uint64_t vpidr_el2; /* Virtualization Processor ID Register */
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uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
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uint64_t el2_addr; /* The address of this in el2 space */
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struct hyp *hyp;
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struct vcpu *vcpu;
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struct {
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uint64_t far_el2; /* Fault Address Register */
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uint64_t hpfar_el2; /* Hypervisor IPA Fault Address Register */
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} exit_info;
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struct vtimer_cpu vtimer_cpu;
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uint64_t setcaps; /* Currently enabled capabilities. */
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/* vCPU state used to handle guest debugging. */
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uint64_t debug_spsr; /* Saved guest SPSR */
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uint64_t debug_mdscr; /* Saved guest MDSCR */
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struct vgic_v3_regs vgic_v3_regs;
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struct vgic_v3_cpu *vgic_cpu;
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bool has_exception;
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};
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struct hyp {
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struct vm *vm;
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struct vtimer vtimer;
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uint64_t vmid_generation;
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uint64_t vttbr_el2;
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uint64_t el2_addr; /* The address of this in el2 space */
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bool vgic_attached;
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struct vgic_v3 *vgic;
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struct hypctx *ctx[];
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};
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#define DEFINE_VMMOPS_IFUNC(ret_type, opname, args) \
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ret_type vmmops_##opname args;
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DEFINE_VMMOPS_IFUNC(int, modinit, (int ipinum))
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DEFINE_VMMOPS_IFUNC(int, modcleanup, (void))
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DEFINE_VMMOPS_IFUNC(void *, init, (struct vm *vm, struct pmap *pmap))
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DEFINE_VMMOPS_IFUNC(int, gla2gpa, (void *vcpui, struct vm_guest_paging *paging,
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uint64_t gla, int prot, uint64_t *gpa, int *is_fault))
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DEFINE_VMMOPS_IFUNC(int, run, (void *vcpui, register_t pc, struct pmap *pmap,
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struct vm_eventinfo *info))
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DEFINE_VMMOPS_IFUNC(void, cleanup, (void *vmi))
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DEFINE_VMMOPS_IFUNC(void *, vcpu_init, (void *vmi, struct vcpu *vcpu,
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int vcpu_id))
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DEFINE_VMMOPS_IFUNC(void, vcpu_cleanup, (void *vcpui))
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DEFINE_VMMOPS_IFUNC(int, exception, (void *vcpui, uint64_t esr, uint64_t far))
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DEFINE_VMMOPS_IFUNC(int, getreg, (void *vcpui, int num, uint64_t *retval))
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DEFINE_VMMOPS_IFUNC(int, setreg, (void *vcpui, int num, uint64_t val))
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DEFINE_VMMOPS_IFUNC(int, getcap, (void *vcpui, int num, int *retval))
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DEFINE_VMMOPS_IFUNC(int, setcap, (void *vcpui, int num, int val))
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DEFINE_VMMOPS_IFUNC(struct vmspace *, vmspace_alloc, (vm_offset_t min,
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vm_offset_t max))
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DEFINE_VMMOPS_IFUNC(void, vmspace_free, (struct vmspace *vmspace))
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#ifdef notyet
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#ifdef BHYVE_SNAPSHOT
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DEFINE_VMMOPS_IFUNC(int, snapshot, (void *vmi, struct vm_snapshot_meta *meta))
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DEFINE_VMMOPS_IFUNC(int, vcpu_snapshot, (void *vcpui,
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struct vm_snapshot_meta *meta))
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DEFINE_VMMOPS_IFUNC(int, restore_tsc, (void *vcpui, uint64_t now))
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#endif
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#endif
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uint64_t vmm_call_hyp(uint64_t, ...);
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#if 0
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#define eprintf(fmt, ...) printf("%s:%d " fmt, __func__, __LINE__, ##__VA_ARGS__)
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#else
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#define eprintf(fmt, ...) do {} while(0)
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#endif
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struct hypctx *arm64_get_active_vcpu(void);
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void raise_data_insn_abort(struct hypctx *, uint64_t, bool, int);
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#endif /* !_VMM_ARM64_H_ */
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