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Apply the following automated changes to try to eliminate no-longer-needed sys/cdefs.h includes as well as now-empty blank lines in a row. Remove /^#if.*\n#endif.*\n#include\s+<sys/cdefs.h>.*\n/ Remove /\n+#include\s+<sys/cdefs.h>.*\n+#if.*\n#endif.*\n+/ Remove /\n+#if.*\n#endif.*\n+/ Remove /^#if.*\n#endif.*\n/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/types.h>/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/param.h>/ Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/capsicum.h>/ Sponsored by: Netflix
144 lines
4.1 KiB
C
144 lines
4.1 KiB
C
/*-
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* Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by BAE Systems, the University of Cambridge
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* Computer Laboratory, and Memorial University under DARPA/AFRL contract
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* FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing
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* (TC) research program.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kthread.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#define GCC_QDSS_BCR 0x29000
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#define GCC_QDSS_BCR_BLK_ARES (1 << 0) /* Async software reset. */
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#define GCC_QDSS_CFG_AHB_CBCR 0x29008
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#define AHB_CBCR_CLK_ENABLE (1 << 0) /* AHB clk branch ctrl */
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#define GCC_QDSS_ETR_USB_CBCR 0x29028
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#define ETR_USB_CBCR_CLK_ENABLE (1 << 0) /* ETR USB clk branch ctrl */
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#define GCC_QDSS_DAP_CBCR 0x29084
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#define DAP_CBCR_CLK_ENABLE (1 << 0) /* DAP clk branch ctrl */
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static struct ofw_compat_data compat_data[] = {
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{ "qcom,gcc-msm8916", 1 },
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{ NULL, 0 }
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};
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struct qcom_gcc_softc {
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struct resource *res;
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};
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static struct resource_spec qcom_gcc_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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/*
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* Qualcomm Debug Subsystem (QDSS)
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* block enabling routine.
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*/
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static void
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qcom_qdss_enable(struct qcom_gcc_softc *sc)
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{
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/* Put QDSS block to reset */
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bus_write_4(sc->res, GCC_QDSS_BCR, GCC_QDSS_BCR_BLK_ARES);
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/* Enable AHB clock branch */
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bus_write_4(sc->res, GCC_QDSS_CFG_AHB_CBCR, AHB_CBCR_CLK_ENABLE);
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/* Enable DAP clock branch */
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bus_write_4(sc->res, GCC_QDSS_DAP_CBCR, DAP_CBCR_CLK_ENABLE);
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/* Enable ETR USB clock branch */
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bus_write_4(sc->res, GCC_QDSS_ETR_USB_CBCR, ETR_USB_CBCR_CLK_ENABLE);
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/* Out of reset */
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bus_write_4(sc->res, GCC_QDSS_BCR, 0);
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}
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static int
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qcom_gcc_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Qualcomm Global Clock Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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qcom_gcc_attach(device_t dev)
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{
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struct qcom_gcc_softc *sc;
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sc = device_get_softc(dev);
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if (bus_alloc_resources(dev, qcom_gcc_spec, &sc->res) != 0) {
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device_printf(dev, "cannot allocate resources for device\n");
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return (ENXIO);
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}
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/*
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* Enable debug unit.
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* This is required for Coresight operation.
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* This also enables USB clock branch.
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*/
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qcom_qdss_enable(sc);
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return (0);
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}
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static device_method_t qcom_gcc_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, qcom_gcc_probe),
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DEVMETHOD(device_attach, qcom_gcc_attach),
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DEVMETHOD_END
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};
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static driver_t qcom_gcc_driver = {
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"qcom_gcc",
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qcom_gcc_methods,
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sizeof(struct qcom_gcc_softc),
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};
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EARLY_DRIVER_MODULE(qcom_gcc, simplebus, qcom_gcc_driver, 0, 0,
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BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
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MODULE_VERSION(qcom_gcc, 1);
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