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f242c47ee2
As with watchpoints allow the kernel debugger to set hardware breakpoints on arm64. These have been tested to work in both the ddb and gdb backends. Reviewed by: jhb (earlier version) Sponsored by: Arm Ltd Sponsored by: Innovate UK Differential Revision: https://reviews.freebsd.org/D44355
130 lines
5.5 KiB
C
130 lines
5.5 KiB
C
/*-
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* Copyright (c) 2014 Andrew Turner
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* Copyright (c) 2014-2015 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Semihalf under
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* sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _MACHINE_DB_MACHDEP_H_
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#define _MACHINE_DB_MACHDEP_H_
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#include <machine/armreg.h>
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#include <machine/frame.h>
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#include <machine/trap.h>
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#define T_BREAKPOINT (EXCP_BRK)
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#define T_HW_BREAKPOINT (EXCP_BRKPT_EL1)
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#define T_SINGLESTEP (EXCP_SOFTSTP_EL1)
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#define T_WATCHPOINT (EXCP_WATCHPT_EL1)
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#define HAS_HW_BREAKPOINT
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#define NHBREAKPOINTS 16
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typedef vm_offset_t db_addr_t;
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typedef long db_expr_t;
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#define PC_REGS() ((db_addr_t)kdb_thrctx->pcb_x[PCB_LR])
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#define BKPT_INST (0xd4200000)
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#define BKPT_SIZE (4)
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#define BKPT_SET(inst) (BKPT_INST)
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#define BKPT_SKIP do { \
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kdb_frame->tf_elr += BKPT_SIZE; \
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kdb_thrctx->pcb_x[PCB_LR] += BKPT_SIZE; \
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} while (0)
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#define db_clear_single_step kdb_cpu_clear_singlestep
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#define db_set_single_step kdb_cpu_set_singlestep
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#define IS_BREAKPOINT_TRAP(type, code) \
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(type == T_BREAKPOINT || type == T_HW_BREAKPOINT)
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#define IS_SSTEP_TRAP(type, code) (type == T_SINGLESTEP)
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#define IS_WATCHPOINT_TRAP(type, code) (type == T_WATCHPOINT)
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#define inst_trap_return(ins) (0)
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/* ret */
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#define inst_return(ins) (((ins) & 0xfffffc1fu) == 0xd65f0000)
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#define inst_call(ins) (((ins) & 0xfc000000u) == 0x94000000u || /* BL */ \
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((ins) & 0xfffffc1fu) == 0xd63f0000u) /* BLR */
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#define inst_load(ins) ({ \
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uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE); \
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is_load_instr(tmp_instr); \
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})
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#define inst_store(ins) ({ \
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uint32_t tmp_instr = db_get_value(PC_REGS(), sizeof(uint32_t), FALSE); \
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is_store_instr(tmp_instr); \
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})
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#define is_load_instr(ins) ((((ins) & 0x3b000000u) == 0x18000000u) || /* literal */ \
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(((ins) & 0x3f400000u) == 0x08400000u) || /* exclusive */ \
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(((ins) & 0x3bc00000u) == 0x28400000u) || /* no-allocate pair */ \
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((((ins) & 0x3b200c00u) == 0x38000400u) && \
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(((ins) & 0x3be00c00u) != 0x38000400u) && \
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(((ins) & 0xffe00c00u) != 0x3c800400u)) || /* immediate post-indexed */ \
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((((ins) & 0x3b200c00u) == 0x38000c00u) && \
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(((ins) & 0x3be00c00u) != 0x38000c00u) && \
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(((ins) & 0xffe00c00u) != 0x3c800c00u)) || /* immediate pre-indexed */ \
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((((ins) & 0x3b200c00u) == 0x38200800u) && \
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(((ins) & 0x3be00c00u) != 0x38200800u) && \
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(((ins) & 0xffe00c00u) != 0x3ca00c80u)) || /* register offset */ \
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((((ins) & 0x3b200c00u) == 0x38000800u) && \
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(((ins) & 0x3be00c00u) != 0x38000800u)) || /* unprivileged */ \
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((((ins) & 0x3b200c00u) == 0x38000000u) && \
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(((ins) & 0x3be00c00u) != 0x38000000u) && \
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(((ins) & 0xffe00c00u) != 0x3c800000u)) || /* unscaled immediate */ \
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((((ins) & 0x3b000000u) == 0x39000000u) && \
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(((ins) & 0x3bc00000u) != 0x39000000u) && \
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(((ins) & 0xffc00000u) != 0x3d800000u)) || /* unsigned immediate */ \
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(((ins) & 0x3bc00000u) == 0x28400000u) || /* pair (offset) */ \
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(((ins) & 0x3bc00000u) == 0x28c00000u) || /* pair (post-indexed) */ \
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(((ins) & 0x3bc00000u) == 0x29800000u)) /* pair (pre-indexed) */
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#define is_store_instr(ins) ((((ins) & 0x3f400000u) == 0x08000000u) || /* exclusive */ \
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(((ins) & 0x3bc00000u) == 0x28000000u) || /* no-allocate pair */ \
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((((ins) & 0x3be00c00u) == 0x38000400u) || \
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(((ins) & 0xffe00c00u) == 0x3c800400u)) || /* immediate post-indexed */ \
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((((ins) & 0x3be00c00u) == 0x38000c00u) || \
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(((ins) & 0xffe00c00u) == 0x3c800c00u)) || /* immediate pre-indexed */ \
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((((ins) & 0x3be00c00u) == 0x38200800u) || \
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(((ins) & 0xffe00c00u) == 0x3ca00800u)) || /* register offset */ \
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(((ins) & 0x3be00c00u) == 0x38000800u) || /* unprivileged */ \
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((((ins) & 0x3be00c00u) == 0x38000000u) || \
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(((ins) & 0xffe00c00u) == 0x3c800000u)) || /* unscaled immediate */ \
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((((ins) & 0x3bc00000u) == 0x39000000u) || \
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(((ins) & 0xffc00000u) == 0x3d800000u)) || /* unsigned immediate */ \
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(((ins) & 0x3bc00000u) == 0x28000000u) || /* pair (offset) */ \
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(((ins) & 0x3bc00000u) == 0x28800000u) || /* pair (post-indexed) */ \
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(((ins) & 0x3bc00000u) == 0x29800000u)) /* pair (pre-indexed) */
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#define next_instr_address(pc, bd) ((bd) ? (pc) : ((pc) + 4))
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#define DB_ELFSIZE 64
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#endif /* !_MACHINE_DB_MACHDEP_H_ */
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