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6c59ac8c79
Applies only to bare-metal Zen2 processors. The system currently
automatically applies it to all of them.
Tunable/sysctl 'machdep.mitigations.zenbleed.enable' can be used to
forcibly enable or disable the mitigation at boot or run-time. Possible
values are:
0: Mitigation disabled
1: Mitigation enabled
2: Run the automatic determination.
Currently, value 2 is the default and has identical effect as value 1.
This might change in the future if we choose to take into account
microcode revisions in the automatic determination process.
The tunable/sysctl value is simply ignored on non-applicable CPU models,
which is useful to apply the same configuration on a set of machines
that do not all have Zen2 processors. Trying to set it to any integer
value not listed above is silently equivalent to setting it to value 2
(automatic determination).
The current mitigation state can be queried through sysctl
'machdep.mitigations.zenbleed.state', which returns "Not applicable",
"Mitigation enabled" or "Mitigation disabled". Note that this state is
not guaranteed to be accurate in case of intervening modifications of
the corresponding chicken bit directly via cpuctl(4) (this includes the
cpucontrol(8) utility). Resetting the desired policy through
'machdep.mitigations.zenbleed.enable' (possibly to its current value)
will reset the hardware state and ensure that the reported state is
again coherent with it.
Reviewed by: kib
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D41817
(cherry picked from commit ebaea1bcd2)
185 lines
5.8 KiB
C
185 lines
5.8 KiB
C
/*-
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* Copyright (c) 1995 Bruce D. Evans.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _X86_X86_VAR_H_
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#define _X86_X86_VAR_H_
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/*
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* Miscellaneous machine-dependent declarations.
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*/
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extern long Maxmem;
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extern u_int basemem;
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extern u_int cpu_exthigh;
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extern u_int cpu_feature;
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extern u_int cpu_feature2;
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extern u_int amd_feature;
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extern u_int amd_feature2;
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extern u_int amd_rascap;
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extern u_int amd_pminfo;
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extern u_int amd_extended_feature_extensions;
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extern u_int via_feature_rng;
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extern u_int via_feature_xcrypt;
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extern u_int cpu_clflush_line_size;
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extern u_int cpu_stdext_feature;
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extern u_int cpu_stdext_feature2;
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extern u_int cpu_stdext_feature3;
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extern uint64_t cpu_ia32_arch_caps;
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extern u_int cpu_high;
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extern u_int cpu_id;
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extern u_int cpu_max_ext_state_size;
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extern u_int cpu_mxcsr_mask;
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extern u_int cpu_procinfo;
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extern u_int cpu_procinfo2;
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extern char cpu_vendor[];
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extern u_int cpu_vendor_id;
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extern u_int cpu_mon_mwait_flags;
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extern u_int cpu_mon_min_size;
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extern u_int cpu_mon_max_size;
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extern u_int cpu_maxphyaddr;
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extern u_int cpu_power_eax;
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extern u_int cpu_power_ebx;
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extern u_int cpu_power_ecx;
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extern u_int cpu_power_edx;
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extern u_int hv_base;
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extern u_int hv_high;
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extern char hv_vendor[];
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extern char kstack[];
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extern char sigcode[];
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extern int szsigcode;
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extern int workaround_erratum383;
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extern int _udatasel;
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extern int _ucodesel;
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extern int _ucode32sel;
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extern int _ufssel;
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extern int _ugssel;
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extern int use_xsave;
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extern uint64_t xsave_mask;
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extern u_int max_apic_id;
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extern int i386_read_exec;
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extern int pti;
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extern int hw_ibrs_ibpb_active;
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extern int hw_mds_disable;
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extern int hw_ssb_active;
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extern int x86_taa_enable;
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extern int cpu_flush_rsb_ctxsw;
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extern int x86_rngds_mitg_enable;
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extern int zenbleed_enable;
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extern int cpu_amdc1e_bug;
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extern char bootmethod[16];
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struct pcb;
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struct thread;
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struct reg;
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struct fpreg;
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struct dbreg;
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struct dumperinfo;
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struct trapframe;
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struct minidumpstate;
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/*
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* The interface type of the interrupt handler entry point cannot be
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* expressed in C. Use simplest non-variadic function type as an
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* approximation.
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*/
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typedef void alias_for_inthand_t(void);
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bool acpi_get_fadt_bootflags(uint16_t *flagsp);
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void *alloc_fpusave(int flags);
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u_int cpu_auxmsr(void);
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vm_paddr_t cpu_getmaxphyaddr(void);
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bool cpu_mwait_usable(void);
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void cpu_probe_amdc1e(void);
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void cpu_setregs(void);
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int dbreg_set_watchpoint(vm_offset_t addr, vm_size_t size, int access);
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int dbreg_clr_watchpoint(vm_offset_t addr, vm_size_t size);
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void dbreg_list_watchpoints(void);
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void x86_clear_dbregs(struct pcb *pcb);
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bool disable_wp(void);
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void restore_wp(bool old_wp);
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void finishidentcpu(void);
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void identify_cpu1(void);
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void identify_cpu2(void);
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void identify_cpu_ext_features(void);
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void identify_cpu_fixup_bsp(void);
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void identify_hypervisor(void);
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void initializecpu(void);
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void initializecpucache(void);
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bool fix_cpuid(void);
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void fillw(int /*u_short*/ pat, void *base, size_t cnt);
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int isa_nmi(int cd);
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void handle_ibrs_entry(void);
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void handle_ibrs_exit(void);
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void hw_ibrs_recalculate(bool all_cpus);
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void hw_mds_recalculate(void);
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void hw_ssb_recalculate(bool all_cpus);
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void x86_taa_recalculate(void);
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void x86_rngds_mitg_recalculate(bool all_cpus);
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void zenbleed_sanitize_enable(void);
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void zenbleed_check_and_apply(bool all_cpus);
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void nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame);
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void nmi_call_kdb_smp(u_int type, struct trapframe *frame);
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void nmi_handle_intr(u_int type, struct trapframe *frame);
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void pagecopy(void *from, void *to);
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void printcpuinfo(void);
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int pti_get_default(void);
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int user_dbreg_trap(register_t dr6);
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int cpu_minidumpsys(struct dumperinfo *, const struct minidumpstate *);
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struct pcb *get_pcb_td(struct thread *td);
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void x86_set_fork_retval(struct thread *td);
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uint64_t rdtsc_ordered(void);
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/*
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* MSR ops for x86_msr_op()
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*/
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#define MSR_OP_ANDNOT 0x00000001
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#define MSR_OP_OR 0x00000002
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#define MSR_OP_WRITE 0x00000003
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#define MSR_OP_READ 0x00000004
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/*
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* Where and which execution mode
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*/
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#define MSR_OP_LOCAL 0x10000000
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#define MSR_OP_SCHED_ALL 0x20000000
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#define MSR_OP_SCHED_ONE 0x30000000
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#define MSR_OP_RENDEZVOUS_ALL 0x40000000
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#define MSR_OP_RENDEZVOUS_ONE 0x50000000
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#define MSR_OP_CPUID(id) ((id) << 8)
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void x86_msr_op(u_int msr, u_int op, uint64_t arg1, uint64_t *res);
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#if defined(__i386__) && defined(INVARIANTS)
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void trap_check_kstack(void);
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#else
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#define trap_check_kstack()
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#endif
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#endif
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