Commit graph

13 commits

Author SHA1 Message Date
Brooks Davis 312a05c39e riscv: remove more riscv64sf support
Remove a few more bits of riscv64sf support in libc and libm.

Reduce floating point ABI checks to requiring double hard float.

Reviewed by:	imp, jhb
Fixes:		1ca12bd927 Remove the riscv64sf architecture.
Differential Revision:	https://reviews.freebsd.org/D44334
2024-03-21 23:48:37 +00:00
Brooks Davis 1947a9383e msun/riscv: expose fe{disable,enable}except
This is required for GCC to build.

PR:		272759
Reported by:	dgilbert@eicat.ca
Submitted by:	jrtc27
Differential Revision:	https://reviews.freebsd.org/D44333
2024-03-21 23:48:37 +00:00
Warner Losh d0b2dbfa0e Remove $FreeBSD$: one-line sh pattern
Remove /^\s*#[#!]?\s*\$FreeBSD\$.*$\n/
2023-08-16 11:55:03 -06:00
Warner Losh 42b388439b Remove $FreeBSD$: one-line .h pattern
Remove /^\s*\*+\s*\$FreeBSD\$.*$\n/
2023-08-16 11:54:23 -06:00
Warner Losh b3e7694832 Remove $FreeBSD$: two-line .h pattern
Remove /^\s*\*\n \*\s+\$FreeBSD\$$\n/
2023-08-16 11:54:16 -06:00
Alex Richardson dd5ed53a2f RISC-V: Fix feenableexcept return value
The man page says "The feenableexcept(), fedisableexcept(), and
fegetexcept() functions return a bitmap of the exceptions that were
unmasked prior to the call.", so we should return zero not -1.

Reviewed By:	mhorne
MFC after:	3 days
Differential Revision: https://reviews.freebsd.org/D29386
2021-03-25 11:16:20 +00:00
Alex Richardson 15211f1950 Silence unused parameter warnings in the RISC-V fenv.h
After increasing the lib/msun/tests WARNS to 6, this triggers a
compilation error for RISC-V.

Fixes:		87d65c747a ("lib/msun: Allow building tests with WARNS=6")
Reported by:	Jenkins
2021-03-22 17:49:24 +00:00
Brooks Davis 3b05ffaf6f Replace SOFTFLOAT with __riscv_float_abi_*.
With SOFTFLOAT, libc and libm were built correctly, but any program
including fenv.h itself assumed it was on a hardfloat systen and emitted
inline fpu instructions for fedisableexcept() and friends.

Unlike r315424 which did this for MIPS, I've used riscv_float_abi_soft
and riscv_float_abi_double macros as appropriate rather than using
__riscv_float_abi_soft exclusively.  This ensures that attempts to use an
unsupported hardfloat ABI will fail.

Reviewed by:	br
Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D10039
2018-04-19 20:36:15 +00:00
Ed Maste 2737721014 libm: remove duplicate version script entries
These symbols already appear in the common lib/msun/Symbol.map.
Duplicate entries produce an error with LLVM's LLD linker.

Reviewed by:	br
MFC after:	1 week
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D8627
2016-11-29 18:40:24 +00:00
Ruslan Bukin 7804dd5212 Add full softfloat and hardfloat support for RISC-V.
Hardfloat is now default (use riscv64sf as TARGET_ARCH
for softfloat).

Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D8529
2016-11-16 15:21:32 +00:00
Ruslan Bukin 2ad1d09f16 o Add support for long double.
o Add support for latest RISC-V GNU toolchain.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-11-03 13:06:17 +00:00
Ruslan Bukin 4bf1032a04 Add fenv.c for RISC-V. Copied from MIPS. 2016-01-26 14:40:41 +00:00
Ruslan Bukin 1fdcc5e5c0 Start support for the RISC-V 64-bit architecture developed by UC Berkeley.
RISC-V is a new ISA designed to support computer research and education, and
is now become a standard open architecture for industry implementations.

This is a minimal set of changes required to run 'make kernel-toolchain'
using external (GNU) toolchain.

The FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv.

Reviewed by:	andrew, bdrewery, emaste, imp
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
Differential Revision:	https://reviews.freebsd.org/D4445
2015-12-11 22:55:23 +00:00