I have an 82559 card with the same id as the other 8255[78] chips, but
that was made with a date code of 0699 (June 99). The submitter shows
this working with the probe etc, but doesn't actually say it works as
on the ethernet. :-) Assuming it does, this is a RELENG_3 merge candidate.
Submitted by: Steven E Lumos <slumos@sam.ISRI.UNLV.EDU>
the Davicom DM9100 and DM9102 chipsets, including the Jaton Corporation
XPressNet. Datasheet is available from www.davicom8.com.
The DM910x chips are still more tulip clones. The API is reproduced
pretty faithfully, unfortunately the performance is pretty bad. The
transmitter seems to have a lot of problems DMAing multi-fragment
packets. The only way to make it work reliably is to coalesce transmitted
packets into a single contiguous buffer. The Linux driver (written by
Davicom) actually does something similar to this. I can't recomment this
NIC as anything more than a "connectivity solution."
This driver uses newbus and miibus and is supported on both i386
and alpha platforms.
SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the
SiS chips can be found at www.sis.com.tw.
This is a fairly simple chipset. The receiver uses a 128-bit multicast
hash table and single perfect entry for the station address. Transmit and
receive DMA and FIFO thresholds are easily tuneable. Documentation is
pretty decent and performance is not bad, even on my crufty 486. This
driver uses newbus and miibus and is supported on both the i386 and
alpha architectures.
Doug Rabson's work, with a few tweaks from Warner Losh and I. There are
still some quirks to resolve, but the old driver is presently breaking
the build.
Fix a bug where video capture locks up on channel changes.
Many thanks to Juha for solving this.
Submitted by: Juha Nurmela <Juha.Nurmela@quicknet.inet.fi>
external NatSemi PHY chip was programmed to respond to MII address 24.
In the 3c905B ASICs, the transceiver is internal but it's still mapped
to MII address 24. But *some* 3Com 3c905B ASIC revisions map the
transceiver control registers to *all* MII addresses (0 through 31).
The miibus code probes for PHYs at all MII addresses and because of
this unusual behavior, it will attempt to map the same PHY registers
several times over, which doesn't work.
Naturally, the 3c905B NIC that I tested happened not to exhibit this
behavior.
The fix is to tweak xl_miibus_readreg() and xl_miibus_writereg()
to only respond when attempting to read from MII address 24. This
is safe to do since the 3Com documentation indicates that the PHY
and/or internal transceiver will always be mapped to address 24,
and there are no 3Com XL NICs with more than one PHY.
New Features:
Greatly improved VBI capture support. (mainly for the AleVT port)
Supports select() on /dev/vbi
Improved RISC program for RGB+VBI capture to capture both evenodd
VBI data even when only capturing even only (or odd only) video
Based on code from Juha Nurmela <Juha.Nurmela@quicknet.inet.fi>
Support for Hauppauge 627 and Temic 4006
Submitted by: Maurice Castro <maurice@atum.castro.aus.net>
Bug Fix:
Fix bug in AverMedia card detection.
Break out the detection logic for the aic7855 and properly report
these chips as 7855s instead of 7850s.
The 2940AU_CN is an aic7860 based card, not aic7860.
Not setting CACHETHEN turned out to be a bad idea. It can cause
spurious corruption under heavy PCI load with multiple masters.
due to the fact that there are non-MII cards supported by the same
driver and I don't have all of the cards available for testing. There's
also the 3c905B-COMBO which has MII, AUI and BNC media ports all in one
package. Supporting the COMBO is difficult because we have to add the
10base5 and 10base2 media types to the same ifmedia struct as the
MII-attached types, however there is no way to force the miibus and
child PHYs into existence before xl_attach() completes, so there is
no ifmedia struct available in xl_attach(). What we do inistead is
use the mediainit method as a callback: when a child PHY is attached,
it calls the miibus mediainit routine which selects a default media.
This routing also calls the NIC driver's mediainit method (if it
implements one) at which point we can safely add the other media
types.
This fixes, at least, panics in ncr_attach() on i386's with about 5MB
of memory. The restriction was a hack to leave some low memory for ISA
DMA, but on i386's we now allocate pages from the top down, so all the
restriction did was cause our allocations to fail when there is no free
memory above 1MB.
had to get the ML 6692 PHY driver working correctly, which is harder than
it sounds. "Bitrate" ThunderLAN devices should still be supported (i.e
the older 10Mbps Netflex 3/P, which use the TNETE110 chip that has no
MII support). The ThunderLAN has an internal PHY which makes things a
little complicated, but these are the basic rules:
- For devices with just the ThunderLAN, the internal PHY is used to
provide 10baseT, and 10base5/10baseT support. Autonegotiation will
work, but only with 10baseT links. The only thing that really gets
negotiated is whether the link is full or half duplex.
- For devices with the ThunderLAN and an external 10/100 PHY (like the
Compaq Netelligent 100Mbps cards, or the internal Netflex 3/P with
100Mbps upgrade daughter card), the external PHY is used for 10baseT
and 100baseTX modes. The internal PHY is still used to support
10base5/10base2, though you have to select them manual with ifconfig.
- For devices with the ThunderLAN and the ML6692 PHY, both the internal
and external PHYs are used, though it will appear as though the 6692
PHY will be used to support 10baseT and 100baseTX modes. In reality,
the internal PHY will be used for 10baseT, but this fact will be hidden
from the user. The 10base5/10base2 modes can also be selected manually
as with above.
in 4 byte chunks. It turns out that with the 82c169C on the Netgear
FA-310TX Rev D2, if you tell the chip you have reserved a buffer of 1518
bytes, it will actually treat it as 1516 bytes since 1518 is divisible
by four. Consequently, a packet of 1514 bytes will always end up consuming
two buffers: the last coupleof bytes will spill over into the next
descriptor. This causes the pn_rx_bug_war() routine to trip unnecessarily.
I'm not sure if the 82c169B or 82c168 chips behave the same way; I'll
have to check them. In any case, this change should work just as well
with them. Note that the FA-310TX Rev D2 also has a Broadcom PHY
instead of a Level One LXT970 PHY, however this shouldn't make any
difference as far as the driver is concerned.
This change also allows me to do a way with one rounding overation in
pn_rx-buf_war().
Diskslice/label code not yet handled.
Vinum, i4b, alpha, pc98 not dealt with (left to respective Maintainers)
Add the correct hook for devfs to kern_conf.c
The net result of this excercise is that a lot less files depends on DEVFS,
and devtoname() gets more sensible output in many cases.
A few drivers had minor additional cleanups performed relating to cdevsw
registration.
A few drivers don't register a cdevsw{} anymore, but only use make_dev().
PCI fast ethernet controller. Currently, the only card I know that uses
this chip is the D-Link DFE-550TX. (Don't ask me where to buy these: the
only cards I have are samples sent to me by D-Link.)
This driver is the first to make use of the miibus code once I'm sure
it all works together nicely, I'll start converting the other drivers.
The Sundance chip is a clone of the 3Com 3c90x Etherlink XL design
only with its own register layout. Support is provided for ifmedia,
hardware multicast filtering, bridging and promiscuous mode.
events, in order to pave the way for removing a number of the ad-hoc
implementations currently in use.
Retire the at_shutdown family of functions and replace them with
new event handler lists.
Rework kern_shutdown.c to take greater advantage of the use of event
handlers.
Reviewed by: green
to achieve a delay is pretty mean.
Andrew reports:
"The tulip_delay_300ns() is, well, bloody stupid on machines with a
heavily loaded PCI bus. It tries to do a delay by assuming PCI reads
will take a certain amount of time & issues a large amount of
(expensive, 5% CPU when your PCI bus is heavily loaded) pci reads.
Locally, we've replaced the calls to tulip_delay_300ns(sc) in the EMIT
macros with a simple DELAY(1) and not seen any problems. Plus we've
gained about 50Mb/sec throughput on our gigabit network cards because
of the added PCI bus bandwidth available."
Also, I do not understand why, but this change appears to stop the
Transmit Fifo underrun on one of my systems (but not the Alpha PC164SX).
This shouldn't make that much of a difference since the mii bus isn't
touched all that often, but perhaps when it does get accessed and hence
hammers the register, it was causing the chip to get upset.
Submitted by: Andrew Gallatin <gallatin@cs.duke.edu>
the aic7890/91/96/97 cards. This could cause the system to go into
a long retry/recovery loop during probe.
Fix the alignment argument to bus_dma_tag_create().
Don't set the CACHETHEN bit in dscommand0 for Ultra2 controllers
until we know more about its behavior. The description for this
bit makes it sound like it could cause problems with certain
PCI chipsets.
