From ff9452772d2fbb1268af844ff4c0980942046546 Mon Sep 17 00:00:00 2001 From: Warner Losh Date: Tue, 17 Jul 2018 23:23:45 +0000 Subject: [PATCH] Remove kernel support for armeb Remove all the big-endian arm architectures (ixp425 and ixp435) support in the kernel and associated drivers. Differential Revision: https://reviews.freebsd.org/D16257 --- sys/arm/arm/cpufunc.c | 28 +- sys/arm/arm/elf_trampoline.c | 2 +- sys/arm/arm/identcpu-v4.c | 18 - sys/arm/conf/AVILA | 147 -- sys/arm/conf/AVILA.hints | 53 - sys/arm/conf/CAMBRIA | 141 -- sys/arm/conf/CAMBRIA.hints | 75 - sys/arm/conf/NOTES | 4 - sys/arm/conf/NSLU | 107 -- sys/arm/conf/NSLU.hints | 38 - sys/arm/include/cpufunc.h | 8 +- sys/arm/include/intr.h | 3 +- sys/arm/include/pmap-v4.h | 3 +- sys/arm/xscale/ixp425/avila_ata.c | 553 ------- sys/arm/xscale/ixp425/avila_gpio.c | 371 ----- sys/arm/xscale/ixp425/avila_led.c | 120 -- sys/arm/xscale/ixp425/avila_machdep.c | 419 ----- sys/arm/xscale/ixp425/cambria_exp_space.c | 260 --- sys/arm/xscale/ixp425/cambria_fled.c | 112 -- sys/arm/xscale/ixp425/cambria_gpio.c | 505 ------ sys/arm/xscale/ixp425/cambria_led.c | 135 -- sys/arm/xscale/ixp425/files.avila | 10 - sys/arm/xscale/ixp425/files.ixp425 | 46 - sys/arm/xscale/ixp425/if_npe.c | 1781 --------------------- sys/arm/xscale/ixp425/if_npereg.h | 283 ---- sys/arm/xscale/ixp425/ixdp425_pci.c | 169 -- sys/arm/xscale/ixp425/ixdp425reg.h | 50 - sys/arm/xscale/ixp425/ixp425.c | 692 -------- sys/arm/xscale/ixp425/ixp425_a4x_io.S | 152 -- sys/arm/xscale/ixp425/ixp425_a4x_space.c | 116 -- sys/arm/xscale/ixp425/ixp425_iic.c | 197 --- sys/arm/xscale/ixp425/ixp425_intr.h | 90 -- sys/arm/xscale/ixp425/ixp425_mem.c | 104 -- sys/arm/xscale/ixp425/ixp425_npe.c | 1574 ------------------ sys/arm/xscale/ixp425/ixp425_npereg.h | 429 ----- sys/arm/xscale/ixp425/ixp425_npevar.h | 124 -- sys/arm/xscale/ixp425/ixp425_pci.c | 477 ------ sys/arm/xscale/ixp425/ixp425_pci_asm.S | 108 -- sys/arm/xscale/ixp425/ixp425_pci_space.c | 481 ------ sys/arm/xscale/ixp425/ixp425_qmgr.c | 1104 ------------- sys/arm/xscale/ixp425/ixp425_qmgr.h | 247 --- sys/arm/xscale/ixp425/ixp425_space.c | 125 -- sys/arm/xscale/ixp425/ixp425_timer.c | 266 --- sys/arm/xscale/ixp425/ixp425_wdog.c | 117 -- sys/arm/xscale/ixp425/ixp425reg.h | 710 -------- sys/arm/xscale/ixp425/ixp425var.h | 124 -- sys/arm/xscale/ixp425/std.avila | 20 - sys/arm/xscale/ixp425/std.ixp425 | 5 - sys/arm/xscale/ixp425/std.ixp435 | 7 - sys/arm/xscale/ixp425/uart_bus_ixp425.c | 84 - sys/arm/xscale/ixp425/uart_cpu_ixp425.c | 98 -- sys/arm/xscale/std.xscale-be | 5 - sys/conf/files.arm | 4 +- sys/conf/kern.mk | 1 - sys/conf/options.arm | 3 - sys/dev/cfi/cfi_bus_ixp4xx.c | 82 - sys/dev/hwpmc/hwpmc_xscale.h | 3 - sys/dev/usb/controller/ehci_ixp4xx.c | 323 ---- sys/modules/cfi/Makefile | 9 +- 59 files changed, 14 insertions(+), 13308 deletions(-) delete mode 100644 sys/arm/conf/AVILA delete mode 100644 sys/arm/conf/AVILA.hints delete mode 100644 sys/arm/conf/CAMBRIA delete mode 100644 sys/arm/conf/CAMBRIA.hints delete mode 100644 sys/arm/conf/NSLU delete mode 100644 sys/arm/conf/NSLU.hints delete mode 100644 sys/arm/xscale/ixp425/avila_ata.c delete mode 100644 sys/arm/xscale/ixp425/avila_gpio.c delete mode 100644 sys/arm/xscale/ixp425/avila_led.c delete mode 100644 sys/arm/xscale/ixp425/avila_machdep.c delete mode 100644 sys/arm/xscale/ixp425/cambria_exp_space.c delete mode 100644 sys/arm/xscale/ixp425/cambria_fled.c delete mode 100644 sys/arm/xscale/ixp425/cambria_gpio.c delete mode 100644 sys/arm/xscale/ixp425/cambria_led.c delete mode 100644 sys/arm/xscale/ixp425/files.avila delete mode 100644 sys/arm/xscale/ixp425/files.ixp425 delete mode 100644 sys/arm/xscale/ixp425/if_npe.c delete mode 100644 sys/arm/xscale/ixp425/if_npereg.h delete mode 100644 sys/arm/xscale/ixp425/ixdp425_pci.c delete mode 100644 sys/arm/xscale/ixp425/ixdp425reg.h delete mode 100644 sys/arm/xscale/ixp425/ixp425.c delete mode 100644 sys/arm/xscale/ixp425/ixp425_a4x_io.S delete mode 100644 sys/arm/xscale/ixp425/ixp425_a4x_space.c delete mode 100644 sys/arm/xscale/ixp425/ixp425_iic.c delete mode 100644 sys/arm/xscale/ixp425/ixp425_intr.h delete mode 100644 sys/arm/xscale/ixp425/ixp425_mem.c delete mode 100644 sys/arm/xscale/ixp425/ixp425_npe.c delete mode 100644 sys/arm/xscale/ixp425/ixp425_npereg.h delete mode 100644 sys/arm/xscale/ixp425/ixp425_npevar.h delete mode 100644 sys/arm/xscale/ixp425/ixp425_pci.c delete mode 100644 sys/arm/xscale/ixp425/ixp425_pci_asm.S delete mode 100644 sys/arm/xscale/ixp425/ixp425_pci_space.c delete mode 100644 sys/arm/xscale/ixp425/ixp425_qmgr.c delete mode 100644 sys/arm/xscale/ixp425/ixp425_qmgr.h delete mode 100644 sys/arm/xscale/ixp425/ixp425_space.c delete mode 100644 sys/arm/xscale/ixp425/ixp425_timer.c delete mode 100644 sys/arm/xscale/ixp425/ixp425_wdog.c delete mode 100644 sys/arm/xscale/ixp425/ixp425reg.h delete mode 100644 sys/arm/xscale/ixp425/ixp425var.h delete mode 100644 sys/arm/xscale/ixp425/std.avila delete mode 100644 sys/arm/xscale/ixp425/std.ixp425 delete mode 100644 sys/arm/xscale/ixp425/std.ixp435 delete mode 100644 sys/arm/xscale/ixp425/uart_bus_ixp425.c delete mode 100644 sys/arm/xscale/ixp425/uart_cpu_ixp425.c delete mode 100644 sys/arm/xscale/std.xscale-be delete mode 100644 sys/dev/cfi/cfi_bus_ixp4xx.c delete mode 100644 sys/dev/usb/controller/ehci_ixp4xx.c diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c index 95729f69717f..639ae903551a 100644 --- a/sys/arm/arm/cpufunc.c +++ b/sys/arm/arm/cpufunc.c @@ -65,11 +65,6 @@ __FBSDID("$FreeBSD$"); #include #endif -#ifdef CPU_XSCALE_IXP425 -#include -#include -#endif - /* PRIMARY CACHE VARIABLES */ int arm_picache_size; int arm_picache_line_size; @@ -259,7 +254,7 @@ struct cpu_functions pj4bv7_cpufuncs = { }; #endif /* CPU_MV_PJ4B */ -#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) +#if defined(CPU_XSCALE_PXA2X0) struct cpu_functions xscale_cpufuncs = { /* CPU functions */ @@ -309,7 +304,7 @@ struct cpu_functions xscale_cpufuncs = { xscale_setup /* cpu setup */ }; #endif -/* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ +/* CPU_XSCALE_PXA2X0 */ #ifdef CPU_XSCALE_81342 struct cpu_functions xscalec3_cpufuncs = { @@ -467,7 +462,7 @@ u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore-v4.s */ #if defined(CPU_ARM9) || \ defined (CPU_ARM9E) || \ defined(CPU_ARM1176) || \ - defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ + defined(CPU_XSCALE_PXA2X0) || \ defined(CPU_FA526) || defined(CPU_MV_PJ4B) || \ defined(CPU_XSCALE_81342) || \ defined(CPU_CORTEXA) || defined(CPU_KRAIT) @@ -725,18 +720,6 @@ set_cpufuncs(void) goto out; } #endif /* CPU_XSCALE_PXA2X0 */ -#ifdef CPU_XSCALE_IXP425 - if (cputype == CPU_ID_IXP425_533 || cputype == CPU_ID_IXP425_400 || - cputype == CPU_ID_IXP425_266 || cputype == CPU_ID_IXP435) { - - cpufuncs = xscale_cpufuncs; - cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */ - get_cachetype_cp15(); - pmap_pte_init_xscale(); - - goto out; - } -#endif /* CPU_XSCALE_IXP425 */ /* * Bzzzz. And the answer was ... */ @@ -950,8 +933,7 @@ fa526_setup(void) } #endif /* CPU_FA526 */ -#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ - defined(CPU_XSCALE_81342) +#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_81342) void xscale_setup(void) { @@ -1017,4 +999,4 @@ xscale_setup(void) __asm __volatile("mcr p15, 0, %0, c1, c0, 1" : : "r" (auxctl)); } -#endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ +#endif /* CPU_XSCALE_PXA2X0 */ diff --git a/sys/arm/arm/elf_trampoline.c b/sys/arm/arm/elf_trampoline.c index 0d93998016d1..a43825b072c2 100644 --- a/sys/arm/arm/elf_trampoline.c +++ b/sys/arm/arm/elf_trampoline.c @@ -70,7 +70,7 @@ extern void fa526_idcache_wbinv_all(void); #elif defined(CPU_ARM9E) #define cpu_idcache_wbinv_all armv5_ec_idcache_wbinv_all extern void armv5_ec_idcache_wbinv_all(void); -#elif defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) +#elif defined(CPU_XSCALE_PXA2X0) #define cpu_idcache_wbinv_all xscale_cache_purgeID extern void xscale_cache_purgeID(void); #elif defined(CPU_XSCALE_81342) diff --git a/sys/arm/arm/identcpu-v4.c b/sys/arm/arm/identcpu-v4.c index 0be39020d27a..96472f1902fe 100644 --- a/sys/arm/arm/identcpu-v4.c +++ b/sys/arm/arm/identcpu-v4.c @@ -119,13 +119,6 @@ static const char * const pxa27x_steppings[16] = { "rev 12", "rev 13", "rev 14", "rev 15", }; -static const char * const ixp425_steppings[16] = { - "step 0 (A0)", "rev 1 (ARMv5TE)", "rev 2", "rev 3", - "rev 4", "rev 5", "rev 6", "rev 7", - "rev 8", "rev 9", "rev 10", "rev 11", - "rev 12", "rev 13", "rev 14", "rev 15", -}; - struct cpuidtab { u_int32_t cpuid; enum cpu_class cpu_class; @@ -200,17 +193,6 @@ const struct cpuidtab cpuids[] = { { CPU_ID_PXA210C, CPU_CLASS_XSCALE, "PXA210", pxa2x0_steppings }, - { CPU_ID_IXP425_533, CPU_CLASS_XSCALE, "IXP425 533MHz", - ixp425_steppings }, - { CPU_ID_IXP425_400, CPU_CLASS_XSCALE, "IXP425 400MHz", - ixp425_steppings }, - { CPU_ID_IXP425_266, CPU_CLASS_XSCALE, "IXP425 266MHz", - ixp425_steppings }, - - /* XXX ixp435 steppings? */ - { CPU_ID_IXP435, CPU_CLASS_XSCALE, "IXP435", - ixp425_steppings }, - { CPU_ID_MV88FR131, CPU_CLASS_MARVELL, "Feroceon 88FR131", generic_steppings }, diff --git a/sys/arm/conf/AVILA b/sys/arm/conf/AVILA deleted file mode 100644 index 958e1286ba27..000000000000 --- a/sys/arm/conf/AVILA +++ /dev/null @@ -1,147 +0,0 @@ -# AVILA -- Gateworks Avila XScale board -# kernel configuration file for FreeBSD/arm -# -# For more information on this file, please read the handbook section on -# Kernel Configuration Files: -# -# https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html -# -# The handbook is also available locally in /usr/share/doc/handbook -# if you've installed the doc distribution, otherwise always see the -# FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the -# latest information. -# -# An exhaustive list of options and more detailed explanations of the -# device lines is also present in the ../../conf/NOTES and NOTES files. -# If you are in doubt as to the purpose or necessity of a line, check first -# in NOTES. -# -# $FreeBSD$ - -ident AVILA - -include "std.arm" -include "../xscale/ixp425/std.ixp425" -# NB: memory mapping is defined in std.avila -include "../xscale/ixp425/std.avila" -options XSCALE_CACHE_READ_WRITE_ALLOCATE -#To statically compile in device wiring instead of /boot/device.hints -hints "AVILA.hints" # Default places to look for devices. -makeoptions MODULES_OVERRIDE="" - -makeoptions CONF_CFLAGS=-mcpu=xscale -#options HZ=1000 -options HZ=100 -options DEVICE_POLLING - -options SCHED_4BSD # 4BSD scheduler -options INET # InterNETworking -options TCP_HHOOK # hhook(9) framework for TCP -options GEOM_PART_BSD # BSD partition scheme -options GEOM_PART_MBR # MBR partition scheme -options TMPFS # Efficient memory filesystem -options FFS # Berkeley Fast Filesystem -options SOFTUPDATES # Enable FFS soft updates support -options NFSCL # Network Filesystem Client -options NFS_ROOT # NFS usable as /, requires NFSCL -options BOOTP -options BOOTP_NFSROOT -options BOOTP_NFSV3 -options BOOTP_WIRED_TO=npe0 -#options BOOTP_WIRED_TO=ath0 -#options BOOTP_WIRED_TO=rl0 -options BOOTP_COMPAT -#options PREEMPTION -#options VERBOSE_SYSINIT - -# Hardware performance counters -options HWPMC_HOOKS -device hwpmc - -#device saarm - -device pci -device uart - -device ixpwdog # watchdog timer -device cfi # flash support -device cfid # flash disk support -device geom_redboot # redboot fis parser - -# I2C Bus -device iicbus -device iicbb -device iic - -device ixpiic # I2C bus glue -device ds1672 # DS1672 on I2C bus -device ad7418 # AD7418 on I2C bus - -device avila_led - -device gpio -device gpioled -device avila_gpio # GPIO pins on J8 - -device ata -device avila_ata # Gateworks CF/IDE support - -device npe # Network Processing Engine -device npe_fw -device firmware -device qmgr # Q Manager (required by npe) -device mii # NB: required by npe -device ether -device bpf - -device loop -device if_bridge - -device md -device random # Entropy device - -# Wireless NIC cards -device wlan # 802.11 support -options IEEE80211_DEBUG -options IEEE80211_SUPPORT_TDMA -options IEEE80211_SUPPORT_MESH -device wlan_wep # 802.11 WEP support -device wlan_ccmp # 802.11 CCMP support -device wlan_tkip # 802.11 TKIP support -device wlan_xauth - -device ath # Atheros NICs -device ath_pci # Atheros pci/cardbus glue -options ATH_DEBUG -options ATH_DIAGAPI -#options ATH_TX99_DIAG -device ath_rate_sample # SampleRate tx rate control for ath - -#options AH_DEBUG -#options AH_ASSERT -#device ath_ar5210 -#device ath_ar5211 -device ath_ar5212 -device ath_rf2413 -device ath_rf2417 -device ath_rf2425 -device ath_rf5111 -device ath_rf5112 -device ath_rf5413 -# -device ath_ar5416 -options AH_SUPPORT_AR5416 -device ath_ar9160 -device ath_ar9280 - -device usb -device ohci -device ehci -device umass -device scbus # SCSI bus (required for ATA/SCSI) -device da # Direct Access (disks) -device pass # Passthrough device (direct ATA/SCSI access) - -#device ural -#device zyd -#device wlan_amrr diff --git a/sys/arm/conf/AVILA.hints b/sys/arm/conf/AVILA.hints deleted file mode 100644 index fc177a10623c..000000000000 --- a/sys/arm/conf/AVILA.hints +++ /dev/null @@ -1,53 +0,0 @@ -# $FreeBSD$ - -# -# Device wiring for the Gateworks Avila 2384. -# - -# DBGU is unit 0 -hint.uart.0.at="ixp0" -hint.uart.0.addr=0xc8000000 -hint.uart.0.irq=15 -hint.uart.0.flags=0x10 -hint.uart.0.ier_rxbits=0x5d # NB: need UUE+RTOIE -# USART0 is unit 1 -hint.uart.1.at="ixp0" -hint.uart.1.addr=0xc8001000 -hint.uart.1.irq=13 -hint.uart.1.ier_rxbits=0x5d # NB: need UUE+RTOIE - -# NPE Hardware Queue Manager -hint.ixpqmgr.0.at="ixp0" - -# NPE wired NICs, requires ixpqmgr -hint.npe.0.at="ixp0" -hint.npe.0.npeid="B" -hint.npe.0.mac="B" -hint.npe.0.mii="B" -hint.npe.0.phy=0 -hint.npe.1.at="ixp0" -hint.npe.1.npeid="C" -hint.npe.1.mac="C" -hint.npe.1.mii="B" -hint.npe.1.phy=1 - -# FLASH -hint.cfi.0.at="ixp0" -hint.cfi.0.addr=0x50000000 - -# CF IDE controller -hint.ata_avila.0.at="ixp0" - -# Front Panel LED -hint.led_avila.0.at="ixp0" - -# GPIO pins -hint.gpio_avila.0.at="ixp0" - -# Analog Devices AD7418 temperature sensor -hint.ad7418.0.at="iicbus0" -hint.ad7418.0.addr=0x50 - -# Dallas Semiconductor DS1672 RTC -hint.ds1672_rtc.0.at="iicbus0" -hint.ds1672_rtc.0.addr=0xd0 diff --git a/sys/arm/conf/CAMBRIA b/sys/arm/conf/CAMBRIA deleted file mode 100644 index 5f15c13ff3d0..000000000000 --- a/sys/arm/conf/CAMBRIA +++ /dev/null @@ -1,141 +0,0 @@ -# CAMBRIA -- Gateworks Cambria 235x boards -# kernel configuration file for FreeBSD/arm -# -# For more information on this file, please read the handbook section on -# Kernel Configuration Files: -# -# https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html -# -# The handbook is also available locally in /usr/share/doc/handbook -# if you've installed the doc distribution, otherwise always see the -# FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the -# latest information. -# -# An exhaustive list of options and more detailed explanations of the -# device lines is also present in the ../../conf/NOTES and NOTES files. -# If you are in doubt as to the purpose or necessity of a line, check first -# in NOTES. -# -# $FreeBSD$ - -ident CAMBRIA - -include "std.arm" -include "../xscale/ixp425/std.ixp435" -# NB: memory mapping is defined in std.avila -include "../xscale/ixp425/std.avila" -options XSCALE_CACHE_READ_WRITE_ALLOCATE -#To statically compile in device wiring instead of /boot/device.hints -hints "CAMBRIA.hints" # Default places to look for devices. - -makeoptions CONF_CFLAGS=-mcpu=xscale -makeoptions MODULES_OVERRIDE="" -#options HZ=1000 -options HZ=100 -options DEVICE_POLLING - -options SCHED_4BSD # 4BSD scheduler -#options PREEMPTION -options INET # InterNETworking -options TCP_HHOOK # hhook(9) framework for TCP -options GEOM_PART_BSD # BSD partition scheme -options GEOM_PART_MBR # MBR partition scheme -options TMPFS # Efficient memory filesystem -options FFS # Berkeley Fast Filesystem -options SOFTUPDATES # Enable FFS soft updates support -options NFSCL # Network Filesystem Client -options NFS_ROOT # NFS usable as /, requires NFSCL -options BOOTP -options BOOTP_NFSROOT -options BOOTP_NFSV3 -options BOOTP_WIRED_TO=npe0 -options BOOTP_COMPAT - -# Hardware performance counters -options HWPMC_HOOKS -device hwpmc - -#options VERBOSE_SYSINIT -options VERBOSE_INIT_ARM - -#device saarm - -device pci -device uart - -device ixpwdog # watchdog timer - -options IXP4XX_FLASH_SIZE=0x02000000 # stock 2358 comes w/ 32M -device cfi # flash support -device cfid # flash disk support -device geom_redboot # redboot fis parser - -# I2C Bus -device iicbus -device iicbb -device iic - -device ixpiic # I2C bus glue -device ds1672 # DS1672 on I2C bus -device ad7418 # AD7418 on I2C bus - -device cambria_fled # Font Panel LED on I2C bus -device cambria_led # 8-LED latch - -device gpio -device gpioled -device cambria_gpio # GPIO pins on J11 - -device ata -device avila_ata # Gateworks CF/IDE support - -device npe # Network Processing Engine -device npe_fw -device firmware -device qmgr # Q Manager (required by npe) -device mii # NB: required by npe -device ether -device bpf - -device loop -device if_bridge - -device md -device random # Entropy device - -# Wireless NIC cards -device wlan # 802.11 support -options IEEE80211_DEBUG -options IEEE80211_SUPPORT_TDMA -options IEEE80211_SUPPORT_MESH -device wlan_wep # 802.11 WEP support -device wlan_ccmp # 802.11 CCMP support -device wlan_tkip # 802.11 TKIP support -device wlan_xauth - -device ath # Atheros NICs -device ath_pci # Atheros pci/cardbus glue -options ATH_DEBUG -options ATH_DIAGAPI -options ATH_ENABLE_DFS -options ATH_ENABLE_11N -#options ATH_TX99_DIAG -device ath_rate_sample # SampleRate tx rate control for ath - -options AH_DEBUG -options AH_PRIVATE_DIAG -options AH_SUPPORT_AR5416 # NB: for 11n descriptor format -device ath_hal - -# NB: 2 USB 2.0 ports standard -device usb -options USB_EHCI_BIG_ENDIAN_DESC # handle big-endian byte order -device ehci -device umass -device scbus # SCSI bus (required for ATA/SCSI) -device da # Direct Access (disks) -device pass # Passthrough device (direct ATA/SCSI access) - -#device ural -#device zyd -#device wlan_amrr diff --git a/sys/arm/conf/CAMBRIA.hints b/sys/arm/conf/CAMBRIA.hints deleted file mode 100644 index 9384de4d9681..000000000000 --- a/sys/arm/conf/CAMBRIA.hints +++ /dev/null @@ -1,75 +0,0 @@ -# $FreeBSD$ - -# -# Device wiring for the Gateworks Cambria 2358. -# - -# DBGU is unit 0 -hint.uart.0.at="ixp0" -hint.uart.0.addr=0xc8000000 -hint.uart.0.irq=15 -hint.uart.0.flags=0x10 -hint.uart.0.ier_rxbits=0x5d # NB: need UUE+RTOIE - -# NB: no UART1 on ixp435 - -# optional GPS serial port -#hint.uart.1.at="ixp0" -#hint.uart.1.addr=0x53fc0000 -#hint.uart.1.irq=20 -#hint.uart.1.ier_rxbits=0x1 -#hint.uart.1.rclk=1843200 -# optional RS485 serial port -#hint.uart.2.at="ixp0" -#hint.uart.2.addr=0x53f80000 -#hint.uart.2.irq=21 -#hint.uart.2.rclk=1843200 - -# NPE Hardware Queue Manager -hint.ixpqmgr.0.at="ixp0" - -# NPE wired NICs, requires ixpqmgr -hint.npe.0.at="ixp0" -hint.npe.0.npeid="C" -hint.npe.0.mac="C" -hint.npe.0.mii="C" -hint.npe.0.phy=1 -hint.npe.1.at="ixp0" -hint.npe.1.npeid="A" -hint.npe.1.mac="A" -hint.npe.1.mii="C" -hint.npe.1.phy=2 - -# FLASH -hint.cfi.0.at="ixp0" -hint.cfi.0.addr=0x50000000 - -# CF IDE controller -hint.ata_avila.0.at="ixp0" - -# Front Panel LED -hint.fled.0.at="iicbus0" -hint.fled.0.addr=0x5a - -# Octal LED Latch -hint.led_cambria.0.at="ixp0" - -# GPIO pins -hint.gpio_cambria.0.at="iicbus0" -hint.gpio_cambria.0.addr=0x56 - -# Analog Devices AD7418 temperature sensor -hint.ad7418.0.at="iicbus0" -hint.ad7418.0.addr=0x50 - -# Dallas Semiconductor DS1672 RTC -hint.ds1672_rtc.0.at="iicbus0" -hint.ds1672_rtc.0.addr=0xd0 - -# USB is part of the chip -hint.ehci.0.at="ixp0" -hint.ehci.0.addr=0xcd000000 -hint.ehci.0.irq=32 -hint.ehci.1.at="ixp0" -hint.ehci.1.addr=0xce000000 -hint.ehci.1.irq=33 diff --git a/sys/arm/conf/NOTES b/sys/arm/conf/NOTES index 9f5f6574abc5..1b8d93e3bdfb 100644 --- a/sys/arm/conf/NOTES +++ b/sys/arm/conf/NOTES @@ -6,8 +6,6 @@ cpu CPU_ARM9 cpu CPU_ARM9E cpu CPU_FA526 cpu CPU_XSCALE_81342 -cpu CPU_XSCALE_IXP425 -cpu CPU_XSCALE_IXP435 cpu CPU_XSCALE_PXA2X0 files "../at91/files.at91" @@ -19,8 +17,6 @@ files "../mv/orion/files.db88f5xxx" files "../mv/orion/files.ts7800" files "../xscale/i8134x/files.crb" files "../xscale/i8134x/files.i81342" -files "../xscale/ixp425/files.avila" -files "../xscale/ixp425/files.ixp425" files "../xscale/pxa/files.pxa" options PHYSADDR=0x00000000 diff --git a/sys/arm/conf/NSLU b/sys/arm/conf/NSLU deleted file mode 100644 index b1e9d669ddd7..000000000000 --- a/sys/arm/conf/NSLU +++ /dev/null @@ -1,107 +0,0 @@ -# NSLU - kernel configuration file for FreeBSD/arm on Linksys NSLU2 -# -# For more information on this file, please read the handbook section on -# Kernel Configuration Files: -# -# https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html -# -# The handbook is also available locally in /usr/share/doc/handbook -# if you've installed the doc distribution, otherwise always see the -# FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the -# latest information. -# -# An exhaustive list of options and more detailed explanations of the -# device lines is also present in the ../../conf/NOTES and NOTES files. -# If you are in doubt as to the purpose or necessity of a line, check first -# in NOTES. -# -# $FreeBSD$ - -#NO_UNIVERSE - -ident NSLU - -include "std.arm" -# XXX What is defined in std.avila does not exactly match the following: -#options PHYSADDR=0x10000000 -#options KERNVIRTADDR=0xc0200000 # Used in ldscript.arm -#options FLASHADDR=0x50000000 -#options LOADERRAMADDR=0x00000000 - -include "../xscale/ixp425/std.ixp425" -# NB: memory mapping is defined in std.avila (see also comment above) -include "../xscale/ixp425/std.avila" -options XSCALE_CACHE_READ_WRITE_ALLOCATE -#To statically compile in device wiring instead of /boot/device.hints -hints "NSLU.hints" # Default places to look for devices. -makeoptions MODULES_OVERRIDE="" - -makeoptions CONF_CFLAGS=-mcpu=xscale -options HZ=100 -options DEVICE_POLLING - -options SCHED_ULE # ULE scheduler -options INET # InterNETworking -options INET6 # IPv6 communications protocols -options TCP_HHOOK # hhook(9) framework for TCP -options FFS # Berkeley Fast Filesystem -options SOFTUPDATES # Enable FFS soft updates support -options UFS_ACL # Support for access control lists -options UFS_DIRHASH # Improve performance on big directories -options NFSCL # Network Filesystem Client -options NFSD # Network Filesystem Server -options NFSLOCKD # Network Lock Manager -options NFS_ROOT # NFS usable as /, requires NFSCL -options GEOM_PART_BSD # BSD partition scheme -options GEOM_PART_MBR # MBR partition scheme -options TMPFS # Efficient memory filesystem -#options MSDOSFS # MSDOS Filesystem -options CD9660 # ISO 9660 Filesystem -#options PROCFS # Process filesystem (requires PSEUDOFS) -options PSEUDOFS # Pseudo-filesystem framework -options SCSI_DELAY=5000 # Delay (in ms) before probing SCSI -options KTRACE # ktrace(1) support -options SYSVSHM # SYSV-style shared memory -options SYSVMSG # SYSV-style message queues -options SYSVSEM # SYSV-style semaphores -options _KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions -options MUTEX_NOINLINE # Mutex inlines are space hogs -options RWLOCK_NOINLINE # rwlock inlines are space hogs -options SX_NOINLINE # sx inliens are space hogs -options BOOTP -options BOOTP_NFSROOT -options BOOTP_NFSV3 -options BOOTP_WIRED_TO=npe0 -options BOOTP_COMPAT - -device pci -device uart - -# I2C Bus -device iicbus -device iicbb -device iic - -device ixpiic # I2C bus glue -device ixpwdog # watchdog timer - -device npe # Network Processing Engine -device npe_fw -device firmware -device qmgr # Q Manager (required by npe) -device mii # Minimal mii routines -device rlphy # NSLU2 uses Realtek PHY attached to npe -device ether -device bpf - -device loop - -device md -device random # Entropy device - -device usb -device ohci -device ehci -device umass -device scbus # SCSI bus (required for ATA/SCSI) -device da # Direct Access (disks) diff --git a/sys/arm/conf/NSLU.hints b/sys/arm/conf/NSLU.hints deleted file mode 100644 index ed3f462ee61b..000000000000 --- a/sys/arm/conf/NSLU.hints +++ /dev/null @@ -1,38 +0,0 @@ -# $FreeBSD$ - -# -# Device wiring for the Linksys NSLU2 -# - -# DBGU is unit 0 -hint.uart.0.at="ixp0" -hint.uart.0.addr=0xc8000000 -hint.uart.0.irq=15 -hint.uart.0.flags=0x10 -# USART0 is unit 1 -hint.uart.1.at="ixp0" -hint.uart.1.addr=0xc8001000 -hint.uart.1.irq=13 - -# NPE Hardware Queue Manager -hint.ixpqmgr.0.at="ixp0" - -# NPE wired NICs, requires ixpqmgr -hint.npe.0.at="ixp0" -hint.npe.0.mac="B" -hint.npe.0.mii="B" -hint.npe.0.phy=1 -# The second MAC isn't used on the NSLU, but it needs to be configured or -# we timeout on dhcp packets -hint.npe.1.at="ixp0" -#hint.npe.1.mac="B" -#hint.npe.1.mii="A" -#hint.npe.1.phy=0 - -#not yet -# RTC -#hint.xrtc.0.at="iicbus0" -#hint.xrtc.0.addr=0xde -# Slug LED -# Slug button -# Slug Buzzer diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h index 1f2e94db70c0..666ff6055fa8 100644 --- a/sys/arm/include/cpufunc.h +++ b/sys/arm/include/cpufunc.h @@ -314,8 +314,7 @@ void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); #if defined(CPU_ARM9) || defined(CPU_ARM9E) || \ defined(CPU_FA526) || \ - defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ - defined(CPU_XSCALE_81342) + defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_81342) void armv4_tlb_flushID (void); void armv4_tlb_flushD (void); @@ -325,8 +324,7 @@ void armv4_drain_writebuf (void); void armv4_idcache_inv_all (void); #endif -#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ - defined(CPU_XSCALE_81342) +#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_81342) void xscale_cpwait (void); void xscale_cpu_sleep (int mode); @@ -364,7 +362,7 @@ void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); void xscale_context_switch (void); void xscale_setup (void); -#endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ +#endif /* CPU_XSCALE_PXA2X0 */ #ifdef CPU_XSCALE_81342 diff --git a/sys/arm/include/intr.h b/sys/arm/include/intr.h index beb523c8d8ad..9c6425095f3f 100644 --- a/sys/arm/include/intr.h +++ b/sys/arm/include/intr.h @@ -75,8 +75,7 @@ int intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *, void *); #define NIRQ IRQ_GPIO_MAX #elif defined(SOC_MV_DISCOVERY) #define NIRQ 96 -#elif defined(CPU_ARM9) || defined(SOC_MV_KIRKWOOD) || \ - defined(CPU_XSCALE_IXP435) +#elif defined(CPU_ARM9) || defined(SOC_MV_KIRKWOOD) #define NIRQ 64 #elif defined(CPU_CORTEXA) #define NIRQ 1020 diff --git a/sys/arm/include/pmap-v4.h b/sys/arm/include/pmap-v4.h index bdca55dcf0d5..39c323a3e491 100644 --- a/sys/arm/include/pmap-v4.h +++ b/sys/arm/include/pmap-v4.h @@ -63,8 +63,7 @@ #define ARM_MMU_GENERIC 0 #endif -#if (defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ - defined(CPU_XSCALE_81342)) +#if (defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_81342)) #define ARM_MMU_XSCALE 1 #else #define ARM_MMU_XSCALE 0 diff --git a/sys/arm/xscale/ixp425/avila_ata.c b/sys/arm/xscale/ixp425/avila_ata.c deleted file mode 100644 index fc9e67c5ef17..000000000000 --- a/sys/arm/xscale/ixp425/avila_ata.c +++ /dev/null @@ -1,553 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 Sam Leffler, Errno Consulting - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - */ - -#include -__FBSDID("$FreeBSD$"); - -/* - * Compact Flash Support for the Avila Gateworks XScale boards. - * The CF slot is operated in "True IDE" mode. Registers are on - * the Expansion Bus connected to CS1 and CS2. Interrupts are - * tied to GPIO pin 12. No DMA, just PIO. - * - * The ADI Pronghorn Metro is very similar. It use CS3 and CS4 and - * GPIO pin 0 for interrupts. - * - * See also http://www.intel.com/design/network/applnots/302456.htm. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#define AVILA_IDE_CTRL 0x06 - -struct ata_config { - const char *desc; /* description for probe */ - uint8_t gpin; /* GPIO pin */ - uint8_t irq; /* IRQ */ - uint32_t base16; /* CS base addr for 16-bit */ - uint32_t size16; /* CS size for 16-bit */ - uint32_t off16; /* CS offset for 16-bit */ - uint32_t basealt; /* CS base addr for alt */ - uint32_t sizealt; /* CS size for alt */ - uint32_t offalt; /* CS offset for alt */ -}; - -static const struct ata_config * -ata_getconfig(struct ixp425_softc *sa) -{ - static const struct ata_config configs[] = { - { .desc = "Gateworks Avila IDE/CF Controller", - .gpin = 12, - .irq = IXP425_INT_GPIO_12, - .base16 = IXP425_EXP_BUS_CS1_HWBASE, - .size16 = IXP425_EXP_BUS_CS1_SIZE, - .off16 = EXP_TIMING_CS1_OFFSET, - .basealt = IXP425_EXP_BUS_CS2_HWBASE, - .sizealt = IXP425_EXP_BUS_CS2_SIZE, - .offalt = EXP_TIMING_CS2_OFFSET, - }, - { .desc = "Gateworks Cambria IDE/CF Controller", - .gpin = 12, - .irq = IXP425_INT_GPIO_12, - .base16 = CAMBRIA_CFSEL0_HWBASE, - .size16 = CAMBRIA_CFSEL0_SIZE, - .off16 = EXP_TIMING_CS3_OFFSET, - .basealt = CAMBRIA_CFSEL1_HWBASE, - .sizealt = CAMBRIA_CFSEL1_SIZE, - .offalt = EXP_TIMING_CS4_OFFSET, - }, - { .desc = "ADI Pronghorn Metro IDE/CF Controller", - .gpin = 0, - .irq = IXP425_INT_GPIO_0, - .base16 = IXP425_EXP_BUS_CS3_HWBASE, - .size16 = IXP425_EXP_BUS_CS3_SIZE, - .off16 = EXP_TIMING_CS3_OFFSET, - .basealt = IXP425_EXP_BUS_CS4_HWBASE, - .sizealt = IXP425_EXP_BUS_CS4_SIZE, - .offalt = EXP_TIMING_CS4_OFFSET, - }, - }; - - /* XXX honor hint? (but then no multi-board support) */ - /* XXX total hack */ - if (cpu_is_ixp43x()) - return &configs[1]; /* Cambria */ - if (EXP_BUS_READ_4(sa, EXP_TIMING_CS2_OFFSET) != 0) - return &configs[0]; /* Avila */ - return &configs[2]; /* Pronghorn */ -} - -struct ata_avila_softc { - device_t sc_dev; - bus_space_tag_t sc_iot; - bus_space_handle_t sc_exp_ioh; /* Exp Bus config registers */ - bus_space_handle_t sc_ioh; /* CS1/3 data registers */ - bus_space_handle_t sc_alt_ioh; /* CS2/4 data registers */ - struct bus_space sc_expbus_tag; - struct resource sc_ata; /* hand-crafted for ATA */ - struct resource sc_alt_ata; /* hand-crafted for ATA */ - u_int32_t sc_16bit_off; /* EXP_TIMING_CSx_OFFSET */ - int sc_rid; /* rid for IRQ */ - struct resource *sc_irq; /* IRQ resource */ - void *sc_ih; /* interrupt handler */ - struct { - void (*cb)(void *); - void *arg; - } sc_intr[1]; /* NB: 1/channel */ -}; - -static void ata_avila_intr(void *); -bs_protos(ata); -static void ata_bs_rm_2_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, - u_int16_t *, bus_size_t); -static void ata_bs_wm_2_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, - const u_int16_t *, bus_size_t); - -static int -ata_avila_probe(device_t dev) -{ - struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); - const struct ata_config *config; - - config = ata_getconfig(sa); - if (config != NULL) { - device_set_desc_copy(dev, config->desc); - return 0; - } - return ENXIO; -} - -static int -ata_avila_attach(device_t dev) -{ - struct ata_avila_softc *sc = device_get_softc(dev); - struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); - const struct ata_config *config; - - config = ata_getconfig(sa); - KASSERT(config != NULL, ("no board config")); - - sc->sc_dev = dev; - /* NB: borrow from parent */ - sc->sc_iot = sa->sc_iot; - sc->sc_exp_ioh = sa->sc_exp_ioh; - - if (bus_space_map(sc->sc_iot, config->base16, config->size16, - 0, &sc->sc_ioh)) - panic("%s: cannot map 16-bit window (0x%x/0x%x)", - __func__, config->base16, config->size16); - if (bus_space_map(sc->sc_iot, config->basealt, config->sizealt, - 0, &sc->sc_alt_ioh)) - panic("%s: cannot map alt window (0x%x/0x%x)", - __func__, config->basealt, config->sizealt); - sc->sc_16bit_off = config->off16; - - if (config->base16 != CAMBRIA_CFSEL0_HWBASE) { - /* - * Craft special resource for ATA bus space ops - * that go through the expansion bus and require - * special hackery to ena/dis 16-bit operations. - * - * XXX probably should just make this generic for - * accessing the expansion bus. - */ - sc->sc_expbus_tag.bs_privdata = sc; /* NB: backpointer */ - /* read single */ - sc->sc_expbus_tag.bs_r_1 = ata_bs_r_1; - sc->sc_expbus_tag.bs_r_2 = ata_bs_r_2; - /* read multiple */ - sc->sc_expbus_tag.bs_rm_2 = ata_bs_rm_2; - sc->sc_expbus_tag.bs_rm_2_s = ata_bs_rm_2_s; - /* write (single) */ - sc->sc_expbus_tag.bs_w_1 = ata_bs_w_1; - sc->sc_expbus_tag.bs_w_2 = ata_bs_w_2; - /* write multiple */ - sc->sc_expbus_tag.bs_wm_2 = ata_bs_wm_2; - sc->sc_expbus_tag.bs_wm_2_s = ata_bs_wm_2_s; - - rman_set_bustag(&sc->sc_ata, &sc->sc_expbus_tag); - rman_set_bustag(&sc->sc_alt_ata, &sc->sc_expbus_tag); - } else { - /* - * On Cambria use the shared CS3 expansion bus tag - * that handles interlock for sharing access with the - * optional UART's. - */ - rman_set_bustag(&sc->sc_ata, &cambria_exp_bs_tag); - rman_set_bustag(&sc->sc_alt_ata, &cambria_exp_bs_tag); - } - rman_set_bushandle(&sc->sc_ata, sc->sc_ioh); - rman_set_bushandle(&sc->sc_alt_ata, sc->sc_alt_ioh); - - ixp425_set_gpio(sa, config->gpin, GPIO_TYPE_EDG_RISING); - - /* configure CS1/3 window, leaving timing unchanged */ - EXP_BUS_WRITE_4(sc, sc->sc_16bit_off, - EXP_BUS_READ_4(sc, sc->sc_16bit_off) | - EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN); - /* configure CS2/4 window, leaving timing unchanged */ - EXP_BUS_WRITE_4(sc, config->offalt, - EXP_BUS_READ_4(sc, config->offalt) | - EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN); - - /* setup interrupt */ - sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->sc_rid, - config->irq, config->irq, 1, RF_ACTIVE); - if (!sc->sc_irq) - panic("Unable to allocate irq %u.\n", config->irq); - bus_setup_intr(dev, sc->sc_irq, - INTR_TYPE_BIO | INTR_MPSAFE | INTR_ENTROPY, - NULL, ata_avila_intr, sc, &sc->sc_ih); - - /* attach channel on this controller */ - device_add_child(dev, "ata", -1); - bus_generic_attach(dev); - - return 0; -} - -static int -ata_avila_detach(device_t dev) -{ - struct ata_avila_softc *sc = device_get_softc(dev); - - /* XXX quiesce gpio? */ - - /* detach & delete all children */ - device_delete_children(dev); - - bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); - bus_release_resource(dev, SYS_RES_IRQ, sc->sc_rid, sc->sc_irq); - - return 0; -} - -static void -ata_avila_intr(void *xsc) -{ - struct ata_avila_softc *sc = xsc; - - if (sc->sc_intr[0].cb != NULL) - sc->sc_intr[0].cb(sc->sc_intr[0].arg); -} - -static struct resource * -ata_avila_alloc_resource(device_t dev, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ - struct ata_avila_softc *sc = device_get_softc(dev); - - KASSERT(type == SYS_RES_IRQ && *rid == ATA_IRQ_RID, - ("type %u rid %u start %ju end %ju count %ju flags %u", - type, *rid, start, end, count, flags)); - - /* doesn't matter what we return so reuse the real thing */ - return sc->sc_irq; -} - -static int -ata_avila_release_resource(device_t dev, device_t child, int type, int rid, - struct resource *r) -{ - KASSERT(type == SYS_RES_IRQ && rid == ATA_IRQ_RID, - ("type %u rid %u", type, rid)); - return 0; -} - -static int -ata_avila_setup_intr(device_t dev, device_t child, struct resource *irq, - int flags, driver_filter_t *filt, - driver_intr_t *function, void *argument, void **cookiep) -{ - struct ata_avila_softc *sc = device_get_softc(dev); - int unit = ((struct ata_channel *)device_get_softc(child))->unit; - - KASSERT(unit == 0, ("unit %d", unit)); - sc->sc_intr[unit].cb = function; - sc->sc_intr[unit].arg = argument; - *cookiep = sc; - return 0; -} - -static int -ata_avila_teardown_intr(device_t dev, device_t child, struct resource *irq, - void *cookie) -{ - struct ata_avila_softc *sc = device_get_softc(dev); - int unit = ((struct ata_channel *)device_get_softc(child))->unit; - - KASSERT(unit == 0, ("unit %d", unit)); - sc->sc_intr[unit].cb = NULL; - sc->sc_intr[unit].arg = NULL; - return 0; -} - -/* - * Bus space accessors for CF-IDE PIO operations. - */ - -/* - * Enable/disable 16-bit ops on the expansion bus. - */ -static __inline void -enable_16(struct ata_avila_softc *sc) -{ - EXP_BUS_WRITE_4(sc, sc->sc_16bit_off, - EXP_BUS_READ_4(sc, sc->sc_16bit_off) &~ EXP_BYTE_EN); - DELAY(100); /* XXX? */ -} - -static __inline void -disable_16(struct ata_avila_softc *sc) -{ - DELAY(100); /* XXX? */ - EXP_BUS_WRITE_4(sc, sc->sc_16bit_off, - EXP_BUS_READ_4(sc, sc->sc_16bit_off) | EXP_BYTE_EN); -} - -uint8_t -ata_bs_r_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o) -{ - struct ata_avila_softc *sc = tag->bs_privdata; - - return bus_space_read_1(sc->sc_iot, h, o); -} - -void -ata_bs_w_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, u_int8_t v) -{ - struct ata_avila_softc *sc = tag->bs_privdata; - - bus_space_write_1(sc->sc_iot, h, o, v); -} - -uint16_t -ata_bs_r_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o) -{ - struct ata_avila_softc *sc = tag->bs_privdata; - uint16_t v; - - enable_16(sc); - v = bus_space_read_2(sc->sc_iot, h, o); - disable_16(sc); - return v; -} - -void -ata_bs_w_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, uint16_t v) -{ - struct ata_avila_softc *sc = tag->bs_privdata; - - enable_16(sc); - bus_space_write_2(sc->sc_iot, h, o, v); - disable_16(sc); -} - -void -ata_bs_rm_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, - u_int16_t *d, bus_size_t c) -{ - struct ata_avila_softc *sc = tag->bs_privdata; - - enable_16(sc); - bus_space_read_multi_2(sc->sc_iot, h, o, d, c); - disable_16(sc); -} - -void -ata_bs_wm_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, - const u_int16_t *d, bus_size_t c) -{ - struct ata_avila_softc *sc = tag->bs_privdata; - - enable_16(sc); - bus_space_write_multi_2(sc->sc_iot, h, o, d, c); - disable_16(sc); -} - -/* XXX workaround ata driver by (incorrectly) byte swapping stream cases */ - -void -ata_bs_rm_2_s(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, - u_int16_t *d, bus_size_t c) -{ - struct ata_avila_softc *sc = tag->bs_privdata; - uint16_t v; - bus_size_t i; - - enable_16(sc); -#if 1 - for (i = 0; i < c; i++) { - v = bus_space_read_2(sc->sc_iot, h, o); - d[i] = bswap16(v); - } -#else - bus_space_read_multi_stream_2(sc->sc_iot, h, o, d, c); -#endif - disable_16(sc); -} - -void -ata_bs_wm_2_s(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, - const u_int16_t *d, bus_size_t c) -{ - struct ata_avila_softc *sc = tag->bs_privdata; - bus_size_t i; - - enable_16(sc); -#if 1 - for (i = 0; i < c; i++) - bus_space_write_2(sc->sc_iot, h, o, bswap16(d[i])); -#else - bus_space_write_multi_stream_2(sc->sc_iot, h, o, d, c); -#endif - disable_16(sc); -} - -static device_method_t ata_avila_methods[] = { - /* device interface */ - DEVMETHOD(device_probe, ata_avila_probe), - DEVMETHOD(device_attach, ata_avila_attach), - DEVMETHOD(device_detach, ata_avila_detach), - DEVMETHOD(device_shutdown, bus_generic_shutdown), - DEVMETHOD(device_suspend, bus_generic_suspend), - DEVMETHOD(device_resume, bus_generic_resume), - - /* bus methods */ - DEVMETHOD(bus_alloc_resource, ata_avila_alloc_resource), - DEVMETHOD(bus_release_resource, ata_avila_release_resource), - DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), - DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), - DEVMETHOD(bus_setup_intr, ata_avila_setup_intr), - DEVMETHOD(bus_teardown_intr, ata_avila_teardown_intr), - - { 0, 0 } -}; - -devclass_t ata_avila_devclass; - -static driver_t ata_avila_driver = { - "ata_avila", - ata_avila_methods, - sizeof(struct ata_avila_softc), -}; - -DRIVER_MODULE(ata_avila, ixp, ata_avila_driver, ata_avila_devclass, 0, 0); -MODULE_VERSION(ata_avila, 1); -MODULE_DEPEND(ata_avila, ata, 1, 1, 1); - -static int -avila_channel_probe(device_t dev) -{ - struct ata_channel *ch = device_get_softc(dev); - - ch->unit = 0; - ch->flags |= ATA_USE_16BIT | ATA_NO_SLAVE; - device_set_desc_copy(dev, "ATA channel 0"); - - return ata_probe(dev); -} - -static int -avila_channel_attach(device_t dev) -{ - struct ata_avila_softc *sc = device_get_softc(device_get_parent(dev)); - struct ata_channel *ch = device_get_softc(dev); - int i; - - for (i = 0; i < ATA_MAX_RES; i++) - ch->r_io[i].res = &sc->sc_ata; - - ch->r_io[ATA_DATA].offset = ATA_DATA; - ch->r_io[ATA_FEATURE].offset = ATA_FEATURE; - ch->r_io[ATA_COUNT].offset = ATA_COUNT; - ch->r_io[ATA_SECTOR].offset = ATA_SECTOR; - ch->r_io[ATA_CYL_LSB].offset = ATA_CYL_LSB; - ch->r_io[ATA_CYL_MSB].offset = ATA_CYL_MSB; - ch->r_io[ATA_DRIVE].offset = ATA_DRIVE; - ch->r_io[ATA_COMMAND].offset = ATA_COMMAND; - ch->r_io[ATA_ERROR].offset = ATA_FEATURE; - /* NB: should be used only for ATAPI devices */ - ch->r_io[ATA_IREASON].offset = ATA_COUNT; - ch->r_io[ATA_STATUS].offset = ATA_COMMAND; - - /* NB: the control and alt status registers are special */ - ch->r_io[ATA_ALTSTAT].res = &sc->sc_alt_ata; - ch->r_io[ATA_ALTSTAT].offset = AVILA_IDE_CTRL; - ch->r_io[ATA_CONTROL].res = &sc->sc_alt_ata; - ch->r_io[ATA_CONTROL].offset = AVILA_IDE_CTRL; - - /* NB: by convention this points at the base of registers */ - ch->r_io[ATA_IDX_ADDR].offset = 0; - - ata_generic_hw(dev); - return ata_attach(dev); -} - -static device_method_t avila_channel_methods[] = { - /* device interface */ - DEVMETHOD(device_probe, avila_channel_probe), - DEVMETHOD(device_attach, avila_channel_attach), - DEVMETHOD(device_detach, ata_detach), - DEVMETHOD(device_shutdown, bus_generic_shutdown), - DEVMETHOD(device_suspend, ata_suspend), - DEVMETHOD(device_resume, ata_resume), - - { 0, 0 } -}; - -driver_t avila_channel_driver = { - "ata", - avila_channel_methods, - sizeof(struct ata_channel), -}; -DRIVER_MODULE(ata, ata_avila, avila_channel_driver, ata_devclass, 0, 0); diff --git a/sys/arm/xscale/ixp425/avila_gpio.c b/sys/arm/xscale/ixp425/avila_gpio.c deleted file mode 100644 index 99f0e803f583..000000000000 --- a/sys/arm/xscale/ixp425/avila_gpio.c +++ /dev/null @@ -1,371 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2009, Oleksandr Tymoshenko - * Copyright (c) 2009, Luiz Otavio O Souza. - * Copyright (c) 2010, Andrew Thompson - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice unmodified, this list of conditions, and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * GPIO driver for Gateworks Avilia - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "gpio_if.h" - -#define GPIO_SET_BITS(sc, reg, bits) \ - GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, (reg)) | (bits)) - -#define GPIO_CLEAR_BITS(sc, reg, bits) \ - GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, (reg)) & ~(bits)) - -struct avila_gpio_softc { - device_t sc_dev; - device_t sc_busdev; - bus_space_tag_t sc_iot; - bus_space_handle_t sc_gpio_ioh; - uint32_t sc_valid; - struct gpio_pin sc_pins[IXP4XX_GPIO_PINS]; -}; - -struct avila_gpio_pin { - const char *name; - int pin; - int caps; -}; - -#define GPIO_PIN_IO (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT) -static struct avila_gpio_pin avila_gpio_pins[] = { - { "GPIO0", 0, GPIO_PIN_IO }, - { "GPIO1", 1, GPIO_PIN_IO }, - { "GPIO2", 2, GPIO_PIN_IO }, - { "GPIO3", 3, GPIO_PIN_IO }, - { "GPIO4", 4, GPIO_PIN_IO }, - /* - * The following pins are connected to system devices and should not - * really be frobbed. - */ -#if 0 - { "SER_ENA", 5, GPIO_PIN_IO }, - { "I2C_SCL", 6, GPIO_PIN_IO }, - { "I2C_SDA", 7, GPIO_PIN_IO }, - { "PCI_INTD", 8, GPIO_PIN_IO }, - { "PCI_INTC", 9, GPIO_PIN_IO }, - { "PCI_INTB", 10, GPIO_PIN_IO }, - { "PCI_INTA", 11, GPIO_PIN_IO }, - { "ATA_INT", 12, GPIO_PIN_IO }, - { "PCI_RST", 13, GPIO_PIN_IO }, - { "PCI_CLK", 14, GPIO_PIN_OUTPUT }, - { "EX_CLK", 15, GPIO_PIN_OUTPUT }, -#endif -}; -#undef GPIO_PIN_IO - -/* - * Helpers - */ -static void avila_gpio_pin_configure(struct avila_gpio_softc *sc, - struct gpio_pin *pin, uint32_t flags); -static int avila_gpio_pin_flags(struct avila_gpio_softc *sc, uint32_t pin); - -/* - * Driver stuff - */ -static int avila_gpio_probe(device_t dev); -static int avila_gpio_attach(device_t dev); -static int avila_gpio_detach(device_t dev); - -/* - * GPIO interface - */ -static device_t avila_gpio_get_bus(device_t); -static int avila_gpio_pin_max(device_t dev, int *maxpin); -static int avila_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps); -static int avila_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t - *flags); -static int avila_gpio_pin_getname(device_t dev, uint32_t pin, char *name); -static int avila_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags); -static int avila_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value); -static int avila_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val); -static int avila_gpio_pin_toggle(device_t dev, uint32_t pin); - -static int -avila_gpio_pin_flags(struct avila_gpio_softc *sc, uint32_t pin) -{ - uint32_t v; - - v = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR) & (1 << pin); - - return (v ? GPIO_PIN_INPUT : GPIO_PIN_OUTPUT); -} - -static void -avila_gpio_pin_configure(struct avila_gpio_softc *sc, struct gpio_pin *pin, - unsigned int flags) -{ - uint32_t mask; - - mask = 1 << pin->gp_pin; - - /* - * Manage input/output - */ - if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { - IXP4XX_GPIO_LOCK(); - pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT); - if (flags & GPIO_PIN_OUTPUT) { - pin->gp_flags |= GPIO_PIN_OUTPUT; - GPIO_CLEAR_BITS(sc, IXP425_GPIO_GPOER, mask); - } - else { - pin->gp_flags |= GPIO_PIN_INPUT; - GPIO_SET_BITS(sc, IXP425_GPIO_GPOER, mask); - } - IXP4XX_GPIO_UNLOCK(); - } -} - -static device_t -avila_gpio_get_bus(device_t dev) -{ - struct avila_gpio_softc *sc; - - sc = device_get_softc(dev); - - return (sc->sc_busdev); -} - -static int -avila_gpio_pin_max(device_t dev, int *maxpin) -{ - - *maxpin = IXP4XX_GPIO_PINS - 1; - return (0); -} - -static int -avila_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) -{ - struct avila_gpio_softc *sc = device_get_softc(dev); - - if (pin >= IXP4XX_GPIO_PINS || !(sc->sc_valid & (1 << pin))) - return (EINVAL); - - *caps = sc->sc_pins[pin].gp_caps; - return (0); -} - -static int -avila_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) -{ - struct avila_gpio_softc *sc = device_get_softc(dev); - - if (pin >= IXP4XX_GPIO_PINS || !(sc->sc_valid & (1 << pin))) - return (EINVAL); - - IXP4XX_GPIO_LOCK(); - /* refresh since we do not own all the pins */ - sc->sc_pins[pin].gp_flags = avila_gpio_pin_flags(sc, pin); - *flags = sc->sc_pins[pin].gp_flags; - IXP4XX_GPIO_UNLOCK(); - - return (0); -} - -static int -avila_gpio_pin_getname(device_t dev, uint32_t pin, char *name) -{ - struct avila_gpio_softc *sc = device_get_softc(dev); - - if (pin >= IXP4XX_GPIO_PINS || !(sc->sc_valid & (1 << pin))) - return (EINVAL); - - memcpy(name, sc->sc_pins[pin].gp_name, GPIOMAXNAME); - return (0); -} - -static int -avila_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) -{ - struct avila_gpio_softc *sc = device_get_softc(dev); - uint32_t mask = 1 << pin; - - if (pin >= IXP4XX_GPIO_PINS || !(sc->sc_valid & mask)) - return (EINVAL); - - avila_gpio_pin_configure(sc, &sc->sc_pins[pin], flags); - - return (0); -} - -static int -avila_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) -{ - struct avila_gpio_softc *sc = device_get_softc(dev); - uint32_t mask = 1 << pin; - - if (pin >= IXP4XX_GPIO_PINS || !(sc->sc_valid & mask)) - return (EINVAL); - - IXP4XX_GPIO_LOCK(); - if (value) - GPIO_SET_BITS(sc, IXP425_GPIO_GPOUTR, mask); - else - GPIO_CLEAR_BITS(sc, IXP425_GPIO_GPOUTR, mask); - IXP4XX_GPIO_UNLOCK(); - - return (0); -} - -static int -avila_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) -{ - struct avila_gpio_softc *sc = device_get_softc(dev); - - if (pin >= IXP4XX_GPIO_PINS || !(sc->sc_valid & (1 << pin))) - return (EINVAL); - - IXP4XX_GPIO_LOCK(); - *val = (GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR) & (1 << pin)) ? 1 : 0; - IXP4XX_GPIO_UNLOCK(); - - return (0); -} - -static int -avila_gpio_pin_toggle(device_t dev, uint32_t pin) -{ - struct avila_gpio_softc *sc = device_get_softc(dev); - uint32_t mask = 1 << pin; - int res; - - if (pin >= IXP4XX_GPIO_PINS || !(sc->sc_valid & mask)) - return (EINVAL); - - IXP4XX_GPIO_LOCK(); - res = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR) & mask; - if (res) - GPIO_CLEAR_BITS(sc, IXP425_GPIO_GPOUTR, mask); - else - GPIO_SET_BITS(sc, IXP425_GPIO_GPOUTR, mask); - IXP4XX_GPIO_UNLOCK(); - - return (0); -} - -static int -avila_gpio_probe(device_t dev) -{ - - device_set_desc(dev, "Gateworks Avila GPIO driver"); - return (0); -} - -static int -avila_gpio_attach(device_t dev) -{ -#define N(a) (sizeof(a) / sizeof(a[0])) - struct avila_gpio_softc *sc = device_get_softc(dev); - struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); - int i; - - sc->sc_dev = dev; - sc->sc_iot = sa->sc_iot; - sc->sc_gpio_ioh = sa->sc_gpio_ioh; - - for (i = 0; i < N(avila_gpio_pins); i++) { - struct avila_gpio_pin *p = &avila_gpio_pins[i]; - - strncpy(sc->sc_pins[p->pin].gp_name, p->name, GPIOMAXNAME); - sc->sc_pins[p->pin].gp_pin = p->pin; - sc->sc_pins[p->pin].gp_caps = p->caps; - sc->sc_pins[p->pin].gp_flags = avila_gpio_pin_flags(sc, p->pin); - sc->sc_valid |= 1 << p->pin; - } - - sc->sc_busdev = gpiobus_attach_bus(dev); - if (sc->sc_busdev == NULL) - return (ENXIO); - - return (0); -#undef N -} - -static int -avila_gpio_detach(device_t dev) -{ - - gpiobus_detach_bus(dev); - - return(0); -} - -static device_method_t gpio_avila_methods[] = { - DEVMETHOD(device_probe, avila_gpio_probe), - DEVMETHOD(device_attach, avila_gpio_attach), - DEVMETHOD(device_detach, avila_gpio_detach), - - /* GPIO protocol */ - DEVMETHOD(gpio_get_bus, avila_gpio_get_bus), - DEVMETHOD(gpio_pin_max, avila_gpio_pin_max), - DEVMETHOD(gpio_pin_getname, avila_gpio_pin_getname), - DEVMETHOD(gpio_pin_getflags, avila_gpio_pin_getflags), - DEVMETHOD(gpio_pin_getcaps, avila_gpio_pin_getcaps), - DEVMETHOD(gpio_pin_setflags, avila_gpio_pin_setflags), - DEVMETHOD(gpio_pin_get, avila_gpio_pin_get), - DEVMETHOD(gpio_pin_set, avila_gpio_pin_set), - DEVMETHOD(gpio_pin_toggle, avila_gpio_pin_toggle), - {0, 0}, -}; - -static driver_t gpio_avila_driver = { - "gpio", - gpio_avila_methods, - sizeof(struct avila_gpio_softc), -}; -static devclass_t gpio_avila_devclass; - -DRIVER_MODULE(gpio_avila, ixp, gpio_avila_driver, gpio_avila_devclass, 0, 0); -MODULE_VERSION(gpio_avila, 1); diff --git a/sys/arm/xscale/ixp425/avila_led.c b/sys/arm/xscale/ixp425/avila_led.c deleted file mode 100644 index a4a27d8727ed..000000000000 --- a/sys/arm/xscale/ixp425/avila_led.c +++ /dev/null @@ -1,120 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 Kevin Lo. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include - -#include -#include - -#include - -#define GPIO_LED_STATUS 3 -#define GPIO_LED_STATUS_BIT (1U << GPIO_LED_STATUS) - -struct led_avila_softc { - device_t sc_dev; - bus_space_tag_t sc_iot; - bus_space_handle_t sc_gpio_ioh; - struct cdev *sc_led; -}; - -static void -led_func(void *arg, int onoff) -{ - struct led_avila_softc *sc = arg; - uint32_t reg; - - IXP4XX_GPIO_LOCK(); - reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR); - if (onoff) - reg &= ~GPIO_LED_STATUS_BIT; - else - reg |= GPIO_LED_STATUS_BIT; - GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg); - IXP4XX_GPIO_UNLOCK(); -} - -static int -led_avila_probe(device_t dev) -{ - device_set_desc(dev, "Gateworks Avila Front Panel LED"); - return (0); -} - -static int -led_avila_attach(device_t dev) -{ - struct led_avila_softc *sc = device_get_softc(dev); - struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); - - sc->sc_dev = dev; - sc->sc_iot = sa->sc_iot; - sc->sc_gpio_ioh = sa->sc_gpio_ioh; - - /* Configure LED GPIO pin as output */ - GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, - GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER) &~ GPIO_LED_STATUS_BIT); - - sc->sc_led = led_create(led_func, sc, "gpioled"); - - led_func(sc, 1); /* Turn on LED */ - - return (0); -} - -static int -led_avila_detach(device_t dev) -{ - struct led_avila_softc *sc = device_get_softc(dev); - - if (sc->sc_led != NULL) - led_destroy(sc->sc_led); - return (0); -} - -static device_method_t led_avila_methods[] = { - DEVMETHOD(device_probe, led_avila_probe), - DEVMETHOD(device_attach, led_avila_attach), - DEVMETHOD(device_detach, led_avila_detach), - - {0, 0}, -}; - -static driver_t led_avila_driver = { - "led_avila", - led_avila_methods, - sizeof(struct led_avila_softc), -}; -static devclass_t led_avila_devclass; - -DRIVER_MODULE(led_avila, ixp, led_avila_driver, led_avila_devclass, 0, 0); diff --git a/sys/arm/xscale/ixp425/avila_machdep.c b/sys/arm/xscale/ixp425/avila_machdep.c deleted file mode 100644 index a84de1f3402b..000000000000 --- a/sys/arm/xscale/ixp425/avila_machdep.c +++ /dev/null @@ -1,419 +0,0 @@ -/* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 1994-1998 Mark Brinicombe. - * Copyright (c) 1994 Brini. - * All rights reserved. - * - * This code is derived from software written for Brini by Mark Brinicombe - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Brini. - * 4. The name of the company nor the name of the author may be used to - * endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RiscBSD kernel project - * - * machdep.c - * - * Machine dependent functions for kernel setup - * - * This file needs a lot of work. - * - * Created : 17/09/94 - */ - -#include -__FBSDID("$FreeBSD$"); - -#include "opt_kstack_pages.h" - -#define _ARM32_BUS_DMA_PRIVATE -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ -#define KERNEL_PT_IO 1 -#define KERNEL_PT_IO_NUM 3 -#define KERNEL_PT_BEFOREKERN KERNEL_PT_IO + KERNEL_PT_IO_NUM -#define KERNEL_PT_AFKERNEL KERNEL_PT_BEFOREKERN + 1 /* L2 table for mapping after kernel */ -#define KERNEL_PT_AFKERNEL_NUM 9 - -/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */ -#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM) - -struct pv_addr kernel_pt_table[NUM_KERNEL_PTS]; - -/* Physical and virtual addresses for some global pages */ - -struct pv_addr systempage; -struct pv_addr msgbufpv; -struct pv_addr irqstack; -struct pv_addr undstack; -struct pv_addr abtstack; -struct pv_addr kernelstack; -struct pv_addr minidataclean; - -/* Static device mappings. */ -static const struct devmap_entry ixp425_devmap[] = { - /* Physical/Virtual address for I/O space */ - { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, }, - - /* Expansion Bus */ - { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, }, - - /* CFI Flash on the Expansion Bus */ - { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE, - IXP425_EXP_BUS_CS0_SIZE, }, - - /* IXP425 PCI Configuration */ - { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, }, - - /* SDRAM Controller */ - { IXP425_MCU_VBASE, IXP425_MCU_HWBASE, IXP425_MCU_SIZE, }, - - /* PCI Memory Space */ - { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, }, - - /* Q-Mgr Memory Space */ - { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, }, - - { 0 }, -}; - -/* Static device mappings. */ -static const struct devmap_entry ixp435_devmap[] = { - /* Physical/Virtual address for I/O space */ - { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE, }, - - { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, }, - - /* IXP425 PCI Configuration */ - { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE, }, - - /* DDRII Controller NB: mapped same place as IXP425 */ - { IXP425_MCU_VBASE, IXP435_MCU_HWBASE, IXP425_MCU_SIZE, }, - - /* PCI Memory Space */ - { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE, }, - - /* Q-Mgr Memory Space */ - { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, }, - - /* CFI Flash on the Expansion Bus */ - { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE, - IXP425_EXP_BUS_CS0_SIZE, }, - - /* USB1 Memory Space */ - { IXP435_USB1_VBASE, IXP435_USB1_HWBASE, IXP435_USB1_SIZE, }, - /* USB2 Memory Space */ - { IXP435_USB2_VBASE, IXP435_USB2_HWBASE, IXP435_USB2_SIZE, }, - - /* GPS Memory Space */ - { CAMBRIA_GPS_VBASE, CAMBRIA_GPS_HWBASE, CAMBRIA_GPS_SIZE, }, - - /* RS485 Memory Space */ - { CAMBRIA_RS485_VBASE, CAMBRIA_RS485_HWBASE, CAMBRIA_RS485_SIZE, }, - - { 0 } -}; - -extern vm_offset_t xscale_cache_clean_addr; - -void * -initarm(struct arm_boot_params *abp) -{ -#define next_chunk2(a,b) (((a) + (b)) &~ ((b)-1)) -#define next_page(a) next_chunk2(a,PAGE_SIZE) - struct pv_addr kernel_l1pt; - struct pv_addr dpcpu; - int loop, i; - u_int l1pagetable; - vm_offset_t freemempos; - vm_offset_t freemem_pt; - vm_offset_t afterkern; - vm_offset_t freemem_after; - vm_offset_t lastaddr; - uint32_t memsize; - - /* kernel text starts where we were loaded at boot */ -#define KERNEL_TEXT_OFF (abp->abp_physaddr - PHYSADDR) -#define KERNEL_TEXT_BASE (KERNBASE + KERNEL_TEXT_OFF) -#define KERNEL_TEXT_PHYS (PHYSADDR + KERNEL_TEXT_OFF) - - lastaddr = parse_boot_param(abp); - arm_physmem_kernaddr = abp->abp_physaddr; - set_cpufuncs(); /* NB: sets cputype */ - pcpu_init(pcpup, 0, sizeof(struct pcpu)); - PCPU_SET(curthread, &thread0); - - init_static_kenv(NULL, 0); - - /* Do basic tuning, hz etc */ - init_param1(); - - /* - * We allocate memory downwards from where we were loaded - * by RedBoot; first the L1 page table, then NUM_KERNEL_PTS - * entries in the L2 page table. Past that we re-align the - * allocation boundary so later data structures (stacks, etc) - * can be mapped with different attributes (write-back vs - * write-through). Note this leaves a gap for expansion - * (or might be repurposed). - */ - freemempos = abp->abp_physaddr; - - /* macros to simplify initial memory allocation */ -#define alloc_pages(var, np) do { \ - freemempos -= (np * PAGE_SIZE); \ - (var) = freemempos; \ - /* NB: this works because locore maps PA=VA */ \ - memset((char *)(var), 0, ((np) * PAGE_SIZE)); \ -} while (0) -#define valloc_pages(var, np) do { \ - alloc_pages((var).pv_pa, (np)); \ - (var).pv_va = (var).pv_pa + (KERNVIRTADDR - abp->abp_physaddr); \ -} while (0) - - /* force L1 page table alignment */ - while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0) - freemempos -= PAGE_SIZE; - /* allocate contiguous L1 page table */ - valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); - /* now allocate L2 page tables; they are linked to L1 below */ - for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) { - if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) { - valloc_pages(kernel_pt_table[loop], - L2_TABLE_SIZE / PAGE_SIZE); - } else { - kernel_pt_table[loop].pv_pa = freemempos + - (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) * - L2_TABLE_SIZE_REAL; - kernel_pt_table[loop].pv_va = - kernel_pt_table[loop].pv_pa + - (KERNVIRTADDR - abp->abp_physaddr); - } - } - freemem_pt = freemempos; /* base of allocated pt's */ - - /* - * Re-align allocation boundary so we can map the area - * write-back instead of write-through for the stacks and - * related structures allocated below. - */ - freemempos = PHYSADDR + 0x100000; - /* - * Allocate a page for the system page mapped to V0x00000000 - * This page will just contain the system vectors and can be - * shared by all processes. - */ - valloc_pages(systempage, 1); - - /* Allocate dynamic per-cpu area. */ - valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE); - dpcpu_init((void *)dpcpu.pv_va, 0); - - /* Allocate stacks for all modes */ - valloc_pages(irqstack, IRQ_STACK_SIZE); - valloc_pages(abtstack, ABT_STACK_SIZE); - valloc_pages(undstack, UND_STACK_SIZE); - valloc_pages(kernelstack, kstack_pages); - alloc_pages(minidataclean.pv_pa, 1); - valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE); - - /* - * Now construct the L1 page table. First map the L2 - * page tables into the L1 so we can replace L1 mappings - * later on if necessary - */ - l1pagetable = kernel_l1pt.pv_va; - - /* Map the L2 pages tables in the L1 page table */ - pmap_link_l2pt(l1pagetable, rounddown2(ARM_VECTORS_HIGH, 0x00100000), - &kernel_pt_table[KERNEL_PT_SYS]); - pmap_link_l2pt(l1pagetable, IXP425_IO_VBASE, - &kernel_pt_table[KERNEL_PT_IO]); - pmap_link_l2pt(l1pagetable, IXP425_MCU_VBASE, - &kernel_pt_table[KERNEL_PT_IO + 1]); - pmap_link_l2pt(l1pagetable, IXP425_PCI_MEM_VBASE, - &kernel_pt_table[KERNEL_PT_IO + 2]); - pmap_link_l2pt(l1pagetable, KERNBASE, - &kernel_pt_table[KERNEL_PT_BEFOREKERN]); - pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR, 0x100000, - VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, PHYSADDR + 0x100000, - 0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); - pmap_map_chunk(l1pagetable, KERNEL_TEXT_BASE, KERNEL_TEXT_PHYS, - next_chunk2(((uint32_t)lastaddr) - KERNEL_TEXT_BASE, L1_S_SIZE), - VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - freemem_after = next_page((int)lastaddr); - afterkern = round_page(next_chunk2((vm_offset_t)lastaddr, L1_S_SIZE)); - for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) { - pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000, - &kernel_pt_table[KERNEL_PT_AFKERNEL + i]); - } - pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa, - VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - - - /* Map the Mini-Data cache clean area. */ - xscale_setup_minidata(l1pagetable, afterkern, - minidataclean.pv_pa); - - /* Map the vector page. */ - pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, - VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); - if (cpu_is_ixp43x()) - devmap_bootstrap(l1pagetable, ixp435_devmap); - else - devmap_bootstrap(l1pagetable, ixp425_devmap); - /* - * Give the XScale global cache clean code an appropriately - * sized chunk of unmapped VA space starting at 0xff000000 - * (our device mappings end before this address). - */ - xscale_cache_clean_addr = 0xff000000U; - - cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); - cpu_setttb(kernel_l1pt.pv_pa); - cpu_tlb_flushID(); - cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); - - /* - * Pages were allocated during the secondary bootstrap for the - * stacks for different CPU modes. - * We must now set the r13 registers in the different CPU modes to - * point to these stacks. - * Since the ARM stacks use STMFD etc. we must set r13 to the top end - * of the stack memory. - */ - set_stackptrs(0); - - /* - * We must now clean the cache again.... - * Cleaning may be done by reading new data to displace any - * dirty data in the cache. This will have happened in cpu_setttb() - * but since we are boot strapping the addresses used for the read - * may have just been remapped and thus the cache could be out - * of sync. A re-clean after the switch will cure this. - * After booting there are no gross relocations of the kernel thus - * this problem will not occur after initarm(). - */ - cpu_idcache_wbinv_all(); - cpu_setup(); - - /* ready to setup the console (XXX move earlier if possible) */ - cninit(); - /* - * Fetch the RAM size from the MCU registers. The - * expansion bus was mapped above so we can now read 'em. - */ - if (cpu_is_ixp43x()) - memsize = ixp435_ddram_size(); - else - memsize = ixp425_sdram_size(); - - undefined_init(); - - init_proc0(kernelstack.pv_va); - - arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); - - pmap_curmaxkvaddr = afterkern + PAGE_SIZE; - vm_max_kernel_address = 0xe0000000; - pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt); - msgbufp = (void*)msgbufpv.pv_va; - msgbufinit(msgbufp, msgbufsize); - mutex_init(); - - /* - * Add the physical ram we have available. - * - * Exclude the kernel, and all the things we allocated which immediately - * follow the kernel, from the VM allocation pool but not from crash - * dumps. virtual_avail is a global variable which tracks the kva we've - * "allocated" while setting up pmaps. - * - * Prepare the list of physical memory available to the vm subsystem. - */ - arm_physmem_hardware_region(PHYSADDR, memsize); - arm_physmem_exclude_region(freemem_pt, abp->abp_physaddr - - freemem_pt, EXFLAG_NOALLOC); - arm_physmem_exclude_region(freemempos, abp->abp_physaddr - 0x100000 - - freemempos, EXFLAG_NOALLOC); - arm_physmem_exclude_region(abp->abp_physaddr, - virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC); - arm_physmem_init_kernel_globals(); - - init_param2(physmem); - kdb_init(); - - return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP - - sizeof(struct pcb))); -#undef next_page -#undef next_chunk2 -} diff --git a/sys/arm/xscale/ixp425/cambria_exp_space.c b/sys/arm/xscale/ixp425/cambria_exp_space.c deleted file mode 100644 index 68b7f3ce7b91..000000000000 --- a/sys/arm/xscale/ixp425/cambria_exp_space.c +++ /dev/null @@ -1,260 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2009 Sam Leffler. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Bus space tag for devices on the Cambria expansion bus. - * This interlocks accesses to allow the optional GPS+RS485 UART's - * to share access with the CF-IDE adapter. Note this does not - * slow the timing UART r/w ops because the lock operation does - * this implicitly for us. Also note we do not DELAY after byte/word - * chip select changes; this doesn't seem necessary (as required - * for IXP425/Avila boards). - * - * XXX should make this generic so all expansion bus devices can - * use it but probably not until we eliminate the ATA hacks - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -/* Prototypes for all the bus_space structure functions */ -bs_protos(exp); -bs_protos(generic); - -struct expbus_softc { - struct ixp425_softc *sc; /* bus space tag */ - struct mtx lock; /* i/o interlock */ - bus_size_t csoff; /* CS offset for 8/16 enable */ -}; -#define EXP_LOCK_INIT(exp) \ - mtx_init(&(exp)->lock, "ExpBus", NULL, MTX_SPIN) -#define EXP_LOCK_DESTROY(exp) \ - mtx_destroy(&(exp)->lock) -#define EXP_LOCK(exp) mtx_lock_spin(&(exp)->lock) -#define EXP_UNLOCK(exp) mtx_unlock_spin(&(exp)->lock) - -/* - * Enable/disable 16-bit ops on the expansion bus. - */ -static __inline void -enable_16(struct ixp425_softc *sc, bus_size_t cs) -{ - EXP_BUS_WRITE_4(sc, cs, EXP_BUS_READ_4(sc, cs) &~ EXP_BYTE_EN); -} - -static __inline void -disable_16(struct ixp425_softc *sc, bus_size_t cs) -{ - EXP_BUS_WRITE_4(sc, cs, EXP_BUS_READ_4(sc, cs) | EXP_BYTE_EN); -} - -static uint8_t -cambria_bs_r_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o) -{ - struct expbus_softc *exp = tag->bs_privdata; - struct ixp425_softc *sc = exp->sc; - uint8_t v; - - EXP_LOCK(exp); - v = bus_space_read_1(sc->sc_iot, h, o); - EXP_UNLOCK(exp); - return v; -} - -static void -cambria_bs_w_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, u_int8_t v) -{ - struct expbus_softc *exp = tag->bs_privdata; - struct ixp425_softc *sc = exp->sc; - - EXP_LOCK(exp); - bus_space_write_1(sc->sc_iot, h, o, v); - EXP_UNLOCK(exp); -} - -static uint16_t -cambria_bs_r_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o) -{ - struct expbus_softc *exp = tag->bs_privdata; - struct ixp425_softc *sc = exp->sc; - uint16_t v; - - EXP_LOCK(exp); - enable_16(sc, exp->csoff); - v = bus_space_read_2(sc->sc_iot, h, o); - disable_16(sc, exp->csoff); - EXP_UNLOCK(exp); - return v; -} - -static void -cambria_bs_w_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, uint16_t v) -{ - struct expbus_softc *exp = tag->bs_privdata; - struct ixp425_softc *sc = exp->sc; - - EXP_LOCK(exp); - enable_16(sc, exp->csoff); - bus_space_write_2(sc->sc_iot, h, o, v); - disable_16(sc, exp->csoff); - EXP_UNLOCK(exp); -} - -static void -cambria_bs_rm_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, - u_int16_t *d, bus_size_t c) -{ - struct expbus_softc *exp = tag->bs_privdata; - struct ixp425_softc *sc = exp->sc; - - EXP_LOCK(exp); - enable_16(sc, exp->csoff); - bus_space_read_multi_2(sc->sc_iot, h, o, d, c); - disable_16(sc, exp->csoff); - EXP_UNLOCK(exp); -} - -static void -cambria_bs_wm_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, - const u_int16_t *d, bus_size_t c) -{ - struct expbus_softc *exp = tag->bs_privdata; - struct ixp425_softc *sc = exp->sc; - - EXP_LOCK(exp); - enable_16(sc, exp->csoff); - bus_space_write_multi_2(sc->sc_iot, h, o, d, c); - disable_16(sc, exp->csoff); - EXP_UNLOCK(exp); -} - -/* XXX workaround ata driver by (incorrectly) byte swapping stream cases */ - -static void -cambria_bs_rm_2_s(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, - u_int16_t *d, bus_size_t c) -{ - struct expbus_softc *exp = tag->bs_privdata; - struct ixp425_softc *sc = exp->sc; - uint16_t v; - bus_size_t i; - - EXP_LOCK(exp); - enable_16(sc, exp->csoff); -#if 1 - for (i = 0; i < c; i++) { - v = bus_space_read_2(sc->sc_iot, h, o); - d[i] = bswap16(v); - } -#else - bus_space_read_multi_stream_2(sc->sc_iot, h, o, d, c); -#endif - disable_16(sc, exp->csoff); - EXP_UNLOCK(exp); -} - -static void -cambria_bs_wm_2_s(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, - const u_int16_t *d, bus_size_t c) -{ - struct expbus_softc *exp = tag->bs_privdata; - struct ixp425_softc *sc = exp->sc; - bus_size_t i; - - EXP_LOCK(exp); - enable_16(sc, exp->csoff); -#if 1 - for (i = 0; i < c; i++) - bus_space_write_2(sc->sc_iot, h, o, bswap16(d[i])); -#else - bus_space_write_multi_stream_2(sc->sc_iot, h, o, d, c); -#endif - disable_16(sc, exp->csoff); - EXP_UNLOCK(exp); -} - -/* NB: we only define what's needed by ata+uart */ -struct bus_space cambria_exp_bs_tag = { - /* mapping/unmapping */ - .bs_map = generic_bs_map, - .bs_unmap = generic_bs_unmap, - - /* barrier */ - .bs_barrier = generic_bs_barrier, - - /* read (single) */ - .bs_r_1 = cambria_bs_r_1, - .bs_r_2 = cambria_bs_r_2, - - /* write (single) */ - .bs_w_1 = cambria_bs_w_1, - .bs_w_2 = cambria_bs_w_2, - - /* read multiple */ - .bs_rm_2 = cambria_bs_rm_2, - .bs_rm_2_s = cambria_bs_rm_2_s, - - /* write multiple */ - .bs_wm_2 = cambria_bs_wm_2, - .bs_wm_2_s = cambria_bs_wm_2_s, -}; - -void -cambria_exp_bus_init(struct ixp425_softc *sc) -{ - static struct expbus_softc c3; /* NB: no need to malloc */ - uint32_t cs3; - - KASSERT(cpu_is_ixp43x(), ("wrong cpu type")); - - c3.sc = sc; - c3.csoff = EXP_TIMING_CS3_OFFSET; - EXP_LOCK_INIT(&c3); - cambria_exp_bs_tag.bs_privdata = &c3; - - cs3 = EXP_BUS_READ_4(sc, EXP_TIMING_CS3_OFFSET); - /* XXX force slowest possible timings and byte mode */ - EXP_BUS_WRITE_4(sc, EXP_TIMING_CS3_OFFSET, - cs3 | (EXP_T1|EXP_T2|EXP_T3|EXP_T4|EXP_T5) | - EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN); - - /* XXX force GPIO 3+4 for GPS+RS485 uarts */ - ixp425_set_gpio(sc, 3, GPIO_TYPE_EDG_RISING); - ixp425_set_gpio(sc, 4, GPIO_TYPE_EDG_RISING); -} diff --git a/sys/arm/xscale/ixp425/cambria_fled.c b/sys/arm/xscale/ixp425/cambria_fled.c deleted file mode 100644 index d7fec5e22cb9..000000000000 --- a/sys/arm/xscale/ixp425/cambria_fled.c +++ /dev/null @@ -1,112 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2008 Sam Leffler. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); -/* - * Cambria Front Panel LED sitting on the I2C bus. - */ -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include "iicbus_if.h" - -#define IIC_M_WR 0 /* write operation */ -#define LED_ADDR 0xae /* slave address */ - -struct fled_softc { - struct cdev *sc_led; -}; - -static int -fled_probe(device_t dev) -{ - device_set_desc(dev, "Gateworks Cambria Front Panel LED"); - return 0; -} - -static void -fled_cb(void *arg, int onoff) -{ - uint8_t data[1]; - struct iic_msg msgs[1] = { - { LED_ADDR, IIC_M_WR, 1, data }, - }; - device_t dev = arg; - - data[0] = (onoff == 0); /* NB: low true */ - (void) iicbus_transfer(dev, msgs, 1); -} - -static int -fled_attach(device_t dev) -{ - struct fled_softc *sc = device_get_softc(dev); - - sc->sc_led = led_create(fled_cb, dev, "front"); - - fled_cb(dev, 1); /* Turn on LED */ - - return 0; -} - -static int -fled_detach(device_t dev) -{ - struct fled_softc *sc = device_get_softc(dev); - - if (sc->sc_led != NULL) - led_destroy(sc->sc_led); - - return 0; -} - -static device_method_t fled_methods[] = { - DEVMETHOD(device_probe, fled_probe), - DEVMETHOD(device_attach, fled_attach), - DEVMETHOD(device_detach, fled_detach), - - {0, 0}, -}; - -static driver_t fled_driver = { - "fled", - fled_methods, - sizeof(struct fled_softc), -}; -static devclass_t fled_devclass; - -DRIVER_MODULE(fled, iicbus, fled_driver, fled_devclass, 0, 0); -MODULE_VERSION(fled, 1); -MODULE_DEPEND(fled, iicbus, 1, 1, 1); diff --git a/sys/arm/xscale/ixp425/cambria_gpio.c b/sys/arm/xscale/ixp425/cambria_gpio.c deleted file mode 100644 index 8ed35c4e2084..000000000000 --- a/sys/arm/xscale/ixp425/cambria_gpio.c +++ /dev/null @@ -1,505 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2010, Andrew Thompson - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice unmodified, this list of conditions, and the following - * disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * GPIO driver for Gateworks Cambria - * - * Note: - * The Cambria PLD does not set the i2c ack bit after each write, if we used the - * regular iicbus interface it would abort the xfer after the address byte - * times out and not write our latch. To get around this we grab the iicbus and - * then do our own bit banging. This is a compromise to changing all the iicbb - * device methods to allow a flag to be passed down and is similir to how Linux - * does it. - * - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include "iicbb_if.h" -#include "gpio_if.h" - -#define IIC_M_WR 0 /* write operation */ -#define PLD_ADDR 0xac /* slave address */ - -#define I2C_DELAY 10 - -#define GPIO_CONF_CLR(sc, reg, mask) \ - GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, reg) &~ (mask)) -#define GPIO_CONF_SET(sc, reg, mask) \ - GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, reg) | (mask)) - -#define GPIO_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) -#define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) -#define GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) - -#define GPIO_PINS 5 -struct cambria_gpio_softc { - device_t sc_dev; - device_t sc_busdev; - bus_space_tag_t sc_iot; - bus_space_handle_t sc_gpio_ioh; - struct mtx sc_mtx; - struct gpio_pin sc_pins[GPIO_PINS]; - uint8_t sc_latch; - uint8_t sc_val; -}; - -struct cambria_gpio_pin { - const char *name; - int pin; - int flags; -}; - -extern struct ixp425_softc *ixp425_softc; - -static struct cambria_gpio_pin cambria_gpio_pins[GPIO_PINS] = { - { "PLD0", 0, GPIO_PIN_OUTPUT }, - { "PLD1", 1, GPIO_PIN_OUTPUT }, - { "PLD2", 2, GPIO_PIN_OUTPUT }, - { "PLD3", 3, GPIO_PIN_OUTPUT }, - { "PLD4", 4, GPIO_PIN_OUTPUT }, -}; - -/* - * Helpers - */ -static int cambria_gpio_read(struct cambria_gpio_softc *, uint32_t, unsigned int *); -static int cambria_gpio_write(struct cambria_gpio_softc *); - -/* - * Driver stuff - */ -static int cambria_gpio_probe(device_t dev); -static int cambria_gpio_attach(device_t dev); -static int cambria_gpio_detach(device_t dev); - -/* - * GPIO interface - */ -static device_t cambria_gpio_get_bus(device_t); -static int cambria_gpio_pin_max(device_t dev, int *maxpin); -static int cambria_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps); -static int cambria_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t - *flags); -static int cambria_gpio_pin_getname(device_t dev, uint32_t pin, char *name); -static int cambria_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags); -static int cambria_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value); -static int cambria_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val); -static int cambria_gpio_pin_toggle(device_t dev, uint32_t pin); - -static int -i2c_getsda(struct cambria_gpio_softc *sc) -{ - uint32_t reg; - - IXP4XX_GPIO_LOCK(); - GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT); - - reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR); - IXP4XX_GPIO_UNLOCK(); - return (reg & GPIO_I2C_SDA_BIT); -} - -static void -i2c_setsda(struct cambria_gpio_softc *sc, int val) -{ - - IXP4XX_GPIO_LOCK(); - GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SDA_BIT); - if (val) - GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT); - else - GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT); - IXP4XX_GPIO_UNLOCK(); - DELAY(I2C_DELAY); -} - -static void -i2c_setscl(struct cambria_gpio_softc *sc, int val) -{ - - IXP4XX_GPIO_LOCK(); - GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SCL_BIT); - if (val) - GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT); - else - GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT); - IXP4XX_GPIO_UNLOCK(); - DELAY(I2C_DELAY); -} - -static void -i2c_sendstart(struct cambria_gpio_softc *sc) -{ - i2c_setsda(sc, 1); - i2c_setscl(sc, 1); - i2c_setsda(sc, 0); - i2c_setscl(sc, 0); -} - -static void -i2c_sendstop(struct cambria_gpio_softc *sc) -{ - i2c_setscl(sc, 1); - i2c_setsda(sc, 1); - i2c_setscl(sc, 0); - i2c_setsda(sc, 0); -} - -static void -i2c_sendbyte(struct cambria_gpio_softc *sc, u_char data) -{ - int i; - - for (i=7; i>=0; i--) { - i2c_setsda(sc, data & (1<=0; i--) - { - i2c_setscl(sc, 1); - if (i2c_getsda(sc)) - data |= (1<sc_dev; - int error; - - error = iicbus_request_bus(device_get_parent(dev), dev, - IIC_DONTWAIT); - if (error) - return (error); - - i2c_sendstart(sc); - i2c_sendbyte(sc, PLD_ADDR | LSB); - *val = (i2c_readbyte(sc) & (1 << pin)) != 0; - i2c_sendstop(sc); - - iicbus_release_bus(device_get_parent(dev), dev); - - return (0); -} - -static int -cambria_gpio_write(struct cambria_gpio_softc *sc) -{ - device_t dev = sc->sc_dev; - int error; - - error = iicbus_request_bus(device_get_parent(dev), dev, - IIC_DONTWAIT); - if (error) - return (error); - - i2c_sendstart(sc); - i2c_sendbyte(sc, PLD_ADDR & ~LSB); - i2c_sendbyte(sc, sc->sc_latch); - i2c_sendstop(sc); - - iicbus_release_bus(device_get_parent(dev), dev); - - return (0); -} - -static device_t -cambria_gpio_get_bus(device_t dev) -{ - struct cambria_gpio_softc *sc; - - sc = device_get_softc(dev); - - return (sc->sc_busdev); -} - -static int -cambria_gpio_pin_max(device_t dev, int *maxpin) -{ - - *maxpin = GPIO_PINS - 1; - return (0); -} - -static int -cambria_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) -{ - struct cambria_gpio_softc *sc = device_get_softc(dev); - - if (pin >= GPIO_PINS) - return (EINVAL); - - *caps = sc->sc_pins[pin].gp_caps; - return (0); -} - -static int -cambria_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) -{ - struct cambria_gpio_softc *sc = device_get_softc(dev); - - if (pin >= GPIO_PINS) - return (EINVAL); - - *flags = sc->sc_pins[pin].gp_flags; - return (0); -} - -static int -cambria_gpio_pin_getname(device_t dev, uint32_t pin, char *name) -{ - struct cambria_gpio_softc *sc = device_get_softc(dev); - - if (pin >= GPIO_PINS) - return (EINVAL); - - memcpy(name, sc->sc_pins[pin].gp_name, GPIOMAXNAME); - return (0); -} - -static int -cambria_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) -{ - struct cambria_gpio_softc *sc = device_get_softc(dev); - int error; - uint8_t mask; - - mask = 1 << pin; - - if (pin >= GPIO_PINS) - return (EINVAL); - - GPIO_LOCK(sc); - sc->sc_pins[pin].gp_flags = flags; - - /* - * Writing a logical one sets the signal high and writing a logical - * zero sets the signal low. To configure a digital I/O signal as an - * input, a logical one must first be written to the data bit to - * three-state the associated output. - */ - if (flags & GPIO_PIN_INPUT || sc->sc_val & mask) - sc->sc_latch |= mask; /* input or output & high */ - else - sc->sc_latch &= ~mask; - error = cambria_gpio_write(sc); - GPIO_UNLOCK(sc); - - return (error); -} - -static int -cambria_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) -{ - struct cambria_gpio_softc *sc = device_get_softc(dev); - int error; - uint8_t mask; - - mask = 1 << pin; - - if (pin >= GPIO_PINS) - return (EINVAL); - GPIO_LOCK(sc); - if (value) - sc->sc_val |= mask; - else - sc->sc_val &= ~mask; - - if (sc->sc_pins[pin].gp_flags != GPIO_PIN_OUTPUT) { - /* just save, altering the latch will disable input */ - GPIO_UNLOCK(sc); - return (0); - } - - if (value) - sc->sc_latch |= mask; - else - sc->sc_latch &= ~mask; - error = cambria_gpio_write(sc); - GPIO_UNLOCK(sc); - - return (error); -} - -static int -cambria_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) -{ - struct cambria_gpio_softc *sc = device_get_softc(dev); - int error = 0; - - if (pin >= GPIO_PINS) - return (EINVAL); - - GPIO_LOCK(sc); - if (sc->sc_pins[pin].gp_flags == GPIO_PIN_OUTPUT) - *val = (sc->sc_latch & (1 << pin)) ? 1 : 0; - else - error = cambria_gpio_read(sc, pin, val); - GPIO_UNLOCK(sc); - - return (error); -} - -static int -cambria_gpio_pin_toggle(device_t dev, uint32_t pin) -{ - struct cambria_gpio_softc *sc = device_get_softc(dev); - int error = 0; - - if (pin >= GPIO_PINS) - return (EINVAL); - - GPIO_LOCK(sc); - sc->sc_val ^= (1 << pin); - if (sc->sc_pins[pin].gp_flags == GPIO_PIN_OUTPUT) { - sc->sc_latch ^= (1 << pin); - error = cambria_gpio_write(sc); - } - GPIO_UNLOCK(sc); - - return (error); -} - -static int -cambria_gpio_probe(device_t dev) -{ - - device_set_desc(dev, "Gateworks Cambria GPIO driver"); - return (0); -} - -static int -cambria_gpio_attach(device_t dev) -{ - struct cambria_gpio_softc *sc = device_get_softc(dev); - int pin; - - sc->sc_dev = dev; - sc->sc_iot = ixp425_softc->sc_iot; - sc->sc_gpio_ioh = ixp425_softc->sc_gpio_ioh; - - mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); - - for (pin = 0; pin < GPIO_PINS; pin++) { - struct cambria_gpio_pin *p = &cambria_gpio_pins[pin]; - - strncpy(sc->sc_pins[pin].gp_name, p->name, GPIOMAXNAME); - sc->sc_pins[pin].gp_pin = pin; - sc->sc_pins[pin].gp_caps = GPIO_PIN_INPUT|GPIO_PIN_OUTPUT; - sc->sc_pins[pin].gp_flags = 0; - cambria_gpio_pin_setflags(dev, pin, p->flags); - } - - sc->sc_busdev = gpiobus_attach_bus(dev); - if (sc->sc_busdev == NULL) { - mtx_destroy(&sc->sc_mtx); - return (ENXIO); - } - - return (0); -} - -static int -cambria_gpio_detach(device_t dev) -{ - struct cambria_gpio_softc *sc = device_get_softc(dev); - - KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized")); - - gpiobus_detach_bus(dev); - mtx_destroy(&sc->sc_mtx); - - return(0); -} - -static device_method_t cambria_gpio_methods[] = { - DEVMETHOD(device_probe, cambria_gpio_probe), - DEVMETHOD(device_attach, cambria_gpio_attach), - DEVMETHOD(device_detach, cambria_gpio_detach), - - /* GPIO protocol */ - DEVMETHOD(gpio_get_bus, cambria_gpio_get_bus), - DEVMETHOD(gpio_pin_max, cambria_gpio_pin_max), - DEVMETHOD(gpio_pin_getname, cambria_gpio_pin_getname), - DEVMETHOD(gpio_pin_getflags, cambria_gpio_pin_getflags), - DEVMETHOD(gpio_pin_getcaps, cambria_gpio_pin_getcaps), - DEVMETHOD(gpio_pin_setflags, cambria_gpio_pin_setflags), - DEVMETHOD(gpio_pin_get, cambria_gpio_pin_get), - DEVMETHOD(gpio_pin_set, cambria_gpio_pin_set), - DEVMETHOD(gpio_pin_toggle, cambria_gpio_pin_toggle), - {0, 0}, -}; - -static driver_t cambria_gpio_driver = { - "gpio", - cambria_gpio_methods, - sizeof(struct cambria_gpio_softc), -}; -static devclass_t cambria_gpio_devclass; - -DRIVER_MODULE(gpio_cambria, iicbus, cambria_gpio_driver, cambria_gpio_devclass, 0, 0); -MODULE_VERSION(gpio_cambria, 1); -MODULE_DEPEND(gpio_cambria, iicbus, 1, 1, 1); diff --git a/sys/arm/xscale/ixp425/cambria_led.c b/sys/arm/xscale/ixp425/cambria_led.c deleted file mode 100644 index 747d7df0a75c..000000000000 --- a/sys/arm/xscale/ixp425/cambria_led.c +++ /dev/null @@ -1,135 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2008 Sam Leffler. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -/* - * Gateworks Cambria Octal LED Latch driver. - */ -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include - -struct led_softc { - device_t sc_dev; - bus_space_tag_t sc_iot; - bus_space_handle_t sc_ioh; - struct cdev *sc_leds[8]; - uint8_t sc_latch; -}; - -static void -update_latch(struct led_softc *sc, int bit, int onoff) -{ - if (onoff) - sc->sc_latch &= ~bit; - else - sc->sc_latch |= bit; - bus_space_write_1(sc->sc_iot, sc->sc_ioh, 0, sc->sc_latch); -} -static void led_A(void *arg, int onoff) { update_latch(arg, 1<<0, onoff); } -static void led_B(void *arg, int onoff) { update_latch(arg, 1<<1, onoff); } -static void led_C(void *arg, int onoff) { update_latch(arg, 1<<2, onoff); } -static void led_D(void *arg, int onoff) { update_latch(arg, 1<<3, onoff); } -static void led_E(void *arg, int onoff) { update_latch(arg, 1<<4, onoff); } -static void led_F(void *arg, int onoff) { update_latch(arg, 1<<5, onoff); } -static void led_G(void *arg, int onoff) { update_latch(arg, 1<<6, onoff); } -static void led_H(void *arg, int onoff) { update_latch(arg, 1<<7, onoff); } - -static int -led_probe(device_t dev) -{ - device_set_desc(dev, "Gateworks Octal LED Latch"); - return (0); -} - -static int -led_attach(device_t dev) -{ - struct led_softc *sc = device_get_softc(dev); - struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); - - sc->sc_dev = dev; - sc->sc_iot = sa->sc_iot; - /* NB: write anywhere works, use first location */ - if (bus_space_map(sc->sc_iot, CAMBRIA_OCTAL_LED_HWBASE, sizeof(uint8_t), - 0, &sc->sc_ioh)) { - device_printf(dev, "cannot map LED latch (0x%lx)", - CAMBRIA_OCTAL_LED_HWBASE); - return ENXIO; - } - - sc->sc_leds[0] = led_create(led_A, sc, "A"); - sc->sc_leds[1] = led_create(led_B, sc, "B"); - sc->sc_leds[2] = led_create(led_C, sc, "C"); - sc->sc_leds[3] = led_create(led_D, sc, "D"); - sc->sc_leds[4] = led_create(led_E, sc, "E"); - sc->sc_leds[5] = led_create(led_F, sc, "F"); - sc->sc_leds[6] = led_create(led_G, sc, "G"); - sc->sc_leds[7] = led_create(led_H, sc, "H"); - - return 0; -} - -static int -led_detach(device_t dev) -{ - struct led_softc *sc = device_get_softc(dev); - int i; - - for (i = 0; i < 8; i++) { - struct cdev *led = sc->sc_leds[i]; - if (led != NULL) - led_destroy(led); - } - return (0); -} - -static device_method_t led_methods[] = { - DEVMETHOD(device_probe, led_probe), - DEVMETHOD(device_attach, led_attach), - DEVMETHOD(device_detach, led_detach), - - {0, 0}, -}; - -static driver_t led_driver = { - "led_cambria", - led_methods, - sizeof(struct led_softc), -}; -static devclass_t led_devclass; -DRIVER_MODULE(led_cambria, ixp, led_driver, led_devclass, 0, 0); diff --git a/sys/arm/xscale/ixp425/files.avila b/sys/arm/xscale/ixp425/files.avila deleted file mode 100644 index 5008e0910a12..000000000000 --- a/sys/arm/xscale/ixp425/files.avila +++ /dev/null @@ -1,10 +0,0 @@ -#$FreeBSD$ -arm/xscale/ixp425/avila_machdep.c standard -arm/xscale/ixp425/avila_ata.c optional avila_ata -arm/xscale/ixp425/avila_led.c optional avila_led -arm/xscale/ixp425/avila_gpio.c optional avila_gpio -arm/xscale/ixp425/cambria_exp_space.c standard -arm/xscale/ixp425/cambria_fled.c optional cambria_fled -arm/xscale/ixp425/cambria_led.c optional cambria_led -arm/xscale/ixp425/cambria_gpio.c optional cambria_gpio -arm/xscale/ixp425/ixdp425_pci.c optional pci diff --git a/sys/arm/xscale/ixp425/files.ixp425 b/sys/arm/xscale/ixp425/files.ixp425 deleted file mode 100644 index 66a7320114c1..000000000000 --- a/sys/arm/xscale/ixp425/files.ixp425 +++ /dev/null @@ -1,46 +0,0 @@ -#$FreeBSD$ -arm/xscale/ixp425/ixp425.c standard -arm/xscale/ixp425/ixp425_mem.c standard -arm/xscale/ixp425/ixp425_space.c standard -arm/xscale/ixp425/ixp425_timer.c standard -arm/xscale/ixp425/ixp425_wdog.c optional ixpwdog -arm/xscale/ixp425/ixp425_iic.c optional ixpiic -arm/xscale/ixp425/ixp425_pci.c optional pci -arm/xscale/ixp425/ixp425_pci_asm.S optional pci -arm/xscale/ixp425/ixp425_pci_space.c optional pci -arm/xscale/ixp425/uart_cpu_ixp425.c optional uart -arm/xscale/ixp425/uart_bus_ixp425.c optional uart -arm/xscale/ixp425/ixp425_a4x_space.c optional uart -arm/xscale/ixp425/ixp425_a4x_io.S optional uart -dev/cfi/cfi_bus_ixp4xx.c optional cfi -dev/uart/uart_dev_ns8250.c optional uart -# -# NPE-based Ethernet support (requires qmgr also). -# -arm/xscale/ixp425/if_npe.c optional npe -arm/xscale/ixp425/ixp425_npe.c optional npe -ixp425_npe_fw.c optional npe_fw \ - compile-with "${AWK} -f $S/tools/fw_stub.awk IxNpeMicrocode.dat:npe_fw -mnpe -c${.TARGET}" \ - no-implicit-rule before-depend local \ - clean "ixp425_npe_fw.c" -# -# NB: ld encodes the path in the binary symbols generated for the -# firmware image so link the file to the object directory to -# get known values for reference in the _fw.c file. -# -IxNpeMicrocode.fwo optional npe_fw \ - dependency "IxNpeMicrocode.dat" \ - compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} IxNpeMicrocode.dat" \ - no-implicit-rule \ - clean "IxNpeMicrocode.fwo" -IxNpeMicrocode.dat optional npe_fw \ - dependency "$S/contrib/dev/npe/IxNpeMicrocode.dat.uu" \ - compile-with "uudecode < $S/contrib/dev/npe/IxNpeMicrocode.dat.uu" \ - no-obj no-implicit-rule \ - clean "IxNpeMicrocode.dat" -# -# Q-Manager support -# -arm/xscale/ixp425/ixp425_qmgr.c optional qmgr -# -dev/usb/controller/ehci_ixp4xx.c optional ehci usb diff --git a/sys/arm/xscale/ixp425/if_npe.c b/sys/arm/xscale/ixp425/if_npe.c deleted file mode 100644 index dbeee47fc261..000000000000 --- a/sys/arm/xscale/ixp425/if_npe.c +++ /dev/null @@ -1,1781 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006-2008 Sam Leffler. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -/* - * Intel XScale NPE Ethernet driver. - * - * This driver handles the two ports present on the IXP425. - * Packet processing is done by the Network Processing Engines - * (NPE's) that work together with a MAC and PHY. The MAC - * is also mapped to the XScale cpu; the PHY is accessed via - * the MAC. NPE-XScale communication happens through h/w - * queues managed by the Q Manager block. - * - * The code here replaces the ethAcc, ethMii, and ethDB classes - * in the Intel Access Library (IAL) and the OS-specific driver. - * - * XXX add vlan support - */ -#ifdef HAVE_KERNEL_OPTION_HEADERS -#include "opt_device_polling.h" -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef INET -#include -#include -#include -#include -#endif - -#include -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include - -#include "miibus_if.h" - -/* - * XXX: For the main bus dma tag. Can go away if the new method to get the - * dma tag from the parent got MFC'd into RELENG_6. - */ -extern struct ixp425_softc *ixp425_softc; - -struct npebuf { - struct npebuf *ix_next; /* chain to next buffer */ - void *ix_m; /* backpointer to mbuf */ - bus_dmamap_t ix_map; /* bus dma map for associated data */ - struct npehwbuf *ix_hw; /* associated h/w block */ - uint32_t ix_neaddr; /* phys address of ix_hw */ -}; - -struct npedma { - const char* name; - int nbuf; /* # npebuf's allocated */ - bus_dma_tag_t mtag; /* bus dma tag for mbuf data */ - struct npehwbuf *hwbuf; /* NPE h/w buffers */ - bus_dma_tag_t buf_tag; /* tag+map for NPE buffers */ - bus_dmamap_t buf_map; - bus_addr_t buf_phys; /* phys addr of buffers */ - struct npebuf *buf; /* s/w buffers (1-1 w/ h/w) */ -}; - -struct npe_softc { - /* XXX mii requires this be first; do not move! */ - struct ifnet *sc_ifp; /* ifnet pointer */ - struct mtx sc_mtx; /* basically a perimeter lock */ - device_t sc_dev; - bus_space_tag_t sc_iot; - bus_space_handle_t sc_ioh; /* MAC register window */ - device_t sc_mii; /* child miibus */ - bus_space_handle_t sc_miih; /* MII register window */ - int sc_npeid; - struct ixpnpe_softc *sc_npe; /* NPE support */ - int sc_debug; /* DPRINTF* control */ - int sc_tickinterval; - struct callout tick_ch; /* Tick callout */ - int npe_watchdog_timer; - struct npedma txdma; - struct npebuf *tx_free; /* list of free tx buffers */ - struct npedma rxdma; - bus_addr_t buf_phys; /* XXX for returning a value */ - int rx_qid; /* rx qid */ - int rx_freeqid; /* rx free buffers qid */ - int tx_qid; /* tx qid */ - int tx_doneqid; /* tx completed qid */ - struct ifmib_iso_8802_3 mibdata; - bus_dma_tag_t sc_stats_tag; /* bus dma tag for stats block */ - struct npestats *sc_stats; - bus_dmamap_t sc_stats_map; - bus_addr_t sc_stats_phys; /* phys addr of sc_stats */ - struct npestats sc_totals; /* accumulated sc_stats */ -}; - -/* - * Static configuration for IXP425. The tx and - * rx free Q id's are fixed by the NPE microcode. The - * rx Q id's are programmed to be separate to simplify - * multi-port processing. It may be better to handle - * all traffic through one Q (as done by the Intel drivers). - * - * Note that the PHY's are accessible only from MAC B on the - * IXP425 and from MAC C on other devices. This and other - * platform-specific assumptions are handled with hints. - */ -static const struct { - uint32_t macbase; - uint32_t miibase; - int phy; /* phy id */ - uint8_t rx_qid; - uint8_t rx_freeqid; - uint8_t tx_qid; - uint8_t tx_doneqid; -} npeconfig[NPE_MAX] = { - [NPE_A] = { - .macbase = IXP435_MAC_A_HWBASE, - .miibase = IXP425_MAC_C_HWBASE, - .phy = 2, - .rx_qid = 4, - .rx_freeqid = 26, - .tx_qid = 23, - .tx_doneqid = 31 - }, - [NPE_B] = { - .macbase = IXP425_MAC_B_HWBASE, - .miibase = IXP425_MAC_B_HWBASE, - .phy = 0, - .rx_qid = 4, - .rx_freeqid = 27, - .tx_qid = 24, - .tx_doneqid = 31 - }, - [NPE_C] = { - .macbase = IXP425_MAC_C_HWBASE, - .miibase = IXP425_MAC_B_HWBASE, - .phy = 1, - .rx_qid = 12, - .rx_freeqid = 28, - .tx_qid = 25, - .tx_doneqid = 31 - }, -}; -static struct npe_softc *npes[NPE_MAX]; /* NB: indexed by npeid */ - -static __inline uint32_t -RD4(struct npe_softc *sc, bus_size_t off) -{ - return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); -} - -static __inline void -WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) -{ - bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); -} - -#define NPE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) -#define NPE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) -#define NPE_LOCK_INIT(_sc) \ - mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ - MTX_NETWORK_LOCK, MTX_DEF) -#define NPE_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); -#define NPE_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); -#define NPE_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); - -static devclass_t npe_devclass; - -static int override_npeid(device_t, const char *resname, int *val); -static int npe_activate(device_t dev); -static void npe_deactivate(device_t dev); -static int npe_ifmedia_update(struct ifnet *ifp); -static void npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr); -static void npe_setmac(struct npe_softc *sc, u_char *eaddr); -static void npe_getmac(struct npe_softc *sc, u_char *eaddr); -static void npe_txdone(int qid, void *arg); -static int npe_rxbuf_init(struct npe_softc *, struct npebuf *, - struct mbuf *); -static int npe_rxdone(int qid, void *arg); -static void npeinit(void *); -static void npestart_locked(struct ifnet *); -static void npestart(struct ifnet *); -static void npestop(struct npe_softc *); -static void npewatchdog(struct npe_softc *); -static int npeioctl(struct ifnet * ifp, u_long, caddr_t); - -static int npe_setrxqosentry(struct npe_softc *, int classix, - int trafclass, int qid); -static int npe_setportaddress(struct npe_softc *, const uint8_t mac[]); -static int npe_setfirewallmode(struct npe_softc *, int onoff); -static int npe_updatestats(struct npe_softc *); -#if 0 -static int npe_getstats(struct npe_softc *); -static uint32_t npe_getimageid(struct npe_softc *); -static int npe_setloopback(struct npe_softc *, int ena); -#endif - -/* NB: all tx done processing goes through one queue */ -static int tx_doneqid = -1; - -static SYSCTL_NODE(_hw, OID_AUTO, npe, CTLFLAG_RD, 0, - "IXP4XX NPE driver parameters"); - -static int npe_debug = 0; -SYSCTL_INT(_hw_npe, OID_AUTO, debug, CTLFLAG_RWTUN, &npe_debug, - 0, "IXP4XX NPE network interface debug msgs"); -#define DPRINTF(sc, fmt, ...) do { \ - if (sc->sc_debug) device_printf(sc->sc_dev, fmt, __VA_ARGS__); \ -} while (0) -#define DPRINTFn(n, sc, fmt, ...) do { \ - if (sc->sc_debug >= n) device_printf(sc->sc_dev, fmt, __VA_ARGS__);\ -} while (0) -static int npe_tickinterval = 3; /* npe_tick frequency (secs) */ -SYSCTL_INT(_hw_npe, OID_AUTO, tickinterval, CTLFLAG_RDTUN, &npe_tickinterval, - 0, "periodic work interval (secs)"); - -static int npe_rxbuf = 64; /* # rx buffers to allocate */ -SYSCTL_INT(_hw_npe, OID_AUTO, rxbuf, CTLFLAG_RDTUN, &npe_rxbuf, - 0, "rx buffers allocated"); -static int npe_txbuf = 128; /* # tx buffers to allocate */ -SYSCTL_INT(_hw_npe, OID_AUTO, txbuf, CTLFLAG_RDTUN, &npe_txbuf, - 0, "tx buffers allocated"); - -static int -unit2npeid(int unit) -{ - static const int npeidmap[2][3] = { - /* on 425 A is for HSS, B & C are for Ethernet */ - { NPE_B, NPE_C, -1 }, /* IXP425 */ - /* 435 only has A & C, order C then A */ - { NPE_C, NPE_A, -1 }, /* IXP435 */ - }; - /* XXX check feature register instead */ - return (unit < 3 ? npeidmap[ - (cpu_ident() & CPU_ID_CPU_MASK) == CPU_ID_IXP435][unit] : -1); -} - -static int -npe_probe(device_t dev) -{ - static const char *desc[NPE_MAX] = { - [NPE_A] = "IXP NPE-A", - [NPE_B] = "IXP NPE-B", - [NPE_C] = "IXP NPE-C" - }; - int unit = device_get_unit(dev); - int npeid; - - if (unit > 2 || - (ixp4xx_read_feature_bits() & - (unit == 0 ? EXP_FCTRL_ETH0 : EXP_FCTRL_ETH1)) == 0) - return EINVAL; - - npeid = -1; - if (!override_npeid(dev, "npeid", &npeid)) - npeid = unit2npeid(unit); - if (npeid == -1) { - device_printf(dev, "unit %d not supported\n", unit); - return EINVAL; - } - device_set_desc(dev, desc[npeid]); - return 0; -} - -static int -npe_attach(device_t dev) -{ - struct npe_softc *sc = device_get_softc(dev); - struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); - struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); - struct sysctl_oid *tree = device_get_sysctl_tree(dev); - struct ifnet *ifp; - int error; - u_char eaddr[6]; - - sc->sc_dev = dev; - sc->sc_iot = sa->sc_iot; - NPE_LOCK_INIT(sc); - callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); - sc->sc_debug = npe_debug; - sc->sc_tickinterval = npe_tickinterval; - - ifp = if_alloc(IFT_ETHER); - if (ifp == NULL) { - device_printf(dev, "cannot allocate ifnet\n"); - error = EIO; /* XXX */ - goto out; - } - /* NB: must be setup prior to invoking mii code */ - sc->sc_ifp = ifp; - - error = npe_activate(dev); - if (error) { - device_printf(dev, "cannot activate npe\n"); - goto out; - } - - npe_getmac(sc, eaddr); - - ifp->if_softc = sc; - if_initname(ifp, device_get_name(dev), device_get_unit(dev)); - ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; - ifp->if_start = npestart; - ifp->if_ioctl = npeioctl; - ifp->if_init = npeinit; - IFQ_SET_MAXLEN(&ifp->if_snd, sc->txdma.nbuf - 1); - ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; - IFQ_SET_READY(&ifp->if_snd); - ifp->if_linkmib = &sc->mibdata; - ifp->if_linkmiblen = sizeof(sc->mibdata); - sc->mibdata.dot3Compliance = DOT3COMPLIANCE_STATS; - /* device supports oversided vlan frames */ - ifp->if_capabilities |= IFCAP_VLAN_MTU; - ifp->if_capenable = ifp->if_capabilities; -#ifdef DEVICE_POLLING - ifp->if_capabilities |= IFCAP_POLLING; -#endif - - SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "debug", - CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs"); - SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tickinterval", - CTLFLAG_RW, &sc->sc_tickinterval, 0, "periodic work frequency"); - SYSCTL_ADD_STRUCT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "stats", - CTLFLAG_RD, &sc->sc_totals, npestats, "onboard stats"); - - ether_ifattach(ifp, eaddr); - return 0; -out: - if (ifp != NULL) - if_free(ifp); - NPE_LOCK_DESTROY(sc); - npe_deactivate(dev); - return error; -} - -static int -npe_detach(device_t dev) -{ - struct npe_softc *sc = device_get_softc(dev); - struct ifnet *ifp = sc->sc_ifp; - -#ifdef DEVICE_POLLING - if (ifp->if_capenable & IFCAP_POLLING) - ether_poll_deregister(ifp); -#endif - npestop(sc); - if (ifp != NULL) { - ether_ifdetach(ifp); - if_free(ifp); - } - NPE_LOCK_DESTROY(sc); - npe_deactivate(dev); - return 0; -} - -/* - * Compute and install the multicast filter. - */ -static void -npe_setmcast(struct npe_softc *sc) -{ - struct ifnet *ifp = sc->sc_ifp; - uint8_t mask[ETHER_ADDR_LEN], addr[ETHER_ADDR_LEN]; - int i; - - if (ifp->if_flags & IFF_PROMISC) { - memset(mask, 0, ETHER_ADDR_LEN); - memset(addr, 0, ETHER_ADDR_LEN); - } else if (ifp->if_flags & IFF_ALLMULTI) { - static const uint8_t allmulti[ETHER_ADDR_LEN] = - { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 }; - memcpy(mask, allmulti, ETHER_ADDR_LEN); - memcpy(addr, allmulti, ETHER_ADDR_LEN); - } else { - uint8_t clr[ETHER_ADDR_LEN], set[ETHER_ADDR_LEN]; - struct ifmultiaddr *ifma; - const uint8_t *mac; - - memset(clr, 0, ETHER_ADDR_LEN); - memset(set, 0xff, ETHER_ADDR_LEN); - - if_maddr_rlock(ifp); - CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { - if (ifma->ifma_addr->sa_family != AF_LINK) - continue; - mac = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); - for (i = 0; i < ETHER_ADDR_LEN; i++) { - clr[i] |= mac[i]; - set[i] &= mac[i]; - } - } - if_maddr_runlock(ifp); - - for (i = 0; i < ETHER_ADDR_LEN; i++) { - mask[i] = set[i] | ~clr[i]; - addr[i] = set[i]; - } - } - - /* - * Write the mask and address registers. - */ - for (i = 0; i < ETHER_ADDR_LEN; i++) { - WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); - WR4(sc, NPE_MAC_ADDR(i), addr[i]); - } -} - -static void -npe_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) -{ - struct npe_softc *sc; - - if (error != 0) - return; - sc = (struct npe_softc *)arg; - sc->buf_phys = segs[0].ds_addr; -} - -static int -npe_dma_setup(struct npe_softc *sc, struct npedma *dma, - const char *name, int nbuf, int maxseg) -{ - int error, i; - - memset(dma, 0, sizeof(*dma)); - - dma->name = name; - dma->nbuf = nbuf; - - /* DMA tag for mapped mbufs */ - error = bus_dma_tag_create(ixp425_softc->sc_dmat, 1, 0, - BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, - MCLBYTES, maxseg, MCLBYTES, 0, - busdma_lock_mutex, &sc->sc_mtx, &dma->mtag); - if (error != 0) { - device_printf(sc->sc_dev, "unable to create %s mbuf dma tag, " - "error %u\n", dma->name, error); - return error; - } - - /* DMA tag and map for the NPE buffers */ - error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, - BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, - nbuf * sizeof(struct npehwbuf), 1, - nbuf * sizeof(struct npehwbuf), 0, - busdma_lock_mutex, &sc->sc_mtx, &dma->buf_tag); - if (error != 0) { - device_printf(sc->sc_dev, - "unable to create %s npebuf dma tag, error %u\n", - dma->name, error); - return error; - } - if (bus_dmamem_alloc(dma->buf_tag, (void **)&dma->hwbuf, - BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, - &dma->buf_map) != 0) { - device_printf(sc->sc_dev, - "unable to allocate memory for %s h/w buffers, error %u\n", - dma->name, error); - return error; - } - /* XXX M_TEMP */ - dma->buf = malloc(nbuf * sizeof(struct npebuf), M_TEMP, M_NOWAIT | M_ZERO); - if (dma->buf == NULL) { - device_printf(sc->sc_dev, - "unable to allocate memory for %s s/w buffers\n", - dma->name); - return error; - } - if (bus_dmamap_load(dma->buf_tag, dma->buf_map, - dma->hwbuf, nbuf*sizeof(struct npehwbuf), npe_getaddr, sc, 0) != 0) { - device_printf(sc->sc_dev, - "unable to map memory for %s h/w buffers, error %u\n", - dma->name, error); - return error; - } - dma->buf_phys = sc->buf_phys; - for (i = 0; i < dma->nbuf; i++) { - struct npebuf *npe = &dma->buf[i]; - struct npehwbuf *hw = &dma->hwbuf[i]; - - /* calculate offset to shared area */ - npe->ix_neaddr = dma->buf_phys + - ((uintptr_t)hw - (uintptr_t)dma->hwbuf); - KASSERT((npe->ix_neaddr & 0x1f) == 0, - ("ixpbuf misaligned, PA 0x%x", npe->ix_neaddr)); - error = bus_dmamap_create(dma->mtag, BUS_DMA_NOWAIT, - &npe->ix_map); - if (error != 0) { - device_printf(sc->sc_dev, - "unable to create dmamap for %s buffer %u, " - "error %u\n", dma->name, i, error); - return error; - } - npe->ix_hw = hw; - } - bus_dmamap_sync(dma->buf_tag, dma->buf_map, BUS_DMASYNC_PREWRITE); - return 0; -} - -static void -npe_dma_destroy(struct npe_softc *sc, struct npedma *dma) -{ - int i; - - if (dma->hwbuf != NULL) { - for (i = 0; i < dma->nbuf; i++) { - struct npebuf *npe = &dma->buf[i]; - bus_dmamap_destroy(dma->mtag, npe->ix_map); - } - bus_dmamap_unload(dma->buf_tag, dma->buf_map); - bus_dmamem_free(dma->buf_tag, dma->hwbuf, dma->buf_map); - } - if (dma->buf != NULL) - free(dma->buf, M_TEMP); - if (dma->buf_tag) - bus_dma_tag_destroy(dma->buf_tag); - if (dma->mtag) - bus_dma_tag_destroy(dma->mtag); - memset(dma, 0, sizeof(*dma)); -} - -static int -override_addr(device_t dev, const char *resname, int *base) -{ - int unit = device_get_unit(dev); - const char *resval; - - /* XXX warn for wrong hint type */ - if (resource_string_value("npe", unit, resname, &resval) != 0) - return 0; - switch (resval[0]) { - case 'A': - *base = IXP435_MAC_A_HWBASE; - break; - case 'B': - *base = IXP425_MAC_B_HWBASE; - break; - case 'C': - *base = IXP425_MAC_C_HWBASE; - break; - default: - device_printf(dev, "Warning, bad value %s for " - "npe.%d.%s ignored\n", resval, unit, resname); - return 0; - } - if (bootverbose) - device_printf(dev, "using npe.%d.%s=%s override\n", - unit, resname, resval); - return 1; -} - -static int -override_npeid(device_t dev, const char *resname, int *npeid) -{ - int unit = device_get_unit(dev); - const char *resval; - - /* XXX warn for wrong hint type */ - if (resource_string_value("npe", unit, resname, &resval) != 0) - return 0; - switch (resval[0]) { - case 'A': *npeid = NPE_A; break; - case 'B': *npeid = NPE_B; break; - case 'C': *npeid = NPE_C; break; - default: - device_printf(dev, "Warning, bad value %s for " - "npe.%d.%s ignored\n", resval, unit, resname); - return 0; - } - if (bootverbose) - device_printf(dev, "using npe.%d.%s=%s override\n", - unit, resname, resval); - return 1; -} - -static int -override_unit(device_t dev, const char *resname, int *val, int min, int max) -{ - int unit = device_get_unit(dev); - int resval; - - if (resource_int_value("npe", unit, resname, &resval) != 0) - return 0; - if (!(min <= resval && resval <= max)) { - device_printf(dev, "Warning, bad value %d for npe.%d.%s " - "ignored (value must be [%d-%d])\n", resval, unit, - resname, min, max); - return 0; - } - if (bootverbose) - device_printf(dev, "using npe.%d.%s=%d override\n", - unit, resname, resval); - *val = resval; - return 1; -} - -static void -npe_mac_reset(struct npe_softc *sc) -{ - /* - * Reset MAC core. - */ - WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); - DELAY(NPE_MAC_RESET_DELAY); - /* configure MAC to generate MDC clock */ - WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); -} - -static int -npe_activate(device_t dev) -{ - struct npe_softc *sc = device_get_softc(dev); - int error, i, macbase, miibase, phy; - - /* - * Setup NEP ID, MAC, and MII bindings. We allow override - * via hints to handle unexpected board configs. - */ - if (!override_npeid(dev, "npeid", &sc->sc_npeid)) - sc->sc_npeid = unit2npeid(device_get_unit(dev)); - sc->sc_npe = ixpnpe_attach(dev, sc->sc_npeid); - if (sc->sc_npe == NULL) { - device_printf(dev, "cannot attach ixpnpe\n"); - return EIO; /* XXX */ - } - - /* MAC */ - if (!override_addr(dev, "mac", &macbase)) - macbase = npeconfig[sc->sc_npeid].macbase; - if (bootverbose) - device_printf(sc->sc_dev, "MAC at 0x%x\n", macbase); - if (bus_space_map(sc->sc_iot, macbase, IXP425_REG_SIZE, 0, &sc->sc_ioh)) { - device_printf(dev, "cannot map mac registers 0x%x:0x%x\n", - macbase, IXP425_REG_SIZE); - return ENOMEM; - } - - /* PHY */ - if (!override_unit(dev, "phy", &phy, 0, MII_NPHY - 1)) - phy = npeconfig[sc->sc_npeid].phy; - if (!override_addr(dev, "mii", &miibase)) - miibase = npeconfig[sc->sc_npeid].miibase; - if (bootverbose) - device_printf(sc->sc_dev, "MII at 0x%x\n", miibase); - if (miibase != macbase) { - /* - * PHY is mapped through a different MAC, setup an - * additional mapping for frobbing the PHY registers. - */ - if (bus_space_map(sc->sc_iot, miibase, IXP425_REG_SIZE, 0, &sc->sc_miih)) { - device_printf(dev, - "cannot map MII registers 0x%x:0x%x\n", - miibase, IXP425_REG_SIZE); - return ENOMEM; - } - } else - sc->sc_miih = sc->sc_ioh; - - /* - * Load NPE firmware and start it running. - */ - error = ixpnpe_init(sc->sc_npe); - if (error != 0) { - device_printf(dev, "cannot init NPE (error %d)\n", error); - return error; - } - - /* attach PHY */ - error = mii_attach(dev, &sc->sc_mii, sc->sc_ifp, npe_ifmedia_update, - npe_ifmedia_status, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); - if (error != 0) { - device_printf(dev, "attaching PHYs failed\n"); - return error; - } - - error = npe_dma_setup(sc, &sc->txdma, "tx", npe_txbuf, NPE_MAXSEG); - if (error != 0) - return error; - error = npe_dma_setup(sc, &sc->rxdma, "rx", npe_rxbuf, 1); - if (error != 0) - return error; - - /* setup statistics block */ - error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0, - BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, - sizeof(struct npestats), 1, sizeof(struct npestats), 0, - busdma_lock_mutex, &sc->sc_mtx, &sc->sc_stats_tag); - if (error != 0) { - device_printf(sc->sc_dev, "unable to create stats tag, " - "error %u\n", error); - return error; - } - if (bus_dmamem_alloc(sc->sc_stats_tag, (void **)&sc->sc_stats, - BUS_DMA_NOWAIT, &sc->sc_stats_map) != 0) { - device_printf(sc->sc_dev, - "unable to allocate memory for stats block, error %u\n", - error); - return error; - } - if (bus_dmamap_load(sc->sc_stats_tag, sc->sc_stats_map, - sc->sc_stats, sizeof(struct npestats), npe_getaddr, sc, 0) != 0) { - device_printf(sc->sc_dev, - "unable to load memory for stats block, error %u\n", - error); - return error; - } - sc->sc_stats_phys = sc->buf_phys; - - /* - * Setup h/w rx/tx queues. There are four q's: - * rx inbound q of rx'd frames - * rx_free pool of ixpbuf's for receiving frames - * tx outbound q of frames to send - * tx_done q of tx frames that have been processed - * - * The NPE handles the actual tx/rx process and the q manager - * handles the queues. The driver just writes entries to the - * q manager mailbox's and gets callbacks when there are rx'd - * frames to process or tx'd frames to reap. These callbacks - * are controlled by the q configurations; e.g. we get a - * callback when tx_done has 2 or more frames to process and - * when the rx q has at least one frame. These setings can - * changed at the time the q is configured. - */ - sc->rx_qid = npeconfig[sc->sc_npeid].rx_qid; - ixpqmgr_qconfig(sc->rx_qid, npe_rxbuf, 0, 1, - IX_QMGR_Q_SOURCE_ID_NOT_E, (qconfig_hand_t *)npe_rxdone, sc); - sc->rx_freeqid = npeconfig[sc->sc_npeid].rx_freeqid; - ixpqmgr_qconfig(sc->rx_freeqid, npe_rxbuf, 0, npe_rxbuf/2, 0, NULL, sc); - /* - * Setup the NPE to direct all traffic to rx_qid. - * When QoS is enabled in the firmware there are - * 8 traffic classes; otherwise just 4. - */ - for (i = 0; i < 8; i++) - npe_setrxqosentry(sc, i, 0, sc->rx_qid); - - /* disable firewall mode just in case (should be off) */ - npe_setfirewallmode(sc, 0); - - sc->tx_qid = npeconfig[sc->sc_npeid].tx_qid; - sc->tx_doneqid = npeconfig[sc->sc_npeid].tx_doneqid; - ixpqmgr_qconfig(sc->tx_qid, npe_txbuf, 0, npe_txbuf, 0, NULL, sc); - if (tx_doneqid == -1) { - ixpqmgr_qconfig(sc->tx_doneqid, npe_txbuf, 0, 2, - IX_QMGR_Q_SOURCE_ID_NOT_E, npe_txdone, sc); - tx_doneqid = sc->tx_doneqid; - } - - KASSERT(npes[sc->sc_npeid] == NULL, - ("npe %u already setup", sc->sc_npeid)); - npes[sc->sc_npeid] = sc; - - return 0; -} - -static void -npe_deactivate(device_t dev) -{ - struct npe_softc *sc = device_get_softc(dev); - - npes[sc->sc_npeid] = NULL; - - /* XXX disable q's */ - if (sc->sc_npe != NULL) { - ixpnpe_stop(sc->sc_npe); - ixpnpe_detach(sc->sc_npe); - } - if (sc->sc_stats != NULL) { - bus_dmamap_unload(sc->sc_stats_tag, sc->sc_stats_map); - bus_dmamem_free(sc->sc_stats_tag, sc->sc_stats, - sc->sc_stats_map); - } - if (sc->sc_stats_tag != NULL) - bus_dma_tag_destroy(sc->sc_stats_tag); - npe_dma_destroy(sc, &sc->txdma); - npe_dma_destroy(sc, &sc->rxdma); - bus_generic_detach(sc->sc_dev); - if (sc->sc_mii != NULL) - device_delete_child(sc->sc_dev, sc->sc_mii); -} - -/* - * Change media according to request. - */ -static int -npe_ifmedia_update(struct ifnet *ifp) -{ - struct npe_softc *sc = ifp->if_softc; - struct mii_data *mii; - - mii = device_get_softc(sc->sc_mii); - NPE_LOCK(sc); - mii_mediachg(mii); - /* XXX push state ourself? */ - NPE_UNLOCK(sc); - return (0); -} - -/* - * Notify the world which media we're using. - */ -static void -npe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) -{ - struct npe_softc *sc = ifp->if_softc; - struct mii_data *mii; - - mii = device_get_softc(sc->sc_mii); - NPE_LOCK(sc); - mii_pollstat(mii); - ifmr->ifm_active = mii->mii_media_active; - ifmr->ifm_status = mii->mii_media_status; - NPE_UNLOCK(sc); -} - -static void -npe_addstats(struct npe_softc *sc) -{ -#define NPEADD(x) sc->sc_totals.x += be32toh(ns->x) -#define MIBADD(x) do { sc->mibdata.x += be32toh(ns->x); NPEADD(x); } while (0) - struct ifnet *ifp = sc->sc_ifp; - struct npestats *ns = sc->sc_stats; - - MIBADD(dot3StatsAlignmentErrors); - MIBADD(dot3StatsFCSErrors); - MIBADD(dot3StatsInternalMacReceiveErrors); - NPEADD(RxOverrunDiscards); - NPEADD(RxLearnedEntryDiscards); - NPEADD(RxLargeFramesDiscards); - NPEADD(RxSTPBlockedDiscards); - NPEADD(RxVLANTypeFilterDiscards); - NPEADD(RxVLANIdFilterDiscards); - NPEADD(RxInvalidSourceDiscards); - NPEADD(RxBlackListDiscards); - NPEADD(RxWhiteListDiscards); - NPEADD(RxUnderflowEntryDiscards); - MIBADD(dot3StatsSingleCollisionFrames); - MIBADD(dot3StatsMultipleCollisionFrames); - MIBADD(dot3StatsDeferredTransmissions); - MIBADD(dot3StatsLateCollisions); - MIBADD(dot3StatsExcessiveCollisions); - MIBADD(dot3StatsInternalMacTransmitErrors); - MIBADD(dot3StatsCarrierSenseErrors); - NPEADD(TxLargeFrameDiscards); - NPEADD(TxVLANIdFilterDiscards); - - sc->mibdata.dot3StatsFrameTooLongs += - be32toh(ns->RxLargeFramesDiscards) - + be32toh(ns->TxLargeFrameDiscards); - sc->mibdata.dot3StatsMissedFrames += - be32toh(ns->RxOverrunDiscards) - + be32toh(ns->RxUnderflowEntryDiscards); - - if_inc_counter(ifp, IFCOUNTER_OERRORS, - be32toh(ns->dot3StatsInternalMacTransmitErrors) + - be32toh(ns->dot3StatsCarrierSenseErrors) + - be32toh(ns->TxVLANIdFilterDiscards)); - if_inc_counter(ifp, IFCOUNTER_IERRORS, - be32toh(ns->dot3StatsFCSErrors) + - be32toh(ns->dot3StatsInternalMacReceiveErrors) + - be32toh(ns->RxOverrunDiscards) + - be32toh(ns->RxUnderflowEntryDiscards)); - if_inc_counter(ifp, IFCOUNTER_COLLISIONS, - be32toh(ns->dot3StatsSingleCollisionFrames) + - be32toh(ns->dot3StatsMultipleCollisionFrames)); -#undef NPEADD -#undef MIBADD -} - -static void -npe_tick(void *xsc) -{ -#define ACK (NPE_RESETSTATS << NPE_MAC_MSGID_SHL) - struct npe_softc *sc = xsc; - struct mii_data *mii = device_get_softc(sc->sc_mii); - uint32_t msg[2]; - - NPE_ASSERT_LOCKED(sc); - - /* - * NB: to avoid sleeping with the softc lock held we - * split the NPE msg processing into two parts. The - * request for statistics is sent w/o waiting for a - * reply and then on the next tick we retrieve the - * results. This works because npe_tick is the only - * code that talks via the mailbox's (except at setup). - * This likely can be handled better. - */ - if (ixpnpe_recvmsg_async(sc->sc_npe, msg) == 0 && msg[0] == ACK) { - bus_dmamap_sync(sc->sc_stats_tag, sc->sc_stats_map, - BUS_DMASYNC_POSTREAD); - npe_addstats(sc); - } - npe_updatestats(sc); - mii_tick(mii); - - npewatchdog(sc); - - /* schedule next poll */ - callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); -#undef ACK -} - -static void -npe_setmac(struct npe_softc *sc, u_char *eaddr) -{ - WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); - WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); - WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); - WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); - WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); - WR4(sc, NPE_MAC_UNI_ADDR_6, eaddr[5]); -} - -static void -npe_getmac(struct npe_softc *sc, u_char *eaddr) -{ - /* NB: the unicast address appears to be loaded from EEPROM on reset */ - eaddr[0] = RD4(sc, NPE_MAC_UNI_ADDR_1) & 0xff; - eaddr[1] = RD4(sc, NPE_MAC_UNI_ADDR_2) & 0xff; - eaddr[2] = RD4(sc, NPE_MAC_UNI_ADDR_3) & 0xff; - eaddr[3] = RD4(sc, NPE_MAC_UNI_ADDR_4) & 0xff; - eaddr[4] = RD4(sc, NPE_MAC_UNI_ADDR_5) & 0xff; - eaddr[5] = RD4(sc, NPE_MAC_UNI_ADDR_6) & 0xff; -} - -struct txdone { - struct npebuf *head; - struct npebuf **tail; - int count; -}; - -static __inline void -npe_txdone_finish(struct npe_softc *sc, const struct txdone *td) -{ - struct ifnet *ifp = sc->sc_ifp; - - NPE_LOCK(sc); - *td->tail = sc->tx_free; - sc->tx_free = td->head; - /* - * We're no longer busy, so clear the busy flag and call the - * start routine to xmit more packets. - */ - if_inc_counter(ifp, IFCOUNTER_OPACKETS, td->count); - ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; - sc->npe_watchdog_timer = 0; - npestart_locked(ifp); - NPE_UNLOCK(sc); -} - -/* - * Q manager callback on tx done queue. Reap mbufs - * and return tx buffers to the free list. Finally - * restart output. Note the microcode has only one - * txdone q wired into it so we must use the NPE ID - * returned with each npehwbuf to decide where to - * send buffers. - */ -static void -npe_txdone(int qid, void *arg) -{ -#define P2V(a, dma) \ - &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] - struct npe_softc *sc0 = arg; - struct npe_softc *sc; - struct npebuf *npe; - struct txdone *td, q[NPE_MAX]; - uint32_t entry; - - q[NPE_A].tail = &q[NPE_A].head; q[NPE_A].count = 0; - q[NPE_B].tail = &q[NPE_B].head; q[NPE_B].count = 0; - q[NPE_C].tail = &q[NPE_C].head; q[NPE_C].count = 0; - /* XXX max # at a time? */ - while (ixpqmgr_qread(qid, &entry) == 0) { - DPRINTF(sc0, "%s: entry 0x%x NPE %u port %u\n", - __func__, entry, NPE_QM_Q_NPE(entry), NPE_QM_Q_PORT(entry)); - - sc = npes[NPE_QM_Q_NPE(entry)]; - npe = P2V(NPE_QM_Q_ADDR(entry), &sc->txdma); - m_freem(npe->ix_m); - npe->ix_m = NULL; - - td = &q[NPE_QM_Q_NPE(entry)]; - *td->tail = npe; - td->tail = &npe->ix_next; - td->count++; - } - - if (q[NPE_A].count) - npe_txdone_finish(npes[NPE_A], &q[NPE_A]); - if (q[NPE_B].count) - npe_txdone_finish(npes[NPE_B], &q[NPE_B]); - if (q[NPE_C].count) - npe_txdone_finish(npes[NPE_C], &q[NPE_C]); -#undef P2V -} - -static int -npe_rxbuf_init(struct npe_softc *sc, struct npebuf *npe, struct mbuf *m) -{ - bus_dma_segment_t segs[1]; - struct npedma *dma = &sc->rxdma; - struct npehwbuf *hw; - int error, nseg; - - if (m == NULL) { - m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); - if (m == NULL) - return ENOBUFS; - } - KASSERT(m->m_ext.ext_size >= 1536 + ETHER_ALIGN, - ("ext_size %d", m->m_ext.ext_size)); - m->m_pkthdr.len = m->m_len = 1536; - /* backload payload and align ip hdr */ - m->m_data = m->m_ext.ext_buf + (m->m_ext.ext_size - (1536+ETHER_ALIGN)); - bus_dmamap_unload(dma->mtag, npe->ix_map); - error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, m, - segs, &nseg, 0); - if (error != 0) { - m_freem(m); - return error; - } - hw = npe->ix_hw; - hw->ix_ne[0].data = htobe32(segs[0].ds_addr); - /* NB: NPE requires length be a multiple of 64 */ - /* NB: buffer length is shifted in word */ - hw->ix_ne[0].len = htobe32(segs[0].ds_len << 16); - hw->ix_ne[0].next = 0; - bus_dmamap_sync(dma->buf_tag, dma->buf_map, - BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); - npe->ix_m = m; - /* Flush the memory in the mbuf */ - bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREREAD); - return 0; -} - -/* - * RX q processing for a specific NPE. Claim entries - * from the hardware queue and pass the frames up the - * stack. Pass the rx buffers to the free list. - */ -static int -npe_rxdone(int qid, void *arg) -{ -#define P2V(a, dma) \ - &(dma)->buf[((a) - (dma)->buf_phys) / sizeof(struct npehwbuf)] - struct npe_softc *sc = arg; - struct npedma *dma = &sc->rxdma; - uint32_t entry; - int rx_npkts = 0; - - while (ixpqmgr_qread(qid, &entry) == 0) { - struct npebuf *npe = P2V(NPE_QM_Q_ADDR(entry), dma); - struct mbuf *m; - - bus_dmamap_sync(dma->buf_tag, dma->buf_map, - BUS_DMASYNC_POSTREAD); - DPRINTF(sc, "%s: entry 0x%x neaddr 0x%x ne_len 0x%x\n", - __func__, entry, npe->ix_neaddr, npe->ix_hw->ix_ne[0].len); - /* - * Allocate a new mbuf to replenish the rx buffer. - * If doing so fails we drop the rx'd frame so we - * can reuse the previous mbuf. When we're able to - * allocate a new mbuf dispatch the mbuf w/ rx'd - * data up the stack and replace it with the newly - * allocated one. - */ - m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); - if (m != NULL) { - struct mbuf *mrx = npe->ix_m; - struct npehwbuf *hw = npe->ix_hw; - struct ifnet *ifp = sc->sc_ifp; - - /* Flush mbuf memory for rx'd data */ - bus_dmamap_sync(dma->mtag, npe->ix_map, - BUS_DMASYNC_POSTREAD); - - /* set m_len etc. per rx frame size */ - mrx->m_len = be32toh(hw->ix_ne[0].len) & 0xffff; - mrx->m_pkthdr.len = mrx->m_len; - mrx->m_pkthdr.rcvif = ifp; - - if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); - ifp->if_input(ifp, mrx); - rx_npkts++; - } else { - /* discard frame and re-use mbuf */ - m = npe->ix_m; - } - if (npe_rxbuf_init(sc, npe, m) == 0) { - /* return npe buf to rx free list */ - ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); - } else { - /* XXX should not happen */ - } - } - return rx_npkts; -#undef P2V -} - -#ifdef DEVICE_POLLING -static int -npe_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) -{ - struct npe_softc *sc = ifp->if_softc; - int rx_npkts = 0; - - if (ifp->if_drv_flags & IFF_DRV_RUNNING) { - rx_npkts = npe_rxdone(sc->rx_qid, sc); - npe_txdone(sc->tx_doneqid, sc); /* XXX polls both NPE's */ - } - return rx_npkts; -} -#endif /* DEVICE_POLLING */ - -static void -npe_startxmit(struct npe_softc *sc) -{ - struct npedma *dma = &sc->txdma; - int i; - - NPE_ASSERT_LOCKED(sc); - sc->tx_free = NULL; - for (i = 0; i < dma->nbuf; i++) { - struct npebuf *npe = &dma->buf[i]; - if (npe->ix_m != NULL) { - /* NB: should not happen */ - device_printf(sc->sc_dev, - "%s: free mbuf at entry %u\n", __func__, i); - m_freem(npe->ix_m); - } - npe->ix_m = NULL; - npe->ix_next = sc->tx_free; - sc->tx_free = npe; - } -} - -static void -npe_startrecv(struct npe_softc *sc) -{ - struct npedma *dma = &sc->rxdma; - struct npebuf *npe; - int i; - - NPE_ASSERT_LOCKED(sc); - for (i = 0; i < dma->nbuf; i++) { - npe = &dma->buf[i]; - npe_rxbuf_init(sc, npe, npe->ix_m); - /* set npe buf on rx free list */ - ixpqmgr_qwrite(sc->rx_freeqid, npe->ix_neaddr); - } -} - -/* - * Reset and initialize the chip - */ -static void -npeinit_locked(void *xsc) -{ - struct npe_softc *sc = xsc; - struct ifnet *ifp = sc->sc_ifp; - - NPE_ASSERT_LOCKED(sc); -if (ifp->if_drv_flags & IFF_DRV_RUNNING) return;/*XXX*/ - - /* - * Reset MAC core. - */ - npe_mac_reset(sc); - - /* disable transmitter and reciver in the MAC */ - WR4(sc, NPE_MAC_RX_CNTRL1, - RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); - WR4(sc, NPE_MAC_TX_CNTRL1, - RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); - - /* - * Set the MAC core registers. - */ - WR4(sc, NPE_MAC_INT_CLK_THRESH, 0x1); /* clock ratio: for ipx4xx */ - WR4(sc, NPE_MAC_TX_CNTRL2, 0xf); /* max retries */ - WR4(sc, NPE_MAC_RANDOM_SEED, 0x8); /* LFSR back-off seed */ - /* thresholds determined by NPE firmware FS */ - WR4(sc, NPE_MAC_THRESH_P_EMPTY, 0x12); - WR4(sc, NPE_MAC_THRESH_P_FULL, 0x30); - WR4(sc, NPE_MAC_BUF_SIZE_TX, 0x8); /* tx fifo threshold (bytes) */ - WR4(sc, NPE_MAC_TX_DEFER, 0x15); /* for single deferral */ - WR4(sc, NPE_MAC_RX_DEFER, 0x16); /* deferral on inter-frame gap*/ - WR4(sc, NPE_MAC_TX_TWO_DEFER_1, 0x8); /* for 2-part deferral */ - WR4(sc, NPE_MAC_TX_TWO_DEFER_2, 0x7); /* for 2-part deferral */ - WR4(sc, NPE_MAC_SLOT_TIME, 0x80); /* assumes MII mode */ - - WR4(sc, NPE_MAC_TX_CNTRL1, - NPE_TX_CNTRL1_RETRY /* retry failed xmits */ - | NPE_TX_CNTRL1_FCS_EN /* append FCS */ - | NPE_TX_CNTRL1_2DEFER /* 2-part deferal */ - | NPE_TX_CNTRL1_PAD_EN); /* pad runt frames */ - /* XXX pad strip? */ - /* ena pause frame handling */ - WR4(sc, NPE_MAC_RX_CNTRL1, NPE_RX_CNTRL1_PAUSE_EN); - WR4(sc, NPE_MAC_RX_CNTRL2, 0); - - npe_setmac(sc, IF_LLADDR(ifp)); - npe_setportaddress(sc, IF_LLADDR(ifp)); - npe_setmcast(sc); - - npe_startxmit(sc); - npe_startrecv(sc); - - ifp->if_drv_flags |= IFF_DRV_RUNNING; - ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; - sc->npe_watchdog_timer = 0; /* just in case */ - - /* enable transmitter and reciver in the MAC */ - WR4(sc, NPE_MAC_RX_CNTRL1, - RD4(sc, NPE_MAC_RX_CNTRL1) | NPE_RX_CNTRL1_RX_EN); - WR4(sc, NPE_MAC_TX_CNTRL1, - RD4(sc, NPE_MAC_TX_CNTRL1) | NPE_TX_CNTRL1_TX_EN); - - callout_reset(&sc->tick_ch, sc->sc_tickinterval * hz, npe_tick, sc); -} - -static void -npeinit(void *xsc) -{ - struct npe_softc *sc = xsc; - NPE_LOCK(sc); - npeinit_locked(sc); - NPE_UNLOCK(sc); -} - -/* - * Dequeue packets and place on the h/w transmit queue. - */ -static void -npestart_locked(struct ifnet *ifp) -{ - struct npe_softc *sc = ifp->if_softc; - struct npebuf *npe; - struct npehwbuf *hw; - struct mbuf *m, *n; - struct npedma *dma = &sc->txdma; - bus_dma_segment_t segs[NPE_MAXSEG]; - int nseg, len, error, i; - uint32_t next; - - NPE_ASSERT_LOCKED(sc); - /* XXX can this happen? */ - if (ifp->if_drv_flags & IFF_DRV_OACTIVE) - return; - - while (sc->tx_free != NULL) { - IFQ_DRV_DEQUEUE(&ifp->if_snd, m); - if (m == NULL) { - /* XXX? */ - ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; - return; - } - npe = sc->tx_free; - bus_dmamap_unload(dma->mtag, npe->ix_map); - error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, - m, segs, &nseg, 0); - if (error == EFBIG) { - n = m_collapse(m, M_NOWAIT, NPE_MAXSEG); - if (n == NULL) { - if_printf(ifp, "%s: too many fragments %u\n", - __func__, nseg); - m_freem(m); - return; /* XXX? */ - } - m = n; - error = bus_dmamap_load_mbuf_sg(dma->mtag, npe->ix_map, - m, segs, &nseg, 0); - } - if (error != 0 || nseg == 0) { - if_printf(ifp, "%s: error %u nseg %u\n", - __func__, error, nseg); - m_freem(m); - return; /* XXX? */ - } - sc->tx_free = npe->ix_next; - - bus_dmamap_sync(dma->mtag, npe->ix_map, BUS_DMASYNC_PREWRITE); - - /* - * Tap off here if there is a bpf listener. - */ - BPF_MTAP(ifp, m); - - npe->ix_m = m; - hw = npe->ix_hw; - len = m->m_pkthdr.len; - next = npe->ix_neaddr + sizeof(hw->ix_ne[0]); - for (i = 0; i < nseg; i++) { - hw->ix_ne[i].data = htobe32(segs[i].ds_addr); - hw->ix_ne[i].len = htobe32((segs[i].ds_len<<16) | len); - hw->ix_ne[i].next = htobe32(next); - - len = 0; /* zero for segments > 1 */ - next += sizeof(hw->ix_ne[0]); - } - hw->ix_ne[i-1].next = 0; /* zero last in chain */ - bus_dmamap_sync(dma->buf_tag, dma->buf_map, - BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); - - DPRINTF(sc, "%s: qwrite(%u, 0x%x) ne_data %x ne_len 0x%x\n", - __func__, sc->tx_qid, npe->ix_neaddr, - hw->ix_ne[0].data, hw->ix_ne[0].len); - /* stick it on the tx q */ - /* XXX add vlan priority */ - ixpqmgr_qwrite(sc->tx_qid, npe->ix_neaddr); - - sc->npe_watchdog_timer = 5; - } - if (sc->tx_free == NULL) - ifp->if_drv_flags |= IFF_DRV_OACTIVE; -} - -void -npestart(struct ifnet *ifp) -{ - struct npe_softc *sc = ifp->if_softc; - NPE_LOCK(sc); - npestart_locked(ifp); - NPE_UNLOCK(sc); -} - -static void -npe_stopxmit(struct npe_softc *sc) -{ - struct npedma *dma = &sc->txdma; - int i; - - NPE_ASSERT_LOCKED(sc); - - /* XXX qmgr */ - for (i = 0; i < dma->nbuf; i++) { - struct npebuf *npe = &dma->buf[i]; - - if (npe->ix_m != NULL) { - bus_dmamap_unload(dma->mtag, npe->ix_map); - m_freem(npe->ix_m); - npe->ix_m = NULL; - } - } -} - -static void -npe_stoprecv(struct npe_softc *sc) -{ - struct npedma *dma = &sc->rxdma; - int i; - - NPE_ASSERT_LOCKED(sc); - - /* XXX qmgr */ - for (i = 0; i < dma->nbuf; i++) { - struct npebuf *npe = &dma->buf[i]; - - if (npe->ix_m != NULL) { - bus_dmamap_unload(dma->mtag, npe->ix_map); - m_freem(npe->ix_m); - npe->ix_m = NULL; - } - } -} - -/* - * Turn off interrupts, and stop the nic. - */ -void -npestop(struct npe_softc *sc) -{ - struct ifnet *ifp = sc->sc_ifp; - - /* disable transmitter and reciver in the MAC */ - WR4(sc, NPE_MAC_RX_CNTRL1, - RD4(sc, NPE_MAC_RX_CNTRL1) &~ NPE_RX_CNTRL1_RX_EN); - WR4(sc, NPE_MAC_TX_CNTRL1, - RD4(sc, NPE_MAC_TX_CNTRL1) &~ NPE_TX_CNTRL1_TX_EN); - - sc->npe_watchdog_timer = 0; - ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); - - callout_stop(&sc->tick_ch); - - npe_stopxmit(sc); - npe_stoprecv(sc); - /* XXX go into loopback & drain q's? */ - /* XXX but beware of disabling tx above */ - - /* - * The MAC core rx/tx disable may leave the MAC hardware in an - * unpredictable state. A hw reset is executed before resetting - * all the MAC parameters to a known value. - */ - WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); - DELAY(NPE_MAC_RESET_DELAY); - WR4(sc, NPE_MAC_INT_CLK_THRESH, NPE_MAC_INT_CLK_THRESH_DEFAULT); - WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); -} - -void -npewatchdog(struct npe_softc *sc) -{ - NPE_ASSERT_LOCKED(sc); - - if (sc->npe_watchdog_timer == 0 || --sc->npe_watchdog_timer != 0) - return; - - device_printf(sc->sc_dev, "watchdog timeout\n"); - if_inc_counter(sc->sc_ifp, IFCOUNTER_OERRORS, 1); - - npeinit_locked(sc); -} - -static int -npeioctl(struct ifnet *ifp, u_long cmd, caddr_t data) -{ - struct npe_softc *sc = ifp->if_softc; - struct mii_data *mii; - struct ifreq *ifr = (struct ifreq *)data; - int error = 0; -#ifdef DEVICE_POLLING - int mask; -#endif - - switch (cmd) { - case SIOCSIFFLAGS: - NPE_LOCK(sc); - if ((ifp->if_flags & IFF_UP) == 0 && - ifp->if_drv_flags & IFF_DRV_RUNNING) { - ifp->if_drv_flags &= ~IFF_DRV_RUNNING; - npestop(sc); - } else { - /* reinitialize card on any parameter change */ - npeinit_locked(sc); - } - NPE_UNLOCK(sc); - break; - - case SIOCADDMULTI: - case SIOCDELMULTI: - /* update multicast filter list. */ - NPE_LOCK(sc); - npe_setmcast(sc); - NPE_UNLOCK(sc); - error = 0; - break; - - case SIOCSIFMEDIA: - case SIOCGIFMEDIA: - mii = device_get_softc(sc->sc_mii); - error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); - break; - -#ifdef DEVICE_POLLING - case SIOCSIFCAP: - mask = ifp->if_capenable ^ ifr->ifr_reqcap; - if (mask & IFCAP_POLLING) { - if (ifr->ifr_reqcap & IFCAP_POLLING) { - error = ether_poll_register(npe_poll, ifp); - if (error) - return error; - NPE_LOCK(sc); - /* disable callbacks XXX txdone is shared */ - ixpqmgr_notify_disable(sc->rx_qid); - ixpqmgr_notify_disable(sc->tx_doneqid); - ifp->if_capenable |= IFCAP_POLLING; - NPE_UNLOCK(sc); - } else { - error = ether_poll_deregister(ifp); - /* NB: always enable qmgr callbacks */ - NPE_LOCK(sc); - /* enable qmgr callbacks */ - ixpqmgr_notify_enable(sc->rx_qid, - IX_QMGR_Q_SOURCE_ID_NOT_E); - ixpqmgr_notify_enable(sc->tx_doneqid, - IX_QMGR_Q_SOURCE_ID_NOT_E); - ifp->if_capenable &= ~IFCAP_POLLING; - NPE_UNLOCK(sc); - } - } - break; -#endif - default: - error = ether_ioctl(ifp, cmd, data); - break; - } - return error; -} - -/* - * Setup a traffic class -> rx queue mapping. - */ -static int -npe_setrxqosentry(struct npe_softc *sc, int classix, int trafclass, int qid) -{ - uint32_t msg[2]; - - msg[0] = (NPE_SETRXQOSENTRY << 24) | (sc->sc_npeid << 20) | classix; - msg[1] = (trafclass << 24) | (1 << 23) | (qid << 16) | (qid << 4); - return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); -} - -static int -npe_setportaddress(struct npe_softc *sc, const uint8_t mac[ETHER_ADDR_LEN]) -{ - uint32_t msg[2]; - - msg[0] = (NPE_SETPORTADDRESS << 24) - | (sc->sc_npeid << 20) - | (mac[0] << 8) - | (mac[1] << 0); - msg[1] = (mac[2] << 24) - | (mac[3] << 16) - | (mac[4] << 8) - | (mac[5] << 0); - return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); -} - -static int -npe_setfirewallmode(struct npe_softc *sc, int onoff) -{ - uint32_t msg[2]; - - /* XXX honor onoff */ - msg[0] = (NPE_SETFIREWALLMODE << 24) | (sc->sc_npeid << 20); - msg[1] = 0; - return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); -} - -/* - * Update and reset the statistics in the NPE. - */ -static int -npe_updatestats(struct npe_softc *sc) -{ - uint32_t msg[2]; - - msg[0] = NPE_RESETSTATS << NPE_MAC_MSGID_SHL; - msg[1] = sc->sc_stats_phys; /* physical address of stat block */ - return ixpnpe_sendmsg_async(sc->sc_npe, msg); -} - -#if 0 -/* - * Get the current statistics block. - */ -static int -npe_getstats(struct npe_softc *sc) -{ - uint32_t msg[2]; - - msg[0] = NPE_GETSTATS << NPE_MAC_MSGID_SHL; - msg[1] = sc->sc_stats_phys; /* physical address of stat block */ - return ixpnpe_sendandrecvmsg(sc->sc_npe, msg, msg); -} - -/* - * Query the image id of the loaded firmware. - */ -static uint32_t -npe_getimageid(struct npe_softc *sc) -{ - uint32_t msg[2]; - - msg[0] = NPE_GETSTATUS << NPE_MAC_MSGID_SHL; - msg[1] = 0; - return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg) == 0 ? msg[1] : 0; -} - -/* - * Enable/disable loopback. - */ -static int -npe_setloopback(struct npe_softc *sc, int ena) -{ - uint32_t msg[2]; - - msg[0] = (NPE_SETLOOPBACK << NPE_MAC_MSGID_SHL) | (ena != 0); - msg[1] = 0; - return ixpnpe_sendandrecvmsg_sync(sc->sc_npe, msg, msg); -} -#endif - -static void -npe_child_detached(device_t dev, device_t child) -{ - struct npe_softc *sc; - - sc = device_get_softc(dev); - if (child == sc->sc_mii) - sc->sc_mii = NULL; -} - -/* - * MII bus support routines. - */ -#define MII_RD4(sc, reg) bus_space_read_4(sc->sc_iot, sc->sc_miih, reg) -#define MII_WR4(sc, reg, v) \ - bus_space_write_4(sc->sc_iot, sc->sc_miih, reg, v) - -static uint32_t -npe_mii_mdio_read(struct npe_softc *sc, int reg) -{ - uint32_t v; - - /* NB: registers are known to be sequential */ - v = (MII_RD4(sc, reg+0) & 0xff) << 0; - v |= (MII_RD4(sc, reg+4) & 0xff) << 8; - v |= (MII_RD4(sc, reg+8) & 0xff) << 16; - v |= (MII_RD4(sc, reg+12) & 0xff) << 24; - return v; -} - -static void -npe_mii_mdio_write(struct npe_softc *sc, int reg, uint32_t cmd) -{ - /* NB: registers are known to be sequential */ - MII_WR4(sc, reg+0, cmd & 0xff); - MII_WR4(sc, reg+4, (cmd >> 8) & 0xff); - MII_WR4(sc, reg+8, (cmd >> 16) & 0xff); - MII_WR4(sc, reg+12, (cmd >> 24) & 0xff); -} - -static int -npe_mii_mdio_wait(struct npe_softc *sc) -{ - uint32_t v; - int i; - - /* NB: typically this takes 25-30 trips */ - for (i = 0; i < 1000; i++) { - v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_CMD); - if ((v & NPE_MII_GO) == 0) - return 1; - DELAY(1); - } - device_printf(sc->sc_dev, "%s: timeout after ~1ms, cmd 0x%x\n", - __func__, v); - return 0; /* NB: timeout */ -} - -static int -npe_miibus_readreg(device_t dev, int phy, int reg) -{ - struct npe_softc *sc = device_get_softc(dev); - uint32_t v; - - v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) | NPE_MII_GO; - npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); - if (npe_mii_mdio_wait(sc)) - v = npe_mii_mdio_read(sc, NPE_MAC_MDIO_STS); - else - v = 0xffff | NPE_MII_READ_FAIL; - return (v & NPE_MII_READ_FAIL) ? 0xffff : (v & 0xffff); -} - -static int -npe_miibus_writereg(device_t dev, int phy, int reg, int data) -{ - struct npe_softc *sc = device_get_softc(dev); - uint32_t v; - - v = (phy << NPE_MII_ADDR_SHL) | (reg << NPE_MII_REG_SHL) - | data | NPE_MII_WRITE - | NPE_MII_GO; - npe_mii_mdio_write(sc, NPE_MAC_MDIO_CMD, v); - /* XXX complain about timeout */ - (void) npe_mii_mdio_wait(sc); - return (0); -} - -static void -npe_miibus_statchg(device_t dev) -{ - struct npe_softc *sc = device_get_softc(dev); - struct mii_data *mii = device_get_softc(sc->sc_mii); - uint32_t tx1, rx1; - - /* sync MAC duplex state */ - tx1 = RD4(sc, NPE_MAC_TX_CNTRL1); - rx1 = RD4(sc, NPE_MAC_RX_CNTRL1); - if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { - tx1 &= ~NPE_TX_CNTRL1_DUPLEX; - rx1 |= NPE_RX_CNTRL1_PAUSE_EN; - } else { - tx1 |= NPE_TX_CNTRL1_DUPLEX; - rx1 &= ~NPE_RX_CNTRL1_PAUSE_EN; - } - WR4(sc, NPE_MAC_RX_CNTRL1, rx1); - WR4(sc, NPE_MAC_TX_CNTRL1, tx1); -} - -static device_method_t npe_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, npe_probe), - DEVMETHOD(device_attach, npe_attach), - DEVMETHOD(device_detach, npe_detach), - - /* Bus interface */ - DEVMETHOD(bus_child_detached, npe_child_detached), - - /* MII interface */ - DEVMETHOD(miibus_readreg, npe_miibus_readreg), - DEVMETHOD(miibus_writereg, npe_miibus_writereg), - DEVMETHOD(miibus_statchg, npe_miibus_statchg), - - { 0, 0 } -}; - -static driver_t npe_driver = { - "npe", - npe_methods, - sizeof(struct npe_softc), -}; - -DRIVER_MODULE(npe, ixp, npe_driver, npe_devclass, 0, 0); -DRIVER_MODULE(miibus, npe, miibus_driver, miibus_devclass, 0, 0); -MODULE_DEPEND(npe, ixpqmgr, 1, 1, 1); -MODULE_DEPEND(npe, miibus, 1, 1, 1); -MODULE_DEPEND(npe, ether, 1, 1, 1); diff --git a/sys/arm/xscale/ixp425/if_npereg.h b/sys/arm/xscale/ixp425/if_npereg.h deleted file mode 100644 index b9adf47b97d9..000000000000 --- a/sys/arm/xscale/ixp425/if_npereg.h +++ /dev/null @@ -1,283 +0,0 @@ -/*- - * Copyright (c) 2006 Sam Leffler, Errno Consulting - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - * - * $FreeBSD$ - */ - -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2001-2005, Intel Corporation. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef ARM_XSCALE_IF_NPEREG_H -#define ARM_XSCALE_IF_NPEREG_H - -/* - * NPE/NPE tx/rx descriptor format. This is just the area - * shared with ucode running in the NPE; the driver-specific - * state is defined in the driver. The shared area must be - * cacheline-aligned. We allocate NPE_MAXSEG "descriptors" - * per buffer; this allows us to do minimal s/g. The number - * of descriptors can be expanded but doing so uses memory - * so should be done with care. - * - * The driver sets up buffers in uncached memory. - */ -#define NPE_MAXSEG 3 /* empirically selected */ - -struct npehwbuf { - struct { /* NPE shared area, cacheline aligned */ - uint32_t next; /* phys addr of next segment */ - uint32_t len; /* buffer/segment length (bytes) */ - uint32_t data; /* phys addr of data segment */ - uint32_t pad[5]; /* pad to cacheline */ - } ix_ne[NPE_MAXSEG]; -}; - -#define NPE_FRAME_SIZE_DEFAULT 1536 -#define NPE_FRAME_SIZE_MAX (65536-64) -#define NPE_FRAME_SIZE_MIN 64 - -/* - * Queue Manager-related definitions. - * - * These define the layout of 32-bit Q entries passed - * between the host cpu and the NPE's. - */ -#define NPE_QM_Q_NPE(e) (((e)>>0)&0x3) /* NPE ID */ -#define NPE_QM_Q_PORT(e) (((e)>>3)&0x1) /* Port ID */ -#define NPE_QM_Q_PRIO(e) (((e)>>0)&0x3) /* 802.1d priority */ -#define NPE_QM_Q_ADDR(e) ((e)&0xfffffffe0) /* phys address */ - -/* - * Host->NPE requests written to the shared mailbox. - * The NPE writes the same value back as an ACK. - */ -#define NPE_GETSTATUS 0x00 /* get firmware revision */ -#define NPE_SETPORTADDRESS 0x01 /* set port id and mac address */ -#define NPE_GETMACADDRDB 0x02 /* upload filter database */ -#define NPE_SETMACADDRDB 0x03 /* download filter database */ -#define NPE_GETSTATS 0x04 /* get statistics */ -#define NPE_RESETSTATS 0x05 /* reset stats + return result */ -#define NPE_SETMAXFRAME 0x06 /* configure max tx/rx frame lengths */ -#define NPE_SETRXTAGMODE 0x07 /* configure VLAN rx operating mode */ -#define NPE_SETDEFRXVID 0x08 /* set def VLAN tag + traffic class */ -#define NPE_SETRXQOSENTRY 0x0b /* map user pri -> QoS class+rx qid */ -#define NPE_SETFIREWALLMODE 0x0e /* config firewall services */ -#define NPE_SETLOOPBACK 0x12 /* enable/disable loopback */ -/* ... XXX more */ - -#define NPE_MAC_MSGID_SHL 24 -#define NPE_MAC_PORTID_SHL 16 - -/* - * MAC register definitions; see section - * 15.2 of the Intel Developers Manual. - */ -#define NPE_MAC_TX_CNTRL1 0x000 -#define NPE_MAC_TX_CNTRL2 0x004 -#define NPE_MAC_RX_CNTRL1 0x010 -#define NPE_MAC_RX_CNTRL2 0x014 -#define NPE_MAC_RANDOM_SEED 0x020 -#define NPE_MAC_THRESH_P_EMPTY 0x030 -#define NPE_MAC_THRESH_P_FULL 0x038 -#define NPE_MAC_BUF_SIZE_TX 0x040 -#define NPE_MAC_TX_DEFER 0x050 -#define NPE_MAC_RX_DEFER 0x054 -#define NPE_MAC_TX_TWO_DEFER_1 0x060 -#define NPE_MAC_TX_TWO_DEFER_2 0x064 -#define NPE_MAC_SLOT_TIME 0x070 -#define NPE_MAC_MDIO_CMD_1 0x080 -#define NPE_MAC_MDIO_CMD_2 0x084 -#define NPE_MAC_MDIO_CMD_3 0x088 -#define NPE_MAC_MDIO_CMD_4 0x08c -#define NPE_MAC_MDIO_STS_1 0x090 -#define NPE_MAC_MDIO_STS_2 0x094 -#define NPE_MAC_MDIO_STS_3 0x098 -#define NPE_MAC_MDIO_STS_4 0x09c -#define NPE_MAC_ADDR_MASK_1 0x0A0 -#define NPE_MAC_ADDR_MASK_2 0x0A4 -#define NPE_MAC_ADDR_MASK_3 0x0A8 -#define NPE_MAC_ADDR_MASK_4 0x0AC -#define NPE_MAC_ADDR_MASK_5 0x0B0 -#define NPE_MAC_ADDR_MASK_6 0x0B4 -#define NPE_MAC_ADDR_1 0x0C0 -#define NPE_MAC_ADDR_2 0x0C4 -#define NPE_MAC_ADDR_3 0x0C8 -#define NPE_MAC_ADDR_4 0x0CC -#define NPE_MAC_ADDR_5 0x0D0 -#define NPE_MAC_ADDR_6 0x0D4 -#define NPE_MAC_INT_CLK_THRESH 0x0E0 -#define NPE_MAC_UNI_ADDR_1 0x0F0 -#define NPE_MAC_UNI_ADDR_2 0x0F4 -#define NPE_MAC_UNI_ADDR_3 0x0F8 -#define NPE_MAC_UNI_ADDR_4 0x0FC -#define NPE_MAC_UNI_ADDR_5 0x100 -#define NPE_MAC_UNI_ADDR_6 0x104 -#define NPE_MAC_CORE_CNTRL 0x1FC - -#define NPE_MAC_ADDR_MASK(i) (NPE_MAC_ADDR_MASK_1 + ((i)<<2)) -#define NPE_MAC_ADDR(i) (NPE_MAC_ADDR_1 + ((i)<<2)) -#define NPE_MAC_UNI_ADDR(i) (NPE_MAC_UNI_ADDR_1 + ((i)<<2)) - -/* - * Bit definitions - */ - -/* TX Control Register 1*/ -#define NPE_TX_CNTRL1_TX_EN 0x01 /* enable TX engine */ -#define NPE_TX_CNTRL1_DUPLEX 0x02 /* select half duplex */ -#define NPE_TX_CNTRL1_RETRY 0x04 /* auto-retry on collision */ -#define NPE_TX_CNTRL1_PAD_EN 0x08 /* pad frames <64 bytes */ -#define NPE_TX_CNTRL1_FCS_EN 0x10 /* append FCS */ -#define NPE_TX_CNTRL1_2DEFER 0x20 /* select 2-part deferral */ -#define NPE_TX_CNTRL1_RMII 0x40 - -/* TX Control Register 2 */ -#define NPE_TX_CNTRL2_RETRIES_MASK 0xf /* max retry count */ - -/* RX Control Register 1 */ -#define NPE_RX_CNTRL1_RX_EN 0x01 /* enable RX engine */ -#define NPE_RX_CNTRL1_PADSTRIP_EN 0x02 /* strip frame padding */ -#define NPE_RX_CNTRL1_CRC_EN 0x04 /* include CRC in RX frame */ -#define NPE_RX_CNTRL1_PAUSE_EN 0x08 /* detect Pause frames */ -#define NPE_RX_CNTRL1_LOOP_EN 0x10 /* loopback tx/rx */ -#define NPE_RX_CNTRL1_ADDR_FLTR_EN 0x20 /* enable address filtering */ -#define NPE_RX_CNTRL1_RX_RUNT_EN 0x40 /* enable RX of runt frames */ -#define NPE_RX_CNTRL1_BCAST_DIS 0x80 /* discard broadcast frames */ - -/* RX Control Register 2 */ -#define NPE_RX_CNTRL2_DEFER_EN 0x01 - -/* Core Control Register */ -#define NPE_CORE_RESET 0x01 /* MAC reset state */ -#define NPE_CORE_RX_FIFO_FLUSH 0x02 /* flush RX FIFO */ -#define NPE_CORE_TX_FIFO_FLUSH 0x04 /* flush TX FIFO */ -#define NPE_CORE_SEND_JAM 0x08 /* send JAM on packet RX */ -#define NPE_CORE_MDC_EN 0x10 /* IXP42X drives MDC clock */ - -/* - * Stat block returned by NPE with NPE_GETSTATS msg. - */ -struct npestats { - uint32_t dot3StatsAlignmentErrors; - uint32_t dot3StatsFCSErrors; - uint32_t dot3StatsInternalMacReceiveErrors; - uint32_t RxOverrunDiscards; - uint32_t RxLearnedEntryDiscards; - uint32_t RxLargeFramesDiscards; - uint32_t RxSTPBlockedDiscards; - uint32_t RxVLANTypeFilterDiscards; - uint32_t RxVLANIdFilterDiscards; - uint32_t RxInvalidSourceDiscards; - uint32_t RxBlackListDiscards; - uint32_t RxWhiteListDiscards; - uint32_t RxUnderflowEntryDiscards; - uint32_t dot3StatsSingleCollisionFrames; - uint32_t dot3StatsMultipleCollisionFrames; - uint32_t dot3StatsDeferredTransmissions; - uint32_t dot3StatsLateCollisions; - uint32_t dot3StatsExcessiveCollisions; - uint32_t dot3StatsInternalMacTransmitErrors; - uint32_t dot3StatsCarrierSenseErrors; - uint32_t TxLargeFrameDiscards; - uint32_t TxVLANIdFilterDiscards; -}; - -/* - * Default values - */ -#define NPE_MAC_INT_CLK_THRESH_DEFAULT 0x1 - -#define NPE_MAC_RESET_DELAY 1 - -/* This value applies to RMII */ -#define NPE_MAC_SLOT_TIME_RMII_DEFAULT 0xFF - -/* - * MII definitions - these have been verified against the LXT971 and LXT972 PHYs - */ -#define NPE_MII_REG_SHL 16 -#define NPE_MII_ADDR_SHL 21 - -/* NB: shorthands for mii bus mdio routines */ -#define NPE_MAC_MDIO_CMD NPE_MAC_MDIO_CMD_1 -#define NPE_MAC_MDIO_STS NPE_MAC_MDIO_STS_1 - -#define NPE_MII_GO (1<<31) -#define NPE_MII_WRITE (1<<26) -#define NPE_MII_TIMEOUT_10TH_SECS 5 -#define NPE_MII_10TH_SEC_IN_MILLIS 100 -#define NPE_MII_READ_FAIL (1<<31) - -#define NPE_MII_PHY_DEF_DELAY 300 /* max delay before link up, etc. */ -#define NPE_MII_PHY_NO_DELAY 0x0 /* do not delay */ -#define NPE_MII_PHY_NULL 0xff /* PHY is not present */ -#define NPE_MII_PHY_DEF_ADDR 0x0 /* default PHY's logical address */ - -/* Register definition */ -#define NPE_MII_CTRL_REG 0x0 /* Control Register */ -#define NPE_MII_STAT_REG 0x1 /* Status Register */ -#define NPE_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */ -#define NPE_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */ -#define NPE_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */ - /* Advertisement Register */ -#define NPE_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */ - /* partner ability Register */ -#define NPE_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */ - /* Expansion Register */ -#define NPE_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */ - /* next-page transmit Register */ -#endif /* ARM_XSCALE_IF_NPEREG_H */ diff --git a/sys/arm/xscale/ixp425/ixdp425_pci.c b/sys/arm/xscale/ixp425/ixdp425_pci.c deleted file mode 100644 index 14b91784ce74..000000000000 --- a/sys/arm/xscale/ixp425/ixdp425_pci.c +++ /dev/null @@ -1,169 +0,0 @@ -/* $NetBSD: ixdp425_pci.c,v 1.6 2009/10/21 14:15:51 rmind Exp $ */ -/*- - * SPDX-License-Identifier: BSD-2-Clause-NetBSD - * - * Copyright (c) 2003 - * Ichiro FUKUHARA . - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#define _ARM32_BUS_DMA_PRIVATE -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include - -#include -#include -#include -#include - -void -ixp425_md_attach(device_t dev) -{ - struct ixp425_softc *sc = device_get_softc(device_get_parent(dev)); - struct ixppcib_softc *pci_sc = device_get_softc(dev); - uint32_t reg; - - - /* PCI Reset Assert */ - reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR); - reg &= ~(1U << GPIO_PCI_RESET); - GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg); - - /* PCI Clock Disable */ - reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR); - reg &= ~GPCLKR_MUX14; - GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg); - - /* - * set GPIO Direction - * Output: PCI_CLK, PCI_RESET - * Input: PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD - */ - reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER); - reg &= ~(1U << GPIO_PCI_CLK); - reg &= ~(1U << GPIO_PCI_RESET); - reg |= ((1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) | - (1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD)); - GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, reg); - - /* - * Set GPIO interrupt type - * PCI_INT_A, PCI_INTB, PCI_INT_C, PCI_INT_D: Active Low - */ - reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA)); - reg &= ~GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_MASK); - reg |= GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_ACT_LOW); - GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA), reg); - - reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB)); - reg &= ~GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_MASK); - reg |= GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_ACT_LOW); - GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB), reg); - - reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC)); - reg &= ~GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_MASK); - reg |= GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_ACT_LOW); - GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC), reg); - - reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTD)); - reg &= ~GPIO_TYPE(GPIO_PCI_INTD, GPIO_TYPE_MASK); - reg |= GPIO_TYPE(GPIO_PCI_INTD, GPIO_TYPE_ACT_LOW); - GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTD), reg); - - /* clear ISR */ - GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR, - (1U << GPIO_PCI_INTA) | (1U << GPIO_PCI_INTB) | - (1U << GPIO_PCI_INTC) | (1U << GPIO_PCI_INTD)); - - /* wait 1ms to satisfy "minimum reset assertion time" of the PCI spec */ - DELAY(1000); - reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR); - GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg | - (0xf << GPCLKR_CLK0DC_SHIFT) | (0xf << GPCLKR_CLK0TC_SHIFT)); - - /* PCI Clock Enable */ - reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR); - reg |= GPCLKR_MUX14; - GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg | GPCLKR_MUX14); - - /* - * wait 100us to satisfy "minimum reset assertion time from clock stable - * requirement of the PCI spec - */ - DELAY(100); - /* PCI Reset deassert */ - reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR); - reg |= 1U << GPIO_PCI_RESET; - GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg | (1U << GPIO_PCI_RESET)); - pci_sc->sc_irq_rman.rm_type = RMAN_ARRAY; - pci_sc->sc_irq_rman.rm_descr = "IXP425 PCI IRQs"; - CTASSERT(PCI_INT_D < PCI_INT_A); - /* XXX this overlaps the irq's setup in ixp425_attach */ - if (rman_init(&pci_sc->sc_irq_rman) != 0 || - rman_manage_region(&pci_sc->sc_irq_rman, PCI_INT_D, PCI_INT_A) != 0) - panic("ixp425_md_attach: failed to set up IRQ rman"); -} - -#define IXP425_MAX_DEV 5 -#define IXP425_MAX_LINE 4 - -int -ixp425_md_route_interrupt(device_t bridge, device_t device, int pin) -{ - static int ixp425_pci_table[IXP425_MAX_DEV][IXP425_MAX_LINE] = { - {PCI_INT_A, PCI_INT_B, PCI_INT_C, PCI_INT_D}, - {PCI_INT_B, PCI_INT_C, PCI_INT_D, PCI_INT_A}, - {PCI_INT_C, PCI_INT_D, PCI_INT_A, PCI_INT_B}, - {PCI_INT_D, PCI_INT_A, PCI_INT_B, PCI_INT_C}, - /* NB: for optional USB controller on Gateworks Avila */ - {PCI_INT_A, PCI_INT_B, PCI_INT_C, PCI_INT_D}, - }; - int dev; - - dev = pci_get_slot(device); - if (bootverbose) - device_printf(bridge, "routing pin %d for %s\n", pin, - device_get_nameunit(device)); - if (pin >= 1 && pin <= IXP425_MAX_LINE && - dev >= 1 && dev <= IXP425_MAX_DEV) { - return (ixp425_pci_table[dev - 1][pin - 1]); - } else - printf("ixppcib: no mapping for %d/%d/%d\n", - pci_get_bus(device), dev, pci_get_function(device)); - - return (-1); -} diff --git a/sys/arm/xscale/ixp425/ixdp425reg.h b/sys/arm/xscale/ixp425/ixdp425reg.h deleted file mode 100644 index a27066238fa4..000000000000 --- a/sys/arm/xscale/ixp425/ixdp425reg.h +++ /dev/null @@ -1,50 +0,0 @@ -/* $NetBSD: ixdp425reg.h,v 1.7 2009/10/21 14:15:51 rmind Exp $ */ -/*- - * SPDX-License-Identifier: BSD-2-Clause-NetBSD - * - * Copyright (c) 2003 - * Ichiro FUKUHARA . - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* $FreeBSD$ */ -#ifndef _IXDP425REG_H_ -#define _IXDP425REG_H_ -/* GPIOs */ -#define GPIO_PCI_CLK 14 -#define GPIO_PCI_RESET 13 -#define GPIO_PCI_INTA 11 -#define GPIO_PCI_INTB 10 -#define GPIO_PCI_INTC 9 -#define GPIO_PCI_INTD 8 -#define GPIO_I2C_SDA 7 -#define GPIO_I2C_SDA_BIT (1U << GPIO_I2C_SDA) -#define GPIO_I2C_SCL 6 -#define GPIO_I2C_SCL_BIT (1U << GPIO_I2C_SCL) -/* Interrupt */ -#define PCI_INT_A IXP425_INT_GPIO_11 -#define PCI_INT_B IXP425_INT_GPIO_10 -#define PCI_INT_C IXP425_INT_GPIO_9 -#define PCI_INT_D IXP425_INT_GPIO_8 -#endif /* _IXDP425REG_H_ */ diff --git a/sys/arm/xscale/ixp425/ixp425.c b/sys/arm/xscale/ixp425/ixp425.c deleted file mode 100644 index 8b7110a7063c..000000000000 --- a/sys/arm/xscale/ixp425/ixp425.c +++ /dev/null @@ -1,692 +0,0 @@ -/* $NetBSD: ixp425.c,v 1.13 2009/10/21 14:15:50 rmind Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-2-Clause-NetBSD - * - * Copyright (c) 2003 - * Ichiro FUKUHARA . - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include "opt_ddb.h" - -#define _ARM32_BUS_DMA_PRIVATE -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -volatile uint32_t intr_enabled; -uint32_t intr_steer = 0; - -/* ixp43x et. al have +32 IRQ's */ -volatile uint32_t intr_enabled2; -uint32_t intr_steer2 = 0; - -struct ixp425_softc *ixp425_softc = NULL; - -struct mtx ixp425_gpio_mtx; - -static int ixp425_probe(device_t); -static void ixp425_identify(driver_t *, device_t); -static int ixp425_attach(device_t); - -/* - * Return a mask of the "fuse" bits that identify - * which h/w features are present. - * NB: assumes the expansion bus is mapped. - */ -uint32_t -ixp4xx_read_feature_bits(void) -{ - uint32_t bits = ~IXPREG(IXP425_EXP_VBASE + EXP_FCTRL_OFFSET); - bits &= ~EXP_FCTRL_RESVD; - if (!cpu_is_ixp46x()) - bits &= ~EXP_FCTRL_IXP46X_ONLY; - return bits; -} - -void -ixp4xx_write_feature_bits(uint32_t v) -{ - IXPREG(IXP425_EXP_VBASE + EXP_FCTRL_OFFSET) = ~v; -} - -struct arm32_dma_range * -bus_dma_get_range(void) -{ - return (NULL); -} - -int -bus_dma_get_range_nb(void) -{ - return (0); -} - -static const uint8_t int2gpio[32] __attribute__ ((aligned(32))) = { - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#0 -> INT#5 */ - 0x00, 0x01, /* GPIO#0 -> GPIO#1 */ - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#8 -> INT#13 */ - 0xff, 0xff, 0xff, 0xff, 0xff, /* INT#14 -> INT#18 */ - 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* GPIO#2 -> GPIO#7 */ - 0x08, 0x09, 0x0a, 0x0b, 0x0c, /* GPIO#8 -> GPIO#12 */ - 0xff, 0xff /* INT#30 -> INT#31 */ -}; - -static __inline uint32_t -ixp425_irq2gpio_bit(int irq) -{ - return (1U << int2gpio[irq]); -} - -#ifdef DDB -#include - -DB_SHOW_COMMAND(gpio, db_show_gpio) -{ - static const char *itype[8] = { - [GPIO_TYPE_ACT_HIGH] = "act-high", - [GPIO_TYPE_ACT_LOW] = "act-low", - [GPIO_TYPE_EDG_RISING] = "edge-rising", - [GPIO_TYPE_EDG_FALLING] = "edge-falling", - [GPIO_TYPE_TRANSITIONAL]= "transitional", - [5] = "type-5", [6] = "type-6", [7] = "type-7" - }; - uint32_t gpoutr = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOUTR); - uint32_t gpoer = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPOER); - uint32_t gpinr = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPINR); - uint32_t gpit1r = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPIT1R); - uint32_t gpit2r = GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPIT2R); - int i, j; - - db_printf("GPOUTR %08x GPINR %08x GPOER %08x GPISR %08x\n", - gpoutr, gpinr, gpoer, - GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPISR)); - db_printf("GPIT1R %08x GPIT2R %08x GPCLKR %08x\n", - gpit1r, gpit2r, GPIO_CONF_READ_4(ixp425_softc, IXP425_GPIO_GPCLKR)); - for (i = 0; i < 16; i++) { - db_printf("[%2d] out %u in %u %-3s", i, - (gpoutr>>i)&1, (gpinr>>i)&1, (gpoer>>i)&1 ? "in" : "out"); - for (j = 0; j < 32; j++) - if (int2gpio[j] == i) { - db_printf(" irq %2u %s", j, itype[ - (((i & 8) ? gpit2r : gpit1r) >> (3*(i&7))) - & 7]); - break; - } - db_printf("\n"); - } -} -#endif - -void -ixp425_set_gpio(struct ixp425_softc *sc, int pin, int type) -{ - uint32_t gpiotr = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(pin)); - - IXP4XX_GPIO_LOCK(); - /* clear interrupt type */ - GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(pin), - gpiotr &~ GPIO_TYPE(pin, GPIO_TYPE_MASK)); - /* clear any pending interrupt */ - GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR, (1<> last; - for (; mask != 0; mask >>= 1, last++) { - if (mask & 1) - return last; - } - last = 32; - } - if (cpu_is_ixp43x()) { - mask = ixp435_irq_read() >> (32-last); - for (; mask != 0; mask >>= 1, last++) { - if (mask & 1) - return last; - } - } - return -1; -} - -void -cpu_reset(void) -{ - - bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, - IXP425_OST_WDOG_KEY, OST_WDOG_KEY_MAJICK); - bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, - IXP425_OST_WDOG, 0); - bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, - IXP425_OST_WDOG_ENAB, OST_WDOG_ENAB_RST_ENA | - OST_WDOG_ENAB_CNT_ENA); - printf("Reset failed!\n"); - for(;;); -} - -static void -ixp425_identify(driver_t *driver, device_t parent) -{ - BUS_ADD_CHILD(parent, 0, "ixp", 0); -} - -static int -ixp425_probe(device_t dev) -{ - device_set_desc(dev, "Intel IXP4XX"); - return (0); -} - -static int -ixp425_attach(device_t dev) -{ - struct ixp425_softc *sc; - - device_printf(dev, "%b\n", ixp4xx_read_feature_bits(), EXP_FCTRL_BITS); - - sc = device_get_softc(dev); - sc->sc_iot = &ixp425_bs_tag; - KASSERT(ixp425_softc == NULL, ("%s called twice?", __func__)); - ixp425_softc = sc; - - intr_enabled = 0; - ixp425_set_intrmask(); - ixp425_set_intrsteer(); - if (cpu_is_ixp43x()) { - intr_enabled2 = 0; - ixp435_set_intrmask(); - ixp435_set_intrsteer(); - } - arm_post_filter = ixp425_post_filter; - - mtx_init(&ixp425_gpio_mtx, "gpio", NULL, MTX_DEF); - if (bus_space_map(sc->sc_iot, IXP425_GPIO_HWBASE, IXP425_GPIO_SIZE, - 0, &sc->sc_gpio_ioh)) - panic("%s: unable to map GPIO registers", __func__); - if (bus_space_map(sc->sc_iot, IXP425_EXP_HWBASE, IXP425_EXP_SIZE, - 0, &sc->sc_exp_ioh)) - panic("%s: unable to map Expansion Bus registers", __func__); - - /* XXX belongs in platform init */ - if (cpu_is_ixp43x()) - cambria_exp_bus_init(sc); - - if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT, - BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0, - NULL, NULL, &sc->sc_dmat)) - panic("%s: failed to create dma tag", __func__); - - sc->sc_irq_rman.rm_type = RMAN_ARRAY; - sc->sc_irq_rman.rm_descr = "IXP4XX IRQs"; - if (rman_init(&sc->sc_irq_rman) != 0 || - rman_manage_region(&sc->sc_irq_rman, 0, cpu_is_ixp43x() ? 63 : 31) != 0) - panic("%s: failed to set up IRQ rman", __func__); - - sc->sc_mem_rman.rm_type = RMAN_ARRAY; - sc->sc_mem_rman.rm_descr = "IXP4XX Memory"; - if (rman_init(&sc->sc_mem_rman) != 0 || - rman_manage_region(&sc->sc_mem_rman, 0, ~0) != 0) - panic("%s: failed to set up memory rman", __func__); - - BUS_ADD_CHILD(dev, 0, "pcib", 0); - BUS_ADD_CHILD(dev, 0, "ixpclk", 0); - BUS_ADD_CHILD(dev, 0, "ixpiic", 0); - /* XXX move to hints? */ - BUS_ADD_CHILD(dev, 0, "ixpwdog", 0); - - /* attach wired devices via hints */ - bus_enumerate_hinted_children(dev); - - bus_generic_probe(dev); - bus_generic_attach(dev); - - return (0); -} - -static void -ixp425_hinted_child(device_t bus, const char *dname, int dunit) -{ - device_t child; - struct ixp425_ivar *ivar; - - child = BUS_ADD_CHILD(bus, 0, dname, dunit); - ivar = IXP425_IVAR(child); - resource_int_value(dname, dunit, "addr", &ivar->addr); - resource_int_value(dname, dunit, "irq", &ivar->irq); -} - -static device_t -ixp425_add_child(device_t dev, u_int order, const char *name, int unit) -{ - device_t child; - struct ixp425_ivar *ivar; - - child = device_add_child_ordered(dev, order, name, unit); - if (child == NULL) - return NULL; - ivar = malloc(sizeof(struct ixp425_ivar), M_DEVBUF, M_NOWAIT); - if (ivar == NULL) { - device_delete_child(dev, child); - return NULL; - } - ivar->addr = 0; - ivar->irq = -1; - device_set_ivars(child, ivar); - return child; -} - -static int -ixp425_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) -{ - struct ixp425_ivar *ivar = IXP425_IVAR(child); - - switch (which) { - case IXP425_IVAR_ADDR: - if (ivar->addr != 0) { - *(uint32_t *)result = ivar->addr; - return 0; - } - break; - case IXP425_IVAR_IRQ: - if (ivar->irq != -1) { - *(int *)result = ivar->irq; - return 0; - } - break; - } - return EINVAL; -} - -/* - * NB: This table handles P->V translations for regions setup with - * static mappings in initarm. This is used solely for calls to - * bus_alloc_resource_any; anything done with bus_space_map is - * handled elsewhere and does not require an entry here. - * - * XXX this table is also used by uart_cpu_getdev via getvbase - * (hence the public api) - */ -struct hwvtrans { - uint32_t hwbase; - uint32_t size; - uint32_t vbase; - int isa4x; /* XXX needs special bus space tag */ - int isslow; /* XXX needs special bus space tag */ -}; - -static const struct hwvtrans * -gethwvtrans(uint32_t hwbase, uint32_t size) -{ - static const struct hwvtrans hwvtrans[] = { - /* NB: needed only for uart_cpu_getdev */ - { .hwbase = IXP425_UART0_HWBASE, - .size = IXP425_REG_SIZE, - .vbase = IXP425_UART0_VBASE, - .isa4x = 1 }, - { .hwbase = IXP425_UART1_HWBASE, - .size = IXP425_REG_SIZE, - .vbase = IXP425_UART1_VBASE, - .isa4x = 1 }, - { .hwbase = IXP425_PCI_HWBASE, - .size = IXP425_PCI_SIZE, - .vbase = IXP425_PCI_VBASE }, - { .hwbase = IXP425_PCI_MEM_HWBASE, - .size = IXP425_PCI_MEM_SIZE, - .vbase = IXP425_PCI_MEM_VBASE }, - { .hwbase = IXP425_EXP_BUS_CS0_HWBASE, - .size = IXP425_EXP_BUS_CS0_SIZE, - .vbase = IXP425_EXP_BUS_CS0_VBASE }, - /* NB: needed for ixp435 ehci controllers */ - { .hwbase = IXP435_USB1_HWBASE, - .size = IXP435_USB1_SIZE, - .vbase = IXP435_USB1_VBASE }, - { .hwbase = IXP435_USB2_HWBASE, - .size = IXP435_USB2_SIZE, - .vbase = IXP435_USB2_VBASE }, - { .hwbase = CAMBRIA_GPS_HWBASE, - .size = CAMBRIA_GPS_SIZE, - .vbase = CAMBRIA_GPS_VBASE, - .isslow = 1 }, - { .hwbase = CAMBRIA_RS485_HWBASE, - .size = CAMBRIA_RS485_SIZE, - .vbase = CAMBRIA_RS485_VBASE, - .isslow = 1 }, - }; - int i; - - for (i = 0; i < nitems(hwvtrans); i++) { - if (hwbase >= hwvtrans[i].hwbase && - hwbase + size <= hwvtrans[i].hwbase + hwvtrans[i].size) - return &hwvtrans[i]; - } - return NULL; -} - -/* XXX for uart_cpu_getdev */ -int -getvbase(uint32_t hwbase, uint32_t size, uint32_t *vbase) -{ - const struct hwvtrans *hw; - - hw = gethwvtrans(hwbase, size); - if (hw == NULL) - return (ENOENT); - *vbase = hwbase - hw->hwbase + hw->vbase; - return (0); -} - -static struct resource * -ixp425_alloc_resource(device_t dev, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ - struct ixp425_softc *sc = device_get_softc(dev); - const struct hwvtrans *vtrans; - struct resource *rv; - uint32_t addr; - int needactivate = flags & RF_ACTIVE; - int irq; - - flags &= ~RF_ACTIVE; - switch (type) { - case SYS_RES_IRQ: - /* override per hints */ - if (BUS_READ_IVAR(dev, child, IXP425_IVAR_IRQ, &irq) == 0) - start = end = irq; - rv = rman_reserve_resource(&sc->sc_irq_rman, start, end, count, - flags, child); - if (rv != NULL) - rman_set_rid(rv, *rid); - break; - - case SYS_RES_MEMORY: - /* override per hints */ - if (BUS_READ_IVAR(dev, child, IXP425_IVAR_ADDR, &addr) == 0) { - start = addr; - /* XXX use nominal window to check for mapping */ - vtrans = gethwvtrans(start, 0x1000); - if (vtrans != NULL) { - /* - * Assign the entire mapped region; this may - * not be correct but without more info from - * the caller we cannot tell. - */ - end = start + vtrans->size - - (start - vtrans->hwbase); - if (bootverbose) - device_printf(child, - "%s: assign 0x%jx:0x%jx%s\n", - __func__, start, end - start, - vtrans->isa4x ? " A4X" : - vtrans->isslow ? " SLOW" : ""); - } - } else - vtrans = gethwvtrans(start, end - start); - if (vtrans == NULL) { - /* likely means above table needs to be updated */ - device_printf(child, "%s: no mapping for 0x%jx:0x%jx\n", - __func__, start, end - start); - return NULL; - } - rv = rman_reserve_resource(&sc->sc_mem_rman, start, end, - end - start, flags, child); - if (rv == NULL) { - device_printf(child, "%s: cannot reserve 0x%jx:0x%jx\n", - __func__, start, end - start); - return NULL; - } - rman_set_rid(rv, *rid); - break; - default: - rv = NULL; - break; - } - if (rv != NULL && needactivate) { - if (bus_activate_resource(child, type, *rid, rv)) { - rman_release_resource(rv); - return (NULL); - } - } - return (rv); -} - -static int -ixp425_release_resource(device_t bus, device_t child, int type, int rid, - struct resource *r) -{ - /* NB: no private resources, just release */ - return rman_release_resource(r); -} - -static int -ixp425_activate_resource(device_t dev, device_t child, int type, int rid, - struct resource *r) -{ - struct ixp425_softc *sc = device_get_softc(dev); - const struct hwvtrans *vtrans; - - if (type == SYS_RES_MEMORY) { - vtrans = gethwvtrans(rman_get_start(r), rman_get_size(r)); - if (vtrans == NULL) { /* NB: should not happen */ - device_printf(child, "%s: no mapping for 0x%jx:0x%jx\n", - __func__, rman_get_start(r), rman_get_size(r)); - return (ENOENT); - } - if (vtrans->isa4x) - rman_set_bustag(r, &ixp425_a4x_bs_tag); - else if (vtrans->isslow) - rman_set_bustag(r, &cambria_exp_bs_tag); - else - rman_set_bustag(r, sc->sc_iot); - rman_set_bushandle(r, vtrans->vbase); - } - return (rman_activate_resource(r)); -} - -static int -ixp425_deactivate_resource(device_t bus, device_t child, int type, int rid, - struct resource *r) -{ - /* NB: no private resources, just deactive */ - return (rman_deactivate_resource(r)); -} - -static __inline void -get_masks(struct resource *res, uint32_t *mask, uint32_t *mask2) -{ - int i; - - *mask = 0; - for (i = rman_get_start(res); i < 32 && i <= rman_get_end(res); i++) - *mask |= 1 << i; - *mask2 = 0; - for (; i <= rman_get_end(res); i++) - *mask2 |= 1 << (i - 32); -} - -static __inline void -update_masks(uint32_t mask, uint32_t mask2) -{ - - intr_enabled = mask; - ixp425_set_intrmask(); - if (cpu_is_ixp43x()) { - intr_enabled2 = mask2; - ixp435_set_intrmask(); - } -} - -static int -ixp425_setup_intr(device_t dev, device_t child, - struct resource *res, int flags, driver_filter_t *filt, - driver_intr_t *intr, void *arg, void **cookiep) -{ - uint32_t mask, mask2; - int error; - - error = BUS_SETUP_INTR(device_get_parent(dev), child, res, flags, - filt, intr, arg, cookiep); - if (error) - return (error); - - get_masks(res, &mask, &mask2); - update_masks(intr_enabled | mask, intr_enabled2 | mask2); - - return (0); -} - -static int -ixp425_teardown_intr(device_t dev, device_t child, struct resource *res, - void *cookie) -{ - uint32_t mask, mask2; - - get_masks(res, &mask, &mask2); - update_masks(intr_enabled &~ mask, intr_enabled2 &~ mask2); - - return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie)); -} - -static device_method_t ixp425_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, ixp425_probe), - DEVMETHOD(device_attach, ixp425_attach), - DEVMETHOD(device_identify, ixp425_identify), - - /* Bus interface */ - DEVMETHOD(bus_add_child, ixp425_add_child), - DEVMETHOD(bus_hinted_child, ixp425_hinted_child), - DEVMETHOD(bus_read_ivar, ixp425_read_ivar), - - DEVMETHOD(bus_alloc_resource, ixp425_alloc_resource), - DEVMETHOD(bus_release_resource, ixp425_release_resource), - DEVMETHOD(bus_activate_resource, ixp425_activate_resource), - DEVMETHOD(bus_deactivate_resource, ixp425_deactivate_resource), - DEVMETHOD(bus_setup_intr, ixp425_setup_intr), - DEVMETHOD(bus_teardown_intr, ixp425_teardown_intr), - - {0, 0}, -}; - -static driver_t ixp425_driver = { - "ixp", - ixp425_methods, - sizeof(struct ixp425_softc), -}; -static devclass_t ixp425_devclass; - -DRIVER_MODULE(ixp, nexus, ixp425_driver, ixp425_devclass, 0, 0); diff --git a/sys/arm/xscale/ixp425/ixp425_a4x_io.S b/sys/arm/xscale/ixp425/ixp425_a4x_io.S deleted file mode 100644 index bccd19bc2e91..000000000000 --- a/sys/arm/xscale/ixp425/ixp425_a4x_io.S +++ /dev/null @@ -1,152 +0,0 @@ -/* $NetBSD: ixp425_a4x_io.S,v 1.2 2005/12/11 12:16:51 christos Exp $ */ - -/* - * Copyright 2003 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Steve C. Woodford for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * There are simple bus space functions for IO registers mapped at - * 32-bit aligned positions. offset is multiplied by 4. - * - * Based loosely on pxa2x0_a2x_io.S - */ - -#include -__FBSDID("$FreeBSD$"); - -/* - * bus_space I/O functions with offset*4 - */ - -/* - * Read single - */ -ENTRY(a4x_bs_r_1) - ldr r0, [r1, r2, LSL #2] - and r0, r0, #0xff - mov pc, lr -END(a4x_bs_r_1) - -ENTRY(a4x_bs_r_2) - ldr r0, [r1, r2, LSL #2] - mov r1, #0xff - orr r1, r1, r1, lsl #8 - and r0, r0, r1 - mov pc, lr -END(a4x_bs_r_2) - -ENTRY(a4x_bs_r_4) - ldr r0, [r1, r2, LSL #2] - mov pc, lr -END(a4x_bs_r_4) - -/* - * Write single - */ -ENTRY(a4x_bs_w_1) - and r3, r3, #0xff - str r3, [r1, r2, LSL #2] - mov pc, lr -END(a4x_bs_w_1) - -ENTRY(a4x_bs_w_2) - mov r0, #0xff - orr r0, r0, r0, lsl #8 - and r3, r3, r0 - str r3, [r1, r2, LSL #2] - mov pc, lr -END(a4x_bs_w_2) - -ENTRY(a4x_bs_w_4) - str r3, [r1, r2, LSL #2] - mov pc, lr -END(a4x_bs_w_4) - -/* - * Read multiple - */ -ENTRY(a4x_bs_rm_1) - add r0, r1, r2, lsl #2 - ldr r2, [sp, #0] - mov r1, r3 - teq r2, #0 - moveq pc, lr -1: ldr r3, [r0] - subs r2, r2, #1 - strb r3, [r1], #1 - bne 1b - mov pc, lr -END(a4x_bs_rm_1) - -ENTRY(a4x_bs_rm_2) - add r0, r1, r2, lsl #2 - ldr r2, [sp, #0] - mov r1, r3 - teq r2, #0 - moveq pc, lr -1: ldr r3, [r0] - subs r2, r2, #1 - strh r3, [r1], #2 - bne 1b - mov pc, lr -END(a4x_bs_rm_2) - -/* - * Write multiple - */ -ENTRY(a4x_bs_wm_1) - add r0, r1, r2, lsl #2 - ldr r2, [sp, #0] - mov r1, r3 - teq r2, #0 - moveq pc, lr -1: ldrb r3, [r1], #1 - subs r2, r2, #1 - str r3, [r0] - bne 1b - mov pc, lr -END(a4x_bs_wm_1) - -ENTRY(a4x_bs_wm_2) - add r0, r1, r2, lsl #2 - ldr r2, [sp, #0] - mov r1, r3 - teq r2, #0 - moveq pc, lr -1: ldrh r3, [r1], #2 - subs r2, r2, #1 - str r3, [r0] - bne 1b - mov pc, lr -END(a4x_bs_wm_2) diff --git a/sys/arm/xscale/ixp425/ixp425_a4x_space.c b/sys/arm/xscale/ixp425/ixp425_a4x_space.c deleted file mode 100644 index ae4abab49206..000000000000 --- a/sys/arm/xscale/ixp425/ixp425_a4x_space.c +++ /dev/null @@ -1,116 +0,0 @@ -/* $NetBSD: ixp425_a4x_space.c,v 1.2 2005/12/11 12:16:51 christos Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright 2003 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Steve C. Woodford for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * Bus space tag for 8/16-bit devices on 32-bit bus. - * all registers are located at the address of multiple of 4. - * - * Based on pxa2x0_a4x_space.c - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include - -#include - -#include -#include -#include -#include -#include - -#include - -/* Prototypes for all the bus_space structure functions */ -bs_protos(a4x); -bs_protos(generic); - -struct bus_space ixp425_a4x_bs_tag = { - /* cookie */ - .bs_privdata = (void *) 0, - - /* mapping/unmapping */ - .bs_map = generic_bs_map, - .bs_unmap = generic_bs_unmap, - .bs_subregion = generic_bs_subregion, - - /* allocation/deallocation */ - .bs_alloc = generic_bs_alloc, /* XXX not implemented */ - .bs_free = generic_bs_free, /* XXX not implemented */ - - /* barrier */ - .bs_barrier = generic_bs_barrier, - - /* read (single) */ - .bs_r_1 = a4x_bs_r_1, - .bs_r_2 = a4x_bs_r_2, - .bs_r_4 = a4x_bs_r_4, - - /* read multiple */ - .bs_rm_1 = a4x_bs_rm_1, - .bs_rm_2 = a4x_bs_rm_2, - - /* read region */ - /* XXX not implemented */ - - /* write (single) */ - .bs_w_1 = a4x_bs_w_1, - .bs_w_2 = a4x_bs_w_2, - .bs_w_4 = a4x_bs_w_4, - - /* write multiple */ - .bs_wm_1 = a4x_bs_wm_1, - .bs_wm_2 = a4x_bs_wm_2, - - /* write region */ - /* XXX not implemented */ - - /* set multiple */ - /* XXX not implemented */ - - /* set region */ - /* XXX not implemented */ - - /* copy */ - /* XXX not implemented */ -}; diff --git a/sys/arm/xscale/ixp425/ixp425_iic.c b/sys/arm/xscale/ixp425/ixp425_iic.c deleted file mode 100644 index 0ffaace2cc35..000000000000 --- a/sys/arm/xscale/ixp425/ixp425_iic.c +++ /dev/null @@ -1,197 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 Kevin Lo. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include "iicbb_if.h" - -#define I2C_DELAY 10 - -/* bit clr/set shorthands */ -#define GPIO_CONF_CLR(sc, reg, mask) \ - GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, reg) &~ (mask)) -#define GPIO_CONF_SET(sc, reg, mask) \ - GPIO_CONF_WRITE_4(sc, reg, GPIO_CONF_READ_4(sc, reg) | (mask)) - -struct ixpiic_softc { - device_t sc_dev; - bus_space_tag_t sc_iot; - bus_space_handle_t sc_gpio_ioh; - - device_t iicbb; -}; - -static struct ixpiic_softc *ixpiic_sc = NULL; - -static int -ixpiic_probe(device_t dev) -{ - device_set_desc(dev, "IXP4XX GPIO-Based I2C Interface"); - return (0); -} - -static int -ixpiic_attach(device_t dev) -{ - struct ixpiic_softc *sc = device_get_softc(dev); - struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); - - ixpiic_sc = sc; - - sc->sc_dev = dev; - sc->sc_iot = sa->sc_iot; - sc->sc_gpio_ioh = sa->sc_gpio_ioh; - - GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, - GPIO_I2C_SCL_BIT | GPIO_I2C_SDA_BIT); - GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, - GPIO_I2C_SCL_BIT | GPIO_I2C_SDA_BIT); - - /* add generic bit-banging code */ - if ((sc->iicbb = device_add_child(dev, "iicbb", -1)) == NULL) - device_printf(dev, "could not add iicbb\n"); - - /* probe and attach the bit-banging code */ - device_probe_and_attach(sc->iicbb); - - return (0); -} - -static int -ixpiic_callback(device_t dev, int index, caddr_t data) -{ - return (0); -} - -static int -ixpiic_getscl(device_t dev) -{ - struct ixpiic_softc *sc = ixpiic_sc; - uint32_t reg; - - IXP4XX_GPIO_LOCK(); - GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT); - - reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR); - IXP4XX_GPIO_UNLOCK(); - return (reg & GPIO_I2C_SCL_BIT); -} - -static int -ixpiic_getsda(device_t dev) -{ - struct ixpiic_softc *sc = ixpiic_sc; - uint32_t reg; - - IXP4XX_GPIO_LOCK(); - GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT); - - reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPINR); - IXP4XX_GPIO_UNLOCK(); - return (reg & GPIO_I2C_SDA_BIT); -} - -static void -ixpiic_setsda(device_t dev, int val) -{ - struct ixpiic_softc *sc = ixpiic_sc; - - IXP4XX_GPIO_LOCK(); - GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SDA_BIT); - if (val) - GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT); - else - GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SDA_BIT); - IXP4XX_GPIO_UNLOCK(); - DELAY(I2C_DELAY); -} - -static void -ixpiic_setscl(device_t dev, int val) -{ - struct ixpiic_softc *sc = ixpiic_sc; - - IXP4XX_GPIO_LOCK(); - GPIO_CONF_CLR(sc, IXP425_GPIO_GPOUTR, GPIO_I2C_SCL_BIT); - if (val) - GPIO_CONF_SET(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT); - else - GPIO_CONF_CLR(sc, IXP425_GPIO_GPOER, GPIO_I2C_SCL_BIT); - IXP4XX_GPIO_UNLOCK(); - DELAY(I2C_DELAY); -} - -static int -ixpiic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) -{ - /* reset bus */ - ixpiic_setsda(dev, 1); - ixpiic_setscl(dev, 1); - - return (IIC_ENOADDR); -} - -static device_method_t ixpiic_methods[] = { - /* device interface */ - DEVMETHOD(device_probe, ixpiic_probe), - DEVMETHOD(device_attach, ixpiic_attach), - - /* iicbb interface */ - DEVMETHOD(iicbb_callback, ixpiic_callback), - DEVMETHOD(iicbb_setsda, ixpiic_setsda), - DEVMETHOD(iicbb_setscl, ixpiic_setscl), - DEVMETHOD(iicbb_getsda, ixpiic_getsda), - DEVMETHOD(iicbb_getscl, ixpiic_getscl), - DEVMETHOD(iicbb_reset, ixpiic_reset), - - { 0, 0 } -}; - -static driver_t ixpiic_driver = { - "ixpiic", - ixpiic_methods, - sizeof(struct ixpiic_softc), -}; -static devclass_t ixpiic_devclass; - -DRIVER_MODULE(ixpiic, ixp, ixpiic_driver, ixpiic_devclass, 0, 0); -DRIVER_MODULE(iicbb, ixpiic, iicbb_driver, iicbb_devclass, 0, 0); diff --git a/sys/arm/xscale/ixp425/ixp425_intr.h b/sys/arm/xscale/ixp425/ixp425_intr.h deleted file mode 100644 index ae9bf1cf629c..000000000000 --- a/sys/arm/xscale/ixp425/ixp425_intr.h +++ /dev/null @@ -1,90 +0,0 @@ -/* $NetBSD: ixp425_intr.h,v 1.6 2005/12/24 20:06:52 perry Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 2001, 2002 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -#ifndef _IXP425_INTR_H_ -#define _IXP425_INTR_H_ - -#define ARM_IRQ_HANDLER _C_LABEL(ixp425_intr_dispatch) - -#ifndef _LOCORE - -#include - -#include - -#define IXPREG(reg) *((__volatile u_int32_t*) (reg)) - -void ixp425_do_pending(void); - -extern __volatile uint32_t intr_enabled; -extern uint32_t intr_steer; - -static __inline void __attribute__((__unused__)) -ixp425_set_intrmask(void) -{ - IXPREG(IXP425_INT_ENABLE) = intr_enabled & IXP425_INT_HWMASK; -} - -static __inline void -ixp425_set_intrsteer(void) -{ - IXPREG(IXP425_INT_SELECT) = intr_steer & IXP425_INT_HWMASK; -} - -extern __volatile uint32_t intr_enabled2; -extern uint32_t intr_steer2; - -static __inline void __attribute__((__unused__)) -ixp435_set_intrmask(void) -{ - IXPREG(IXP435_INT_ENABLE2) = intr_enabled2 & IXP435_INT_HWMASK; -} - -static __inline void -ixp435_set_intrsteer(void) -{ - IXPREG(IXP435_INT_SELECT2) = intr_steer2 & IXP435_INT_HWMASK; -} - -#endif /* _LOCORE */ - -#endif /* _IXP425_INTR_H_ */ diff --git a/sys/arm/xscale/ixp425/ixp425_mem.c b/sys/arm/xscale/ixp425/ixp425_mem.c deleted file mode 100644 index e4a616520082..000000000000 --- a/sys/arm/xscale/ixp425/ixp425_mem.c +++ /dev/null @@ -1,104 +0,0 @@ -/* $NetBSD: ixp425_mem.c,v 1.2 2005/12/11 12:16:51 christos Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-4-Clause - * - * Copyright (c) 2003 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Steve C. Woodford for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include - -#include -#include - -static uint32_t sdram_64bit[] = { - 0x00800000, /* 8M: One 2M x 32 chip */ - 0x01000000, /* 16M: Two 2M x 32 chips */ - 0x01000000, /* 16M: Two 4M x 16 chips */ - 0x02000000, /* 32M: Four 4M x 32 chips */ - 0, 0, 0, 0 -}; - -static uint32_t sdram_other[] = { - 0x02000000, /* 32M: Two 8M x 16 chips */ - 0x04000000, /* 64M: Four 8M x 16 chips */ - 0x04000000, /* 64M: Two 16M x 16 chips */ - 0x08000000, /* 128M: Four 16M x 16 chips */ - 0x08000000, /* 128M: Two 32M x 16 chips */ - 0x10000000, /* 256M: Four 32M x 16 chips */ - 0, 0 -}; - -uint32_t -ixp425_sdram_size(void) -{ -#define MCU_REG_READ(x) (*(volatile uint32_t *)(IXP425_MCU_VBASE + (x))) - uint32_t size, sdr_config; - - sdr_config = MCU_REG_READ(MCU_SDR_CONFIG); - - if (sdr_config & MCU_SDR_CONFIG_64MBIT) - size = sdram_64bit[MCU_SDR_CONFIG_MCONF(sdr_config)]; - else - size = sdram_other[MCU_SDR_CONFIG_MCONF(sdr_config)]; - - if (size == 0) { - printf("** SDR_CONFIG returns unknown value, using 32M\n"); - size = 32 * 1024 * 1024; - } - - return (size); -#undef MCU_REG_READ -} - -uint32_t -ixp435_ddram_size(void) -{ -#define MCU_REG_READ(x) (*(volatile uint32_t *)(IXP425_MCU_VBASE + (x))) - uint32_t sbr0; - - /* - * Table 198, page 516 shows DDR-I/II SDRAM bank sizes - * for SBR0 and SBR1. The manual states both banks must - * be programmed to be the same size. We just assume - * it's done right and calculate 2x for the memory size. - */ - sbr0 = MCU_REG_READ(MCU_DDR_SBR0); - return 2 * 16*(sbr0 & 0x7f) * 1024 * 1024; -#undef MCU_REG_READ -} diff --git a/sys/arm/xscale/ixp425/ixp425_npe.c b/sys/arm/xscale/ixp425/ixp425_npe.c deleted file mode 100644 index a699c6ad3f81..000000000000 --- a/sys/arm/xscale/ixp425/ixp425_npe.c +++ /dev/null @@ -1,1574 +0,0 @@ -/*- - * SPDX-License-Identifier: (BSD-2-Clause-FreeBSD AND BSD-3-Clause) - * - * Copyright (c) 2006-2008 Sam Leffler, Errno Consulting - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - */ - -/*- - * Copyright (c) 2001-2005, Intel Corporation. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. -*/ -#include -__FBSDID("$FreeBSD$"); - -/* - * Intel XScale Network Processing Engine (NPE) support. - * - * Each NPE has an ixpnpeX device associated with it that is - * attached at boot. Depending on the microcode loaded into - * an NPE there may be an Ethernet interface (npeX) or some - * other network interface (e.g. for ATM). This file has support - * for loading microcode images and the associated NPE CPU - * manipulations (start, stop, reset). - * - * The code here basically replaces the npeDl and npeMh classes - * in the Intel Access Library (IAL). - * - * NB: Microcode images are loaded with firmware(9). To - * include microcode in a static kernel include the - * ixpnpe_fw device. Otherwise the firmware will be - * automatically loaded from the filesystem. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include - -#include -#include - -struct ixpnpe_softc { - device_t sc_dev; - bus_space_tag_t sc_iot; - bus_space_handle_t sc_ioh; - bus_size_t sc_size; /* size of mapped register window */ - struct resource *sc_irq; /* IRQ resource */ - void *sc_ih; /* interrupt handler */ - struct mtx sc_mtx; /* mailbox lock */ - uint32_t sc_msg[2]; /* reply msg collected in ixpnpe_intr */ - int sc_msgwaiting; /* sc_msg holds valid data */ - int sc_npeid; - int sc_nrefs; /* # of references */ - - int validImage; /* valid ucode image loaded */ - int started; /* NPE is started */ - uint8_t functionalityId;/* ucode functionality ID */ - int insMemSize; /* size of instruction memory */ - int dataMemSize; /* size of data memory */ - uint32_t savedExecCount; - uint32_t savedEcsDbgCtxtReg2; -}; -static struct ixpnpe_softc *npes[NPE_MAX]; - -#define IX_NPEDL_NPEIMAGE_FIELD_MASK 0xff - -/* used to read download map from version in microcode image */ -#define IX_NPEDL_BLOCK_TYPE_INSTRUCTION 0x00000000 -#define IX_NPEDL_BLOCK_TYPE_DATA 0x00000001 -#define IX_NPEDL_BLOCK_TYPE_STATE 0x00000002 -#define IX_NPEDL_END_OF_DOWNLOAD_MAP 0x0000000F - -/* - * masks used to extract address info from State information context - * register addresses as read from microcode image - */ -#define IX_NPEDL_MASK_STATE_ADDR_CTXT_REG 0x0000000F -#define IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM 0x000000F0 - -/* LSB offset of Context Number field in State-Info Context Address */ -#define IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM 4 - -/* size (in words) of single State Information entry (ctxt reg address|data) */ -#define IX_NPEDL_STATE_INFO_ENTRY_SIZE 2 - -typedef struct { - uint32_t type; - uint32_t offset; -} IxNpeDlNpeMgrDownloadMapBlockEntry; - -typedef union { - IxNpeDlNpeMgrDownloadMapBlockEntry block; - uint32_t eodmMarker; -} IxNpeDlNpeMgrDownloadMapEntry; - -typedef struct { - /* 1st entry in the download map (there may be more than one) */ - IxNpeDlNpeMgrDownloadMapEntry entry[1]; -} IxNpeDlNpeMgrDownloadMap; - -/* used to access an instruction or data block in a microcode image */ -typedef struct { - uint32_t npeMemAddress; - uint32_t size; - uint32_t data[1]; -} IxNpeDlNpeMgrCodeBlock; - -/* used to access each Context Reg entry state-information block */ -typedef struct { - uint32_t addressInfo; - uint32_t value; -} IxNpeDlNpeMgrStateInfoCtxtRegEntry; - -/* used to access a state-information block in a microcode image */ -typedef struct { - uint32_t size; - IxNpeDlNpeMgrStateInfoCtxtRegEntry ctxtRegEntry[1]; -} IxNpeDlNpeMgrStateInfoBlock; - -static int npe_debug = 0; -SYSCTL_INT(_debug, OID_AUTO, ixp425npe, CTLFLAG_RWTUN, &npe_debug, - 0, "IXP4XX NPE debug msgs"); -#define DPRINTF(dev, fmt, ...) do { \ - if (npe_debug) device_printf(dev, fmt, __VA_ARGS__); \ -} while (0) -#define DPRINTFn(n, dev, fmt, ...) do { \ - if (npe_debug >= n) printf(fmt, __VA_ARGS__); \ -} while (0) - -static int npe_checkbits(struct ixpnpe_softc *, uint32_t reg, uint32_t); -static int npe_isstopped(struct ixpnpe_softc *); -static int npe_load_ins(struct ixpnpe_softc *, - const IxNpeDlNpeMgrCodeBlock *bp, int verify); -static int npe_load_data(struct ixpnpe_softc *, - const IxNpeDlNpeMgrCodeBlock *bp, int verify); -static int npe_load_stateinfo(struct ixpnpe_softc *, - const IxNpeDlNpeMgrStateInfoBlock *bp, int verify); -static int npe_load_image(struct ixpnpe_softc *, - const uint32_t *imageCodePtr, int verify); -static int npe_cpu_reset(struct ixpnpe_softc *); -static int npe_cpu_start(struct ixpnpe_softc *); -static int npe_cpu_stop(struct ixpnpe_softc *); -static void npe_cmd_issue_write(struct ixpnpe_softc *, - uint32_t cmd, uint32_t addr, uint32_t data); -static uint32_t npe_cmd_issue_read(struct ixpnpe_softc *, - uint32_t cmd, uint32_t addr); -static int npe_ins_write(struct ixpnpe_softc *, - uint32_t addr, uint32_t data, int verify); -static int npe_data_write(struct ixpnpe_softc *, - uint32_t addr, uint32_t data, int verify); -static void npe_ecs_reg_write(struct ixpnpe_softc *, - uint32_t reg, uint32_t data); -static uint32_t npe_ecs_reg_read(struct ixpnpe_softc *, uint32_t reg); -static void npe_issue_cmd(struct ixpnpe_softc *, uint32_t command); -static void npe_cpu_step_save(struct ixpnpe_softc *); -static int npe_cpu_step(struct ixpnpe_softc *, uint32_t npeInstruction, - uint32_t ctxtNum, uint32_t ldur); -static void npe_cpu_step_restore(struct ixpnpe_softc *); -static int npe_logical_reg_read(struct ixpnpe_softc *, - uint32_t regAddr, uint32_t regSize, - uint32_t ctxtNum, uint32_t *regVal); -static int npe_logical_reg_write(struct ixpnpe_softc *, - uint32_t regAddr, uint32_t regVal, - uint32_t regSize, uint32_t ctxtNum, int verify); -static int npe_physical_reg_write(struct ixpnpe_softc *, - uint32_t regAddr, uint32_t regValue, int verify); -static int npe_ctx_reg_write(struct ixpnpe_softc *, uint32_t ctxtNum, - uint32_t ctxtReg, uint32_t ctxtRegVal, int verify); - -static void ixpnpe_intr(void *arg); - -static uint32_t -npe_reg_read(struct ixpnpe_softc *sc, bus_size_t off) -{ - uint32_t v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); - DPRINTFn(9, sc->sc_dev, "%s(0x%lx) => 0x%x\n", __func__, off, v); - return v; -} - -static void -npe_reg_write(struct ixpnpe_softc *sc, bus_size_t off, uint32_t val) -{ - DPRINTFn(9, sc->sc_dev, "%s(0x%lx, 0x%x)\n", __func__, off, val); - bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); -} - -struct ixpnpe_softc * -ixpnpe_attach(device_t dev, int npeid) -{ - struct npeconfig { - uint32_t base; - uint32_t size; - int irq; - uint32_t ins_memsize; - uint32_t data_memsize; - }; - static const struct npeconfig npeconfigs[NPE_MAX] = { - [NPE_A] = { - .base = IXP425_NPE_A_HWBASE, - .size = IXP425_NPE_A_SIZE, - .irq = IXP425_INT_NPE_A, - .ins_memsize = IX_NPEDL_INS_MEMSIZE_WORDS_NPEA, - .data_memsize = IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA - }, - [NPE_B] = { - .base = IXP425_NPE_B_HWBASE, - .size = IXP425_NPE_B_SIZE, - .irq = IXP425_INT_NPE_B, - .ins_memsize = IX_NPEDL_INS_MEMSIZE_WORDS_NPEB, - .data_memsize = IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB - }, - [NPE_C] = { - .base = IXP425_NPE_C_HWBASE, - .size = IXP425_NPE_C_SIZE, - .irq = IXP425_INT_NPE_C, - .ins_memsize = IX_NPEDL_INS_MEMSIZE_WORDS_NPEC, - .data_memsize = IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC - }, - }; - struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); - struct ixpnpe_softc *sc; - const struct npeconfig *config; - int rid; - - if (npeid >= NPE_MAX) { - device_printf(dev, "%s: bad npeid %d\n", __func__, npeid); - return NULL; - } - sc = npes[npeid]; - if (sc != NULL) { - sc->sc_nrefs++; - return sc; - } - config = &npeconfigs[npeid]; - - /* XXX M_BUS */ - sc = malloc(sizeof(struct ixpnpe_softc), M_TEMP, M_WAITOK | M_ZERO); - sc->sc_dev = dev; - sc->sc_iot = sa->sc_iot; - mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "npe driver", MTX_DEF); - sc->sc_npeid = npeid; - sc->sc_nrefs = 1; - - sc->sc_size = config->size; - if (cpu_is_ixp42x()) { - /* NB: instruction/data memory sizes are NPE-dependent */ - sc->insMemSize = config->ins_memsize; - sc->dataMemSize = config->data_memsize; - } else { - sc->insMemSize = IXP46X_NPEDL_INS_MEMSIZE_WORDS; - sc->dataMemSize = IXP46X_NPEDL_DATA_MEMSIZE_WORDS; - } - - if (bus_space_map(sc->sc_iot, config->base, sc->sc_size, 0, &sc->sc_ioh)) - panic("%s: Cannot map registers", device_get_name(dev)); - - /* - * Setup IRQ and handler for NPE message support. - */ - rid = 0; - sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, - config->irq, config->irq, 1, RF_ACTIVE); - if (sc->sc_irq == NULL) - panic("%s: Unable to allocate irq %u", device_get_name(dev), - config->irq); - /* XXX could be a source of entropy */ - bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, - NULL, ixpnpe_intr, sc, &sc->sc_ih); - /* - * Enable output fifo interrupts (NB: must also set OFIFO Write Enable) - */ - npe_reg_write(sc, IX_NPECTL, - npe_reg_read(sc, IX_NPECTL) | (IX_NPECTL_OFE | IX_NPECTL_OFWE)); - - npes[npeid] = sc; - - return sc; -} - -void -ixpnpe_detach(struct ixpnpe_softc *sc) -{ - if (--sc->sc_nrefs == 0) { - npes[sc->sc_npeid] = NULL; - - /* disable output fifo interrupts */ - npe_reg_write(sc, IX_NPECTL, - npe_reg_read(sc, IX_NPECTL) &~ (IX_NPECTL_OFE | IX_NPECTL_OFWE)); - - bus_teardown_intr(sc->sc_dev, sc->sc_irq, sc->sc_ih); - bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size); - mtx_destroy(&sc->sc_mtx); - free(sc, M_TEMP); - } -} - -int -ixpnpe_stopandreset(struct ixpnpe_softc *sc) -{ - int error; - - mtx_lock(&sc->sc_mtx); - error = npe_cpu_stop(sc); /* stop NPE */ - if (error == 0) - error = npe_cpu_reset(sc); /* reset it */ - if (error == 0) - sc->started = 0; /* mark stopped */ - mtx_unlock(&sc->sc_mtx); - - DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error); - return error; -} - -static int -ixpnpe_start_locked(struct ixpnpe_softc *sc) -{ - int error; - - if (!sc->started) { - error = npe_cpu_start(sc); - if (error == 0) - sc->started = 1; - } else - error = 0; - - DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error); - return error; -} - -int -ixpnpe_start(struct ixpnpe_softc *sc) -{ - int ret; - - mtx_lock(&sc->sc_mtx); - ret = ixpnpe_start_locked(sc); - mtx_unlock(&sc->sc_mtx); - return (ret); -} - -int -ixpnpe_stop(struct ixpnpe_softc *sc) -{ - int error; - - mtx_lock(&sc->sc_mtx); - error = npe_cpu_stop(sc); - if (error == 0) - sc->started = 0; - mtx_unlock(&sc->sc_mtx); - - DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error); - return error; -} - -/* - * Indicates the start of an NPE Image, in new NPE Image Library format. - * 2 consecutive occurrences indicates the end of the NPE Image Library - */ -#define NPE_IMAGE_MARKER 0xfeedf00d - -/* - * NPE Image Header definition, used in new NPE Image Library format - */ -typedef struct { - uint32_t marker; - uint32_t id; - uint32_t size; -} IxNpeDlImageMgrImageHeader; - -static int -npe_findimage(struct ixpnpe_softc *sc, - const uint32_t *imageLibrary, uint32_t imageId, - const uint32_t **imagePtr, uint32_t *imageSize) -{ - const IxNpeDlImageMgrImageHeader *image; - uint32_t offset = 0; - - while (imageLibrary[offset] == NPE_IMAGE_MARKER) { - image = (const IxNpeDlImageMgrImageHeader *) - &imageLibrary[offset]; - offset += sizeof(IxNpeDlImageMgrImageHeader)/sizeof(uint32_t); - - DPRINTF(sc->sc_dev, "%s: off %u mark 0x%x id 0x%x size %u\n", - __func__, offset, image->marker, image->id, image->size); - if (image->id == imageId) { - *imagePtr = imageLibrary + offset; - *imageSize = image->size; - return 0; - } - /* 2 consecutive NPE_IMAGE_MARKER's indicates end of library */ - if (image->id == NPE_IMAGE_MARKER) { - DPRINTF(sc->sc_dev, "imageId 0x%08x not found in " - "image library header\n", imageId); - /* reached end of library, image not found */ - return ESRCH; - } - offset += image->size; - } - return ESRCH; -} - -static int -ixpnpe_load_firmware(struct ixpnpe_softc *sc, const char *imageName, - uint32_t imageId) -{ - static const char *devname[4] = - { "IXP425", "IXP435/IXP465", "DeviceID#2", "DeviceID#3" }; - uint32_t imageSize; - const uint32_t *imageCodePtr; - const struct firmware *fw; - int error; - - DPRINTF(sc->sc_dev, "load %s, imageId 0x%08x\n", imageName, imageId); - -#if 0 - IxFeatureCtrlDeviceId devid = IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId); - /* - * Checking if image being loaded is meant for device that is running. - * Image is forward compatible. i.e Image built for IXP42X should run - * on IXP46X but not vice versa. - */ - if (devid > (ixFeatureCtrlDeviceRead() & IX_FEATURE_CTRL_DEVICE_TYPE_MASK)) - return EINVAL; -#endif - error = ixpnpe_stopandreset(sc); /* stop and reset the NPE */ - if (error != 0) - return error; - - fw = firmware_get(imageName); - if (fw == NULL) - return ENOENT; - - /* Locate desired image in files w/ combined images */ - error = npe_findimage(sc, fw->data, imageId, &imageCodePtr, &imageSize); - if (error != 0) - goto done; - - device_printf(sc->sc_dev, - "load fw image %s.NPE-%c Func 0x%x Rev %u.%u\n", - devname[NPEIMAGE_DEVID(imageId)], 'A' + NPEIMAGE_NPEID(imageId), - NPEIMAGE_FUNCID(imageId), NPEIMAGE_MAJOR(imageId), - NPEIMAGE_MINOR(imageId)); - - /* - * If download was successful, store image Id in list of - * currently loaded images. If a critical error occurred - * during download, record that the NPE has an invalid image - */ - mtx_lock(&sc->sc_mtx); - error = npe_load_image(sc, imageCodePtr, 1 /*VERIFY*/); - if (error == 0) { - sc->validImage = 1; - error = ixpnpe_start_locked(sc); - } else { - sc->validImage = 0; - } - sc->functionalityId = IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId); - mtx_unlock(&sc->sc_mtx); -done: - firmware_put(fw, FIRMWARE_UNLOAD); - DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error); - return error; -} - -static int -override_imageid(device_t dev, const char *resname, uint32_t *val) -{ - int unit = device_get_unit(dev); - int resval; - - if (resource_int_value("npe", unit, resname, &resval) != 0) - return 0; - /* XXX validate */ - if (bootverbose) - device_printf(dev, "using npe.%d.%s=0x%x override\n", - unit, resname, resval); - *val = resval; - return 1; -} - -int -ixpnpe_init(struct ixpnpe_softc *sc) -{ - static const uint32_t npeconfig[NPE_MAX] = { - [NPE_A] = IXP425_NPE_A_IMAGEID, - [NPE_B] = IXP425_NPE_B_IMAGEID, - [NPE_C] = IXP425_NPE_C_IMAGEID, - }; - uint32_t imageid, msg[2]; - int error; - - if (sc->started) - return 0; - /* - * Load NPE firmware and start it running. We assume - * that minor version bumps remain compatible so probe - * the firmware image starting with the expected version - * and then bump the minor version up to the max. - */ - if (!override_imageid(sc->sc_dev, "imageid", &imageid)) - imageid = npeconfig[sc->sc_npeid]; - for (;;) { - error = ixpnpe_load_firmware(sc, "npe_fw", imageid); - if (error == 0) - break; - /* - * ESRCH is returned when the requested image - * is not present - */ - if (error != ESRCH) { - device_printf(sc->sc_dev, - "cannot init NPE (error %d)\n", error); - return error; - } - /* bump the minor version up to the max possible */ - if (NPEIMAGE_MINOR(imageid) == 0xff) { - device_printf(sc->sc_dev, "cannot locate firmware " - "(imageid 0x%08x)\n", imageid); - return error; - } - imageid++; - } - /* NB: firmware should respond with a status msg */ - if (ixpnpe_recvmsg_sync(sc, msg) != 0) { - device_printf(sc->sc_dev, - "firmware did not respond as expected\n"); - return EIO; - } - return 0; -} - -int -ixpnpe_getfunctionality(struct ixpnpe_softc *sc) -{ - return (sc->validImage ? sc->functionalityId : 0); -} - -static int -npe_checkbits(struct ixpnpe_softc *sc, uint32_t reg, uint32_t expectedBitsSet) -{ - uint32_t val; - - val = npe_reg_read(sc, reg); - DPRINTFn(5, sc->sc_dev, "%s(0x%x, 0x%x) => 0x%x (%u)\n", - __func__, reg, expectedBitsSet, val, - (val & expectedBitsSet) == expectedBitsSet); - return ((val & expectedBitsSet) == expectedBitsSet); -} - -static int -npe_isstopped(struct ixpnpe_softc *sc) -{ - return npe_checkbits(sc, - IX_NPEDL_REG_OFFSET_EXCTL, IX_NPEDL_EXCTL_STATUS_STOP); -} - -static int -npe_load_ins(struct ixpnpe_softc *sc, - const IxNpeDlNpeMgrCodeBlock *bp, int verify) -{ - uint32_t npeMemAddress; - int i, blockSize; - - npeMemAddress = bp->npeMemAddress; - blockSize = bp->size; /* NB: instruction/data count */ - if (npeMemAddress + blockSize > sc->insMemSize) { - device_printf(sc->sc_dev, - "Block size %u too big for NPE memory\n", blockSize); - return EINVAL; /* XXX */ - } - for (i = 0; i < blockSize; i++, npeMemAddress++) { - if (npe_ins_write(sc, npeMemAddress, bp->data[i], verify) != 0) { - device_printf(sc->sc_dev, - "NPE instruction write failed"); - return EIO; - } - } - return 0; -} - -static int -npe_load_data(struct ixpnpe_softc *sc, - const IxNpeDlNpeMgrCodeBlock *bp, int verify) -{ - uint32_t npeMemAddress; - int i, blockSize; - - npeMemAddress = bp->npeMemAddress; - blockSize = bp->size; /* NB: instruction/data count */ - if (npeMemAddress + blockSize > sc->dataMemSize) { - device_printf(sc->sc_dev, - "Block size %u too big for NPE memory\n", blockSize); - return EINVAL; - } - for (i = 0; i < blockSize; i++, npeMemAddress++) { - if (npe_data_write(sc, npeMemAddress, bp->data[i], verify) != 0) { - device_printf(sc->sc_dev, "NPE data write failed\n"); - return EIO; - } - } - return 0; -} - -static int -npe_load_stateinfo(struct ixpnpe_softc *sc, - const IxNpeDlNpeMgrStateInfoBlock *bp, int verify) -{ - int i, nentries, error; - - npe_cpu_step_save(sc); - - /* for each state-info context register entry in block */ - nentries = bp->size / IX_NPEDL_STATE_INFO_ENTRY_SIZE; - error = 0; - for (i = 0; i < nentries; i++) { - /* each state-info entry is 2 words (address, value) */ - uint32_t regVal = bp->ctxtRegEntry[i].value; - uint32_t addrInfo = bp->ctxtRegEntry[i].addressInfo; - - uint32_t reg = (addrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_REG); - uint32_t cNum = (addrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM) >> - IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM; - - /* error-check Context Register No. and Context Number values */ - if (!(0 <= reg && reg < IX_NPEDL_CTXT_REG_MAX)) { - device_printf(sc->sc_dev, - "invalid Context Register %u\n", reg); - error = EINVAL; - break; - } - if (!(0 <= cNum && cNum < IX_NPEDL_CTXT_NUM_MAX)) { - device_printf(sc->sc_dev, - "invalid Context Number %u\n", cNum); - error = EINVAL; - break; - } - /* NOTE that there is no STEVT register for Context 0 */ - if (cNum == 0 && reg == IX_NPEDL_CTXT_REG_STEVT) { - device_printf(sc->sc_dev, - "no STEVT for Context 0\n"); - error = EINVAL; - break; - } - - if (npe_ctx_reg_write(sc, cNum, reg, regVal, verify) != 0) { - device_printf(sc->sc_dev, - "write of state-info to NPE failed\n"); - error = EIO; - break; - } - } - - npe_cpu_step_restore(sc); - return error; -} - -static int -npe_load_image(struct ixpnpe_softc *sc, - const uint32_t *imageCodePtr, int verify) -{ -#define EOM(marker) ((marker) == IX_NPEDL_END_OF_DOWNLOAD_MAP) - const IxNpeDlNpeMgrDownloadMap *downloadMap; - int i, error; - - if (!npe_isstopped(sc)) { /* verify NPE is stopped */ - device_printf(sc->sc_dev, - "cannot load image, NPE not stopped\n"); - return EIO; - } - - /* - * Read Download Map, checking each block type and calling - * appropriate function to perform download - */ - error = 0; - downloadMap = (const IxNpeDlNpeMgrDownloadMap *) imageCodePtr; - for (i = 0; !EOM(downloadMap->entry[i].eodmMarker); i++) { - /* calculate pointer to block to be downloaded */ - const uint32_t *bp = imageCodePtr + - downloadMap->entry[i].block.offset; - switch (downloadMap->entry[i].block.type) { - case IX_NPEDL_BLOCK_TYPE_INSTRUCTION: - error = npe_load_ins(sc, - (const IxNpeDlNpeMgrCodeBlock *) bp, verify); - DPRINTF(sc->sc_dev, "%s: inst, error %d\n", - __func__, error); - break; - case IX_NPEDL_BLOCK_TYPE_DATA: - error = npe_load_data(sc, - (const IxNpeDlNpeMgrCodeBlock *) bp, verify); - DPRINTF(sc->sc_dev, "%s: data, error %d\n", - __func__, error); - break; - case IX_NPEDL_BLOCK_TYPE_STATE: - error = npe_load_stateinfo(sc, - (const IxNpeDlNpeMgrStateInfoBlock *) bp, verify); - DPRINTF(sc->sc_dev, "%s: state, error %d\n", - __func__, error); - break; - default: - device_printf(sc->sc_dev, - "unknown block type 0x%x in download map\n", - downloadMap->entry[i].block.type); - error = EIO; /* XXX */ - break; - } - if (error != 0) - break; - } - return error; -#undef EOM -} - -/* contains Reset values for Context Store Registers */ -static const struct { - uint32_t regAddr; - uint32_t regResetVal; -} ixNpeDlEcsRegResetValues[] = { - { IX_NPEDL_ECS_BG_CTXT_REG_0, IX_NPEDL_ECS_BG_CTXT_REG_0_RESET }, - { IX_NPEDL_ECS_BG_CTXT_REG_1, IX_NPEDL_ECS_BG_CTXT_REG_1_RESET }, - { IX_NPEDL_ECS_BG_CTXT_REG_2, IX_NPEDL_ECS_BG_CTXT_REG_2_RESET }, - { IX_NPEDL_ECS_PRI_1_CTXT_REG_0, IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET }, - { IX_NPEDL_ECS_PRI_1_CTXT_REG_1, IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET }, - { IX_NPEDL_ECS_PRI_1_CTXT_REG_2, IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET }, - { IX_NPEDL_ECS_PRI_2_CTXT_REG_0, IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET }, - { IX_NPEDL_ECS_PRI_2_CTXT_REG_1, IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET }, - { IX_NPEDL_ECS_PRI_2_CTXT_REG_2, IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET }, - { IX_NPEDL_ECS_DBG_CTXT_REG_0, IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET }, - { IX_NPEDL_ECS_DBG_CTXT_REG_1, IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET }, - { IX_NPEDL_ECS_DBG_CTXT_REG_2, IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET }, - { IX_NPEDL_ECS_INSTRUCT_REG, IX_NPEDL_ECS_INSTRUCT_REG_RESET } -}; - -/* contains Reset values for Context Store Registers */ -static const uint32_t ixNpeDlCtxtRegResetValues[] = { - IX_NPEDL_CTXT_REG_RESET_STEVT, - IX_NPEDL_CTXT_REG_RESET_STARTPC, - IX_NPEDL_CTXT_REG_RESET_REGMAP, - IX_NPEDL_CTXT_REG_RESET_CINDEX, -}; - -#define IX_NPEDL_PARITY_BIT_MASK 0x3F00FFFF -#define IX_NPEDL_CONFIG_CTRL_REG_MASK 0x3F3FFFFF - -#if 0 -/* - * Reset the NPE and its coprocessor using the - * fuse bits in the feature control register. - */ -static void -npe_reset(int npeid) -{ - uint32_t mask = EXP_FCTRL_NPEA << npeid; - uint32_t v; - - v = ixp4xx_read_feature_bits(); - ixp4xx_write_feature_bits(v &~ mask); - /* un-fuse and un-reset the NPE & coprocessor */ - ixp4xx_write_feature_bits(v | mask); -} -#endif - -static int -npe_cpu_reset(struct ixpnpe_softc *sc) -{ -#define N(a) (sizeof(a) / sizeof(a[0])) - uint32_t ctxtReg; /* identifies Context Store reg (0-3) */ - uint32_t regAddr; - uint32_t regVal; - uint32_t ixNpeConfigCtrlRegVal; - int i, error = 0; - - /* pre-store the NPE Config Control Register Value */ - ixNpeConfigCtrlRegVal = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_CTL); - ixNpeConfigCtrlRegVal |= 0x3F000000; - - /* disable the parity interrupt */ - npe_reg_write(sc, IX_NPEDL_REG_OFFSET_CTL, - (ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK)); - DPRINTFn(2, sc->sc_dev, "%s: dis parity int, CTL => 0x%x\n", - __func__, ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK); - - npe_cpu_step_save(sc); - - /* - * Clear the FIFOs. - */ - while (npe_checkbits(sc, - IX_NPEDL_REG_OFFSET_WFIFO, IX_NPEDL_MASK_WFIFO_VALID)) { - /* read from the Watch-point FIFO until empty */ - (void) npe_reg_read(sc, IX_NPEDL_REG_OFFSET_WFIFO); - } - - while (npe_checkbits(sc, - IX_NPEDL_REG_OFFSET_STAT, IX_NPEDL_MASK_STAT_OFNE)) { - /* read from the outFIFO until empty */ - (void) npe_reg_read(sc, IX_NPEDL_REG_OFFSET_FIFO); - } - - while (npe_checkbits(sc, - IX_NPEDL_REG_OFFSET_STAT, IX_NPEDL_MASK_STAT_IFNE)) { - /* - * Step execution of the NPE instruction to read inFIFO using - * the Debug Executing Context stack. - */ - error = npe_cpu_step(sc, IX_NPEDL_INSTR_RD_FIFO, 0, 0); - if (error != 0) { - DPRINTF(sc->sc_dev, "%s: cannot step (1), error %u\n", - __func__, error); - npe_cpu_step_restore(sc); - return error; - } - } - - /* - * Reset the mailbox reg - */ - /* ...from XScale side */ - npe_reg_write(sc, IX_NPEDL_REG_OFFSET_MBST, IX_NPEDL_REG_RESET_MBST); - /* ...from NPE side */ - error = npe_cpu_step(sc, IX_NPEDL_INSTR_RESET_MBOX, 0, 0); - if (error != 0) { - DPRINTF(sc->sc_dev, "%s: cannot step (2), error %u\n", - __func__, error); - npe_cpu_step_restore(sc); - return error; - } - - /* - * Reset the physical registers in the NPE register file: - * Note: no need to save/restore REGMAP for Context 0 here - * since all Context Store regs are reset in subsequent code. - */ - for (regAddr = 0; - regAddr < IX_NPEDL_TOTAL_NUM_PHYS_REG && error == 0; - regAddr++) { - /* for each physical register in the NPE reg file, write 0 : */ - error = npe_physical_reg_write(sc, regAddr, 0, TRUE); - if (error != 0) { - DPRINTF(sc->sc_dev, "%s: cannot write phy reg," - "error %u\n", __func__, error); - npe_cpu_step_restore(sc); - return error; /* abort reset */ - } - } - - /* - * Reset the context store: - */ - for (i = IX_NPEDL_CTXT_NUM_MIN; i <= IX_NPEDL_CTXT_NUM_MAX; i++) { - /* set each context's Context Store registers to reset values */ - for (ctxtReg = 0; ctxtReg < IX_NPEDL_CTXT_REG_MAX; ctxtReg++) { - /* NOTE that there is no STEVT register for Context 0 */ - if (i == 0 && ctxtReg == IX_NPEDL_CTXT_REG_STEVT) - continue; - regVal = ixNpeDlCtxtRegResetValues[ctxtReg]; - error = npe_ctx_reg_write(sc, i, ctxtReg, - regVal, TRUE); - if (error != 0) { - DPRINTF(sc->sc_dev, "%s: cannot write ctx reg," - "error %u\n", __func__, error); - npe_cpu_step_restore(sc); - return error; /* abort reset */ - } - } - } - - npe_cpu_step_restore(sc); - - /* write Reset values to Execution Context Stack registers */ - for (i = 0; i < N(ixNpeDlEcsRegResetValues); i++) - npe_ecs_reg_write(sc, - ixNpeDlEcsRegResetValues[i].regAddr, - ixNpeDlEcsRegResetValues[i].regResetVal); - - /* clear the profile counter */ - npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT); - - /* clear registers EXCT, AP0, AP1, AP2 and AP3 */ - for (regAddr = IX_NPEDL_REG_OFFSET_EXCT; - regAddr <= IX_NPEDL_REG_OFFSET_AP3; - regAddr += sizeof(uint32_t)) - npe_reg_write(sc, regAddr, 0); - - /* Reset the Watch-count register */ - npe_reg_write(sc, IX_NPEDL_REG_OFFSET_WC, 0); -#if 0 - /* - * WR IXA00055043 - Remove IMEM Parity Introduced by NPE Reset Operation - * XXX Removed because it breaks IXP435 operation; e.g. on Gateworks - * XXX 2358 boards reseting NPE-A after NPE-C is running causes both - * XXX npe's to stop working - */ - npe_reset(sc->sc_npeid); -#endif - /* - * Call NpeMgr function to stop the NPE again after the Feature Control - * has unfused and Un-Reset the NPE and its associated Coprocessors. - */ - error = npe_cpu_stop(sc); - - /* restore NPE configuration bus Control Register - Parity Settings */ - npe_reg_write(sc, IX_NPEDL_REG_OFFSET_CTL, - (ixNpeConfigCtrlRegVal & IX_NPEDL_CONFIG_CTRL_REG_MASK)); - DPRINTFn(2, sc->sc_dev, "%s: restore CTL => 0x%x\n", - __func__, npe_reg_read(sc, IX_NPEDL_REG_OFFSET_CTL)); - - return error; -#undef N -} - -static int -npe_cpu_start(struct ixpnpe_softc *sc) -{ - uint32_t ecsRegVal; - - /* - * Ensure only Background Context Stack Level is Active by turning off - * the Active bit in each of the other Executing Context Stack levels. - */ - ecsRegVal = npe_ecs_reg_read(sc, IX_NPEDL_ECS_PRI_1_CTXT_REG_0); - ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE; - npe_ecs_reg_write(sc, IX_NPEDL_ECS_PRI_1_CTXT_REG_0, ecsRegVal); - - ecsRegVal = npe_ecs_reg_read(sc, IX_NPEDL_ECS_PRI_2_CTXT_REG_0); - ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE; - npe_ecs_reg_write(sc, IX_NPEDL_ECS_PRI_2_CTXT_REG_0, ecsRegVal); - - ecsRegVal = npe_ecs_reg_read(sc, IX_NPEDL_ECS_DBG_CTXT_REG_0); - ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE; - npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_0, ecsRegVal); - - /* clear the pipeline */ - npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE); - - /* start NPE execution by issuing cmd through EXCTL register on NPE */ - npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_START); - - /* - * Check execution status of NPE to verify operation was successful. - */ - return npe_checkbits(sc, - IX_NPEDL_REG_OFFSET_EXCTL, IX_NPEDL_EXCTL_STATUS_RUN) ? 0 : EIO; -} - -static int -npe_cpu_stop(struct ixpnpe_softc *sc) -{ - /* stop NPE execution by issuing cmd through EXCTL register on NPE */ - npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_STOP); - - /* verify that NPE Stop was successful */ - return npe_checkbits(sc, - IX_NPEDL_REG_OFFSET_EXCTL, IX_NPEDL_EXCTL_STATUS_STOP) ? 0 : EIO; -} - -#define IX_NPEDL_REG_SIZE_BYTE 8 -#define IX_NPEDL_REG_SIZE_SHORT 16 -#define IX_NPEDL_REG_SIZE_WORD 32 - -/* - * Introduce extra read cycles after issuing read command to NPE - * so that we read the register after the NPE has updated it - * This is to overcome race condition between XScale and NPE - */ -#define IX_NPEDL_DELAY_READ_CYCLES 2 -/* - * To mask top three MSBs of 32bit word to download into NPE IMEM - */ -#define IX_NPEDL_MASK_UNUSED_IMEM_BITS 0x1FFFFFFF; - -static void -npe_cmd_issue_write(struct ixpnpe_softc *sc, - uint32_t cmd, uint32_t addr, uint32_t data) -{ - npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXDATA, data); - npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXAD, addr); - npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXCTL, cmd); -} - -static uint32_t -npe_cmd_issue_read(struct ixpnpe_softc *sc, uint32_t cmd, uint32_t addr) -{ - uint32_t data; - int i; - - npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXAD, addr); - npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXCTL, cmd); - for (i = 0; i <= IX_NPEDL_DELAY_READ_CYCLES; i++) - data = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_EXDATA); - return data; -} - -static int -npe_ins_write(struct ixpnpe_softc *sc, uint32_t addr, uint32_t data, int verify) -{ - DPRINTFn(4, sc->sc_dev, "%s(0x%x, 0x%x)\n", __func__, addr, data); - npe_cmd_issue_write(sc, IX_NPEDL_EXCTL_CMD_WR_INS_MEM, addr, data); - if (verify) { - uint32_t rdata; - - /* - * Write invalid data to this reg, so we can see if we're - * reading the EXDATA register too early. - */ - npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXDATA, ~data); - - /* - * Disabled since top 3 MSB are not used for Azusa - * hardware Refer WR:IXA00053900 - */ - data &= IX_NPEDL_MASK_UNUSED_IMEM_BITS; - - rdata = npe_cmd_issue_read(sc, IX_NPEDL_EXCTL_CMD_RD_INS_MEM, - addr); - rdata &= IX_NPEDL_MASK_UNUSED_IMEM_BITS; - - if (data != rdata) - return EIO; - } - return 0; -} - -static int -npe_data_write(struct ixpnpe_softc *sc, uint32_t addr, uint32_t data, int verify) -{ - DPRINTFn(4, sc->sc_dev, "%s(0x%x, 0x%x)\n", __func__, addr, data); - npe_cmd_issue_write(sc, IX_NPEDL_EXCTL_CMD_WR_DATA_MEM, addr, data); - if (verify) { - /* - * Write invalid data to this reg, so we can see if we're - * reading the EXDATA register too early. - */ - npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXDATA, ~data); - if (data != npe_cmd_issue_read(sc, IX_NPEDL_EXCTL_CMD_RD_DATA_MEM, addr)) - return EIO; - } - return 0; -} - -static void -npe_ecs_reg_write(struct ixpnpe_softc *sc, uint32_t reg, uint32_t data) -{ - npe_cmd_issue_write(sc, IX_NPEDL_EXCTL_CMD_WR_ECS_REG, reg, data); -} - -static uint32_t -npe_ecs_reg_read(struct ixpnpe_softc *sc, uint32_t reg) -{ - return npe_cmd_issue_read(sc, IX_NPEDL_EXCTL_CMD_RD_ECS_REG, reg); -} - -static void -npe_issue_cmd(struct ixpnpe_softc *sc, uint32_t command) -{ - npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXCTL, command); -} - -static void -npe_cpu_step_save(struct ixpnpe_softc *sc) -{ - /* turn off the halt bit by clearing Execution Count register. */ - /* save reg contents 1st and restore later */ - sc->savedExecCount = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_EXCT); - npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXCT, 0); - - /* ensure that IF and IE are on (temporarily), so that we don't end up - * stepping forever */ - sc->savedEcsDbgCtxtReg2 = npe_ecs_reg_read(sc, - IX_NPEDL_ECS_DBG_CTXT_REG_2); - - npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_2, - (sc->savedEcsDbgCtxtReg2 | IX_NPEDL_MASK_ECS_DBG_REG_2_IF | - IX_NPEDL_MASK_ECS_DBG_REG_2_IE)); -} - -static int -npe_cpu_step(struct ixpnpe_softc *sc, uint32_t npeInstruction, - uint32_t ctxtNum, uint32_t ldur) -{ -#define IX_NPE_DL_MAX_NUM_OF_RETRIES 1000000 - uint32_t ecsDbgRegVal; - uint32_t oldWatchcount, newWatchcount; - int tries; - - /* set the Active bit, and the LDUR, in the debug level */ - ecsDbgRegVal = IX_NPEDL_MASK_ECS_REG_0_ACTIVE | - (ldur << IX_NPEDL_OFFSET_ECS_REG_0_LDUR); - - npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_0, ecsDbgRegVal); - - /* - * Set CCTXT at ECS DEBUG L3 to specify in which context to execute the - * instruction, and set SELCTXT at ECS DEBUG Level to specify which - * context store to access. - * Debug ECS Level Reg 1 has form 0x000n000n, where n = context number - */ - ecsDbgRegVal = (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_CCTXT) | - (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT); - - npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_1, ecsDbgRegVal); - - /* clear the pipeline */ - npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE); - - /* load NPE instruction into the instruction register */ - npe_ecs_reg_write(sc, IX_NPEDL_ECS_INSTRUCT_REG, npeInstruction); - - /* need this value later to wait for completion of NPE execution step */ - oldWatchcount = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_WC); - - /* issue a Step One command via the Execution Control register */ - npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_STEP); - - /* - * Force the XScale to wait until the NPE has finished execution step - * NOTE that this delay will be very small, just long enough to allow a - * single NPE instruction to complete execution; if instruction - * execution is not completed before timeout retries, exit the while - * loop. - */ - newWatchcount = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_WC); - for (tries = 0; tries < IX_NPE_DL_MAX_NUM_OF_RETRIES && - newWatchcount == oldWatchcount; tries++) { - /* Watch Count register incr's when NPE completes an inst */ - newWatchcount = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_WC); - } - return (tries < IX_NPE_DL_MAX_NUM_OF_RETRIES) ? 0 : EIO; -#undef IX_NPE_DL_MAX_NUM_OF_RETRIES -} - -static void -npe_cpu_step_restore(struct ixpnpe_softc *sc) -{ - /* clear active bit in debug level */ - npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_0, 0); - - /* clear the pipeline */ - npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE); - - /* restore Execution Count register contents. */ - npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXCT, sc->savedExecCount); - - /* restore IF and IE bits to original values */ - npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_2, sc->savedEcsDbgCtxtReg2); -} - -static int -npe_logical_reg_read(struct ixpnpe_softc *sc, - uint32_t regAddr, uint32_t regSize, - uint32_t ctxtNum, uint32_t *regVal) -{ - uint32_t npeInstruction, mask; - int error; - - switch (regSize) { - case IX_NPEDL_REG_SIZE_BYTE: - npeInstruction = IX_NPEDL_INSTR_RD_REG_BYTE; - mask = 0xff; - break; - case IX_NPEDL_REG_SIZE_SHORT: - npeInstruction = IX_NPEDL_INSTR_RD_REG_SHORT; - mask = 0xffff; - break; - case IX_NPEDL_REG_SIZE_WORD: - npeInstruction = IX_NPEDL_INSTR_RD_REG_WORD; - mask = 0xffffffff; - break; - default: - return EINVAL; - } - - /* make regAddr be the SRC and DEST operands (e.g. movX d0, d0) */ - npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_SRC) | - (regAddr << IX_NPEDL_OFFSET_INSTR_DEST); - - /* step execution of NPE inst using Debug Executing Context stack */ - error = npe_cpu_step(sc, npeInstruction, ctxtNum, - IX_NPEDL_RD_INSTR_LDUR); - if (error != 0) { - DPRINTF(sc->sc_dev, "%s(0x%x, %u, %u), cannot step, error %d\n", - __func__, regAddr, regSize, ctxtNum, error); - return error; - } - /* read value of register from Execution Data register */ - *regVal = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_EXDATA); - - /* align value from left to right */ - *regVal = (*regVal >> (IX_NPEDL_REG_SIZE_WORD - regSize)) & mask; - - return 0; -} - -static int -npe_logical_reg_write(struct ixpnpe_softc *sc, uint32_t regAddr, uint32_t regVal, - uint32_t regSize, uint32_t ctxtNum, int verify) -{ - int error; - - DPRINTFn(4, sc->sc_dev, "%s(0x%x, 0x%x, %u, %u)\n", - __func__, regAddr, regVal, regSize, ctxtNum); - if (regSize == IX_NPEDL_REG_SIZE_WORD) { - /* - * NPE register addressing is left-to-right: e.g. |d0|d1|d2|d3| - * Write upper half-word (short) to |d0|d1| - */ - error = npe_logical_reg_write(sc, regAddr, - regVal >> IX_NPEDL_REG_SIZE_SHORT, - IX_NPEDL_REG_SIZE_SHORT, ctxtNum, verify); - if (error != 0) - return error; - - /* Write lower half-word (short) to |d2|d3| */ - error = npe_logical_reg_write(sc, - regAddr + sizeof(uint16_t), - regVal & 0xffff, - IX_NPEDL_REG_SIZE_SHORT, ctxtNum, verify); - } else { - uint32_t npeInstruction; - - switch (regSize) { - case IX_NPEDL_REG_SIZE_BYTE: - npeInstruction = IX_NPEDL_INSTR_WR_REG_BYTE; - regVal &= 0xff; - break; - case IX_NPEDL_REG_SIZE_SHORT: - npeInstruction = IX_NPEDL_INSTR_WR_REG_SHORT; - regVal &= 0xffff; - break; - default: - return EINVAL; - } - /* fill dest operand field of inst with dest reg addr */ - npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_DEST); - - /* fill src operand field of inst with least-sig 5 bits of val*/ - npeInstruction |= - ((regVal & IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA) << - IX_NPEDL_OFFSET_INSTR_SRC); - - /* fill coprocessor field of inst with most-sig 11 bits of val*/ - npeInstruction |= - ((regVal & IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA) << - IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA); - - /* step execution of NPE instruction using Debug ECS */ - error = npe_cpu_step(sc, npeInstruction, - ctxtNum, IX_NPEDL_WR_INSTR_LDUR); - } - if (error != 0) { - DPRINTF(sc->sc_dev, "%s(0x%x, 0x%x, %u, %u), error %u " - "writing reg\n", __func__, regAddr, regVal, regSize, - ctxtNum, error); - return error; - } - if (verify) { - uint32_t retRegVal; - - error = npe_logical_reg_read(sc, regAddr, regSize, ctxtNum, - &retRegVal); - if (error == 0 && regVal != retRegVal) - error = EIO; /* XXX ambiguous */ - } - return error; -} - -/* - * There are 32 physical registers used in an NPE. These are - * treated as 16 pairs of 32-bit registers. To write one of the pair, - * write the pair number (0-16) to the REGMAP for Context 0. Then write - * the value to register 0 or 4 in the regfile, depending on which - * register of the pair is to be written - */ -static int -npe_physical_reg_write(struct ixpnpe_softc *sc, - uint32_t regAddr, uint32_t regValue, int verify) -{ - int error; - - /* - * Set REGMAP for context 0 to (regAddr >> 1) to choose which pair - * (0-16) of physical registers to write . - */ - error = npe_logical_reg_write(sc, IX_NPEDL_CTXT_REG_ADDR_REGMAP, - (regAddr >> IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP), - IX_NPEDL_REG_SIZE_SHORT, 0, verify); - if (error == 0) { - /* regAddr = 0 or 4 */ - regAddr = (regAddr & IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR) * - sizeof(uint32_t); - error = npe_logical_reg_write(sc, regAddr, regValue, - IX_NPEDL_REG_SIZE_WORD, 0, verify); - } - return error; -} - -static int -npe_ctx_reg_write(struct ixpnpe_softc *sc, uint32_t ctxtNum, - uint32_t ctxtReg, uint32_t ctxtRegVal, int verify) -{ - DPRINTFn(4, sc->sc_dev, "%s(%u, %u, %u)\n", - __func__, ctxtNum, ctxtReg, ctxtRegVal); - /* - * Context 0 has no STARTPC. Instead, this value is used to set - * NextPC for Background ECS, to set where NPE starts executing code - */ - if (ctxtNum == 0 && ctxtReg == IX_NPEDL_CTXT_REG_STARTPC) { - /* read BG_CTXT_REG_0, update NEXTPC bits, & write back to reg*/ - uint32_t v = npe_ecs_reg_read(sc, IX_NPEDL_ECS_BG_CTXT_REG_0); - v &= ~IX_NPEDL_MASK_ECS_REG_0_NEXTPC; - v |= (ctxtRegVal << IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC) & - IX_NPEDL_MASK_ECS_REG_0_NEXTPC; - - npe_ecs_reg_write(sc, IX_NPEDL_ECS_BG_CTXT_REG_0, v); - return 0; - } else { - static const struct { - uint32_t regAddress; - uint32_t regSize; - } regAccInfo[IX_NPEDL_CTXT_REG_MAX] = { - { IX_NPEDL_CTXT_REG_ADDR_STEVT, - IX_NPEDL_REG_SIZE_BYTE }, - { IX_NPEDL_CTXT_REG_ADDR_STARTPC, - IX_NPEDL_REG_SIZE_SHORT }, - { IX_NPEDL_CTXT_REG_ADDR_REGMAP, - IX_NPEDL_REG_SIZE_SHORT }, - { IX_NPEDL_CTXT_REG_ADDR_CINDEX, - IX_NPEDL_REG_SIZE_BYTE } - }; - return npe_logical_reg_write(sc, regAccInfo[ctxtReg].regAddress, - ctxtRegVal, regAccInfo[ctxtReg].regSize, ctxtNum, verify); - } -} - -/* - * NPE Mailbox support. - */ -#define IX_NPEMH_MAXTRIES 100000 - -static int -ofifo_wait(struct ixpnpe_softc *sc) -{ - int i; - - for (i = 0; i < IX_NPEMH_MAXTRIES; i++) { - if (npe_reg_read(sc, IX_NPESTAT) & IX_NPESTAT_OFNE) - return 1; - DELAY(10); - } - device_printf(sc->sc_dev, "%s: timeout, last status 0x%x\n", - __func__, npe_reg_read(sc, IX_NPESTAT)); - return 0; -} - -static int -getmsg(struct ixpnpe_softc *sc, uint32_t msg[2]) -{ - mtx_assert(&sc->sc_mtx, MA_OWNED); - - if (!ofifo_wait(sc)) - return EAGAIN; - msg[0] = npe_reg_read(sc, IX_NPEFIFO); - DPRINTF(sc->sc_dev, "%s: msg0 0x%x\n", __func__, msg[0]); - if (!ofifo_wait(sc)) - return EAGAIN; - msg[1] = npe_reg_read(sc, IX_NPEFIFO); - DPRINTF(sc->sc_dev, "%s: msg1 0x%x\n", __func__, msg[1]); - return 0; -} - -static void -ixpnpe_intr(void *arg) -{ - struct ixpnpe_softc *sc = arg; - uint32_t status; - - mtx_lock(&sc->sc_mtx); - status = npe_reg_read(sc, IX_NPESTAT); - DPRINTF(sc->sc_dev, "%s: status 0x%x\n", __func__, status); - if ((status & IX_NPESTAT_OFINT) == 0) { - /* NB: should not happen */ - device_printf(sc->sc_dev, "%s: status 0x%x\n", - __func__, status); - /* XXX must silence interrupt? */ - mtx_unlock(&sc->sc_mtx); - return; - } - /* - * A message is waiting in the output FIFO, copy it so - * the interrupt will be silenced. - */ - if (getmsg(sc, sc->sc_msg) == 0) - sc->sc_msgwaiting = 1; - mtx_unlock(&sc->sc_mtx); -} - -static int -ififo_wait(struct ixpnpe_softc *sc) -{ - int i; - - for (i = 0; i < IX_NPEMH_MAXTRIES; i++) { - if (npe_reg_read(sc, IX_NPESTAT) & IX_NPESTAT_IFNF) - return 1; - DELAY(10); - } - device_printf(sc->sc_dev, "%s: timeout, last status 0x%x\n", - __func__, npe_reg_read(sc, IX_NPESTAT)); - return 0; -} - -static int -putmsg(struct ixpnpe_softc *sc, const uint32_t msg[2]) -{ - mtx_assert(&sc->sc_mtx, MA_OWNED); - - DPRINTF(sc->sc_dev, "%s: msg 0x%x:0x%x\n", __func__, msg[0], msg[1]); - if (!ififo_wait(sc)) - return EIO; - npe_reg_write(sc, IX_NPEFIFO, msg[0]); - if (!ififo_wait(sc)) - return EIO; - npe_reg_write(sc, IX_NPEFIFO, msg[1]); - - return 0; -} - -/* - * Send a msg to the NPE and wait for a reply. We spin as - * we may be called early with interrupts not properly setup. - */ -int -ixpnpe_sendandrecvmsg_sync(struct ixpnpe_softc *sc, - const uint32_t send[2], uint32_t recv[2]) -{ - int error; - - mtx_lock(&sc->sc_mtx); - error = putmsg(sc, send); - if (error == 0) - error = getmsg(sc, recv); - mtx_unlock(&sc->sc_mtx); - - return error; -} - -/* - * Send a msg to the NPE w/o waiting for a reply. - */ -int -ixpnpe_sendmsg_async(struct ixpnpe_softc *sc, const uint32_t msg[2]) -{ - int error; - - mtx_lock(&sc->sc_mtx); - error = putmsg(sc, msg); - mtx_unlock(&sc->sc_mtx); - - return error; -} - -static int -recvmsg_locked(struct ixpnpe_softc *sc, uint32_t msg[2]) -{ - mtx_assert(&sc->sc_mtx, MA_OWNED); - - DPRINTF(sc->sc_dev, "%s: msgwaiting %d\n", __func__, sc->sc_msgwaiting); - if (sc->sc_msgwaiting) { - msg[0] = sc->sc_msg[0]; - msg[1] = sc->sc_msg[1]; - sc->sc_msgwaiting = 0; - return 0; - } - return EAGAIN; -} - -/* - * Receive any msg previously received from the NPE. If nothing - * is available we return EAGAIN and the caller is required to - * do a synchronous receive or try again later. - */ -int -ixpnpe_recvmsg_async(struct ixpnpe_softc *sc, uint32_t msg[2]) -{ - int error; - - mtx_lock(&sc->sc_mtx); - error = recvmsg_locked(sc, msg); - mtx_unlock(&sc->sc_mtx); - - return error; -} - -/* - * Receive a msg from the NPE. If one was received asynchronously - * then it's returned; otherwise we poll synchronously. - */ -int -ixpnpe_recvmsg_sync(struct ixpnpe_softc *sc, uint32_t msg[2]) -{ - int error; - - mtx_lock(&sc->sc_mtx); - error = recvmsg_locked(sc, msg); - if (error == EAGAIN) - error = getmsg(sc, msg); - mtx_unlock(&sc->sc_mtx); - - return error; -} diff --git a/sys/arm/xscale/ixp425/ixp425_npereg.h b/sys/arm/xscale/ixp425/ixp425_npereg.h deleted file mode 100644 index cb9e6a4ef14f..000000000000 --- a/sys/arm/xscale/ixp425/ixp425_npereg.h +++ /dev/null @@ -1,429 +0,0 @@ -/*- - * SPDX-License-Identifier: (BSD-2-Clause-FreeBSD AND BSD-3-Clause) - * - * Copyright (c) 2006 Sam Leffler, Errno Consulting - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - * - * $FreeBSD$ - */ - -/*- - * Copyright (c) 2001-2005, Intel Corporation. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. -*/ - -#ifndef _IXP425_NPEREG_H_ -#define _IXP425_NPEREG_H_ - -/* signature found as 1st word in a microcode image library */ -#define IX_NPEDL_IMAGEMGR_SIGNATURE 0xDEADBEEF -/* marks end of header in a microcode image library */ -#define IX_NPEDL_IMAGEMGR_END_OF_HEADER 0xFFFFFFFF - -/* - * Intel (R) IXP400 Software NPE Image ID Definition - * - * Definition of NPE Image ID to be passed to ixNpeDlNpeInitAndStart() - * as input of type uint32_t which has the following fields format: - * - * Field [Bit Location] - * ----------------------------------- - * Device ID [31 - 28] - * NPE ID [27 - 24] - * NPE Functionality ID [23 - 16] - * Major Release Number [15 - 8] - * Minor Release Number [7 - 0] - */ -#define IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId) \ - (((imageId) >> 24) & 0xf) -#define IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId) \ - (((imageId) >> 28) & 0xf) -#define IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId) \ - (((imageId) >> 16) & 0xff) -#define IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId) \ - (((imageId) >> 8) & 0xff) -#define IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId) \ - (((imageId) >> 0) & 0xff) - -/* - * Instruction and Data Memory Size (in words) for each NPE - */ -#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 4096 -#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 2048 -#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC 2048 - -#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA 2048 -#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB 2048 -#define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC 2048 - -#define IXP46X_NPEDL_INS_MEMSIZE_WORDS 4096 -#define IXP46X_NPEDL_DATA_MEMSIZE_WORDS 4096 - -/* BAR offsets */ -#define IX_NPEDL_REG_OFFSET_EXAD 0x00000000 /* Execution Address */ -#define IX_NPEDL_REG_OFFSET_EXDATA 0x00000004 /* Execution Data */ -#define IX_NPEDL_REG_OFFSET_EXCTL 0x00000008 /* Execution Control */ -#define IX_NPEDL_REG_OFFSET_EXCT 0x0000000C /* Execution Count */ -#define IX_NPEDL_REG_OFFSET_AP0 0x00000010 /* Action Point 0 */ -#define IX_NPEDL_REG_OFFSET_AP1 0x00000014 /* Action Point 1 */ -#define IX_NPEDL_REG_OFFSET_AP2 0x00000018 /* Action Point 2 */ -#define IX_NPEDL_REG_OFFSET_AP3 0x0000001C /* Action Point 3 */ -#define IX_NPEDL_REG_OFFSET_WFIFO 0x00000020 /* Watchpoint FIFO */ -#define IX_NPEDL_REG_OFFSET_WC 0x00000024 /* Watch Count */ -#define IX_NPEDL_REG_OFFSET_PROFCT 0x00000028 /* Profile Count */ -#define IX_NPEDL_REG_OFFSET_STAT 0x0000002C /* Messaging Status */ -#define IX_NPEDL_REG_OFFSET_CTL 0x00000030 /* Messaging Control */ -#define IX_NPEDL_REG_OFFSET_MBST 0x00000034 /* Mailbox Status */ -#define IX_NPEDL_REG_OFFSET_FIFO 0x00000038 /* Message FIFO */ - -/* - * Reset value for Mailbox (MBST) register - * NOTE that if used, it should be complemented with an NPE instruction - * to clear the Mailbox at the NPE side as well - */ -#define IX_NPEDL_REG_RESET_MBST 0x0000F0F0 - -#define IX_NPEDL_MASK_WFIFO_VALID 0x80000000 /* VALID bit */ -#define IX_NPEDL_MASK_STAT_OFNE 0x00010000 /* OFNE bit */ -#define IX_NPEDL_MASK_STAT_IFNE 0x00080000 /* IFNE bit */ - -/* - * EXCTL (Execution Control) Register commands -*/ -#define IX_NPEDL_EXCTL_CMD_NPE_STEP 0x01 /* Step 1 instruction */ -#define IX_NPEDL_EXCTL_CMD_NPE_START 0x02 /* Start execution */ -#define IX_NPEDL_EXCTL_CMD_NPE_STOP 0x03 /* Stop execution */ -#define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE 0x04 /* Clear ins pipeline */ - -/* - * Read/write operations use address in EXAD and data in EXDATA. - */ -#define IX_NPEDL_EXCTL_CMD_RD_INS_MEM 0x10 /* Read ins memory */ -#define IX_NPEDL_EXCTL_CMD_WR_INS_MEM 0x11 /* Write ins memory */ -#define IX_NPEDL_EXCTL_CMD_RD_DATA_MEM 0x12 /* Read data memory */ -#define IX_NPEDL_EXCTL_CMD_WR_DATA_MEM 0x13 /* Write data memory */ -#define IX_NPEDL_EXCTL_CMD_RD_ECS_REG 0x14 /* Read ECS register */ -#define IX_NPEDL_EXCTL_CMD_WR_ECS_REG 0x15 /* Write ECS register */ - -#define IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT 0x0C /* Clear Profile Count register */ - - -/* - * EXCTL (Execution Control) Register status bit masks - */ -#define IX_NPEDL_EXCTL_STATUS_RUN 0x80000000 -#define IX_NPEDL_EXCTL_STATUS_STOP 0x40000000 -#define IX_NPEDL_EXCTL_STATUS_CLEAR 0x20000000 -#define IX_NPEDL_EXCTL_STATUS_ECS_K 0x00800000 /* pipeline Klean */ - -/* - * Executing Context Stack (ECS) level registers - */ -#define IX_NPEDL_ECS_BG_CTXT_REG_0 0x00 /* reg 0 @ bg ctx */ -#define IX_NPEDL_ECS_BG_CTXT_REG_1 0x01 /* reg 1 @ bg ctx */ -#define IX_NPEDL_ECS_BG_CTXT_REG_2 0x02 /* reg 2 @ bg ctx */ - -#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0 0x04 /* reg 0 @ pri 1 ctx */ -#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1 0x05 /* reg 1 @ pri 1 ctx */ -#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2 0x06 /* reg 2 @ pri 1 ctx */ - -#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0 0x08 /* reg 0 @ pri 2 ctx */ -#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1 0x09 /* reg 1 @ pri 2 ctx */ -#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2 0x0A /* reg 2 @ pri 2 ctx */ - -#define IX_NPEDL_ECS_DBG_CTXT_REG_0 0x0C /* reg 0 @ debug ctx */ -#define IX_NPEDL_ECS_DBG_CTXT_REG_1 0x0D /* reg 1 @ debug ctx */ -#define IX_NPEDL_ECS_DBG_CTXT_REG_2 0x0E /* reg 2 @ debug ctx */ - -#define IX_NPEDL_ECS_INSTRUCT_REG 0x11 /* Instruction reg */ - -/* - * Execution Access register reset values - */ -#define IX_NPEDL_ECS_BG_CTXT_REG_0_RESET 0xA0000000 -#define IX_NPEDL_ECS_BG_CTXT_REG_1_RESET 0x01000000 -#define IX_NPEDL_ECS_BG_CTXT_REG_2_RESET 0x00008000 -#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET 0x20000080 -#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET 0x01000000 -#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET 0x00008000 -#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET 0x20000080 -#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET 0x01000000 -#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET 0x00008000 -#define IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET 0x20000000 -#define IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET 0x00000000 -#define IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET 0x001E0000 -#define IX_NPEDL_ECS_INSTRUCT_REG_RESET 0x1003C00F - -/* - * Masks used to read/write particular bits in Execution Access registers - */ - -#define IX_NPEDL_MASK_ECS_REG_0_ACTIVE 0x80000000 /* Active bit */ -#define IX_NPEDL_MASK_ECS_REG_0_NEXTPC 0x1FFF0000 /* NextPC bits */ -#define IX_NPEDL_MASK_ECS_REG_0_LDUR 0x00000700 /* LDUR bits */ - -#define IX_NPEDL_MASK_ECS_REG_1_CCTXT 0x000F0000 /* NextPC bits */ -#define IX_NPEDL_MASK_ECS_REG_1_SELCTXT 0x0000000F - -#define IX_NPEDL_MASK_ECS_DBG_REG_2_IF 0x00100000 /* IF bit */ -#define IX_NPEDL_MASK_ECS_DBG_REG_2_IE 0x00080000 /* IE bit */ - - -/* - * Bit-Offsets from LSB of particular bit-fields in Execution Access registers. - */ - -#define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC 16 -#define IX_NPEDL_OFFSET_ECS_REG_0_LDUR 8 - -#define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT 16 -#define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT 0 - -/* - * NPE core & co-processor instruction templates to load into NPE Instruction - * Register, for read/write of NPE register file registers. - */ - -/* - * Read an 8-bit NPE internal logical register - * and return the value in the EXDATA register (aligned to MSB). - * NPE Assembler instruction: "mov8 d0, d0 &&& DBG_WrExec" - */ -#define IX_NPEDL_INSTR_RD_REG_BYTE 0x0FC00000 - -/* - * Read a 16-bit NPE internal logical register - * and return the value in the EXDATA register (aligned to MSB). - * NPE Assembler instruction: "mov16 d0, d0 &&& DBG_WrExec" - */ -#define IX_NPEDL_INSTR_RD_REG_SHORT 0x0FC08010 - -/* - * Read a 16-bit NPE internal logical register - * and return the value in the EXDATA register. - * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_WrExec" - */ -#define IX_NPEDL_INSTR_RD_REG_WORD 0x0FC08210 - -/* - * Write an 8-bit NPE internal logical register. - * NPE Assembler instruction: "mov8 d0, #0" - */ -#define IX_NPEDL_INSTR_WR_REG_BYTE 0x00004000 - -/* - * Write a 16-bit NPE internal logical register. - * NPE Assembler instruction: "mov16 d0, #0" - */ -#define IX_NPEDL_INSTR_WR_REG_SHORT 0x0000C000 - -/* - * Write a 16-bit NPE internal logical register. - * NPE Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO" - */ -#define IX_NPEDL_INSTR_RD_FIFO 0x0F888220 - -/* - * Reset Mailbox (MBST) register - * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_ClearM" - */ -#define IX_NPEDL_INSTR_RESET_MBOX 0x0FAC8210 - - -/* - * Bit-offsets from LSB, of particular bit-fields in an NPE instruction - */ -#define IX_NPEDL_OFFSET_INSTR_SRC 4 /* src operand */ -#define IX_NPEDL_OFFSET_INSTR_DEST 9 /* dest operand */ -#define IX_NPEDL_OFFSET_INSTR_COPROC 18 /* coprocessor ins */ - -/* - * Masks used to read/write particular bits of an NPE Instruction - */ - -/** - * Mask the bits of 16-bit data value (least-sig 5 bits) to be used in - * SRC field of immediate-mode NPE instruction - */ -#define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA 0x1F - -/** - * Mask the bits of 16-bit data value (most-sig 11 bits) to be used in - * COPROC field of immediate-mode NPE instruction - */ -#define IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA 0xFFE0 - -/** - * LSB offset of the bit-field of 16-bit data value (most-sig 11 bits) - * to be used in COPROC field of immediate-mode NPE instruction - */ -#define IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA 5 - -/** - * Number of left-shifts required to align most-sig 11 bits of 16-bit - * data value into COPROC field of immediate-mode NPE instruction - */ -#define IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA \ - (IX_NPEDL_OFFSET_INSTR_COPROC - IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA) - -/** - * LDUR value used with immediate-mode NPE Instructions by the NpeDl - * for writing to NPE internal logical registers - */ -#define IX_NPEDL_WR_INSTR_LDUR 1 - -/** - * LDUR value used with NON-immediate-mode NPE Instructions by the NpeDl - * for reading from NPE internal logical registers - */ -#define IX_NPEDL_RD_INSTR_LDUR 0 - - -/** - * NPE internal Context Store registers. - */ -typedef enum -{ - IX_NPEDL_CTXT_REG_STEVT = 0, /**< identifies STEVT */ - IX_NPEDL_CTXT_REG_STARTPC, /**< identifies STARTPC */ - IX_NPEDL_CTXT_REG_REGMAP, /**< identifies REGMAP */ - IX_NPEDL_CTXT_REG_CINDEX, /**< identifies CINDEX */ - IX_NPEDL_CTXT_REG_MAX /**< Total number of Context Store registers */ -} IxNpeDlCtxtRegNum; - - -/* - * NPE Context Store register logical addresses - */ -#define IX_NPEDL_CTXT_REG_ADDR_STEVT 0x0000001B -#define IX_NPEDL_CTXT_REG_ADDR_STARTPC 0x0000001C -#define IX_NPEDL_CTXT_REG_ADDR_REGMAP 0x0000001E -#define IX_NPEDL_CTXT_REG_ADDR_CINDEX 0x0000001F - -/* - * NPE Context Store register reset values - */ - -/** - * Reset value of STEVT NPE internal Context Store register - * (STEVT = off, 0x80) - */ -#define IX_NPEDL_CTXT_REG_RESET_STEVT 0x80 - -/** - * Reset value of STARTPC NPE internal Context Store register - * (STARTPC = 0x0000) - */ -#define IX_NPEDL_CTXT_REG_RESET_STARTPC 0x0000 - -/** - * Reset value of REGMAP NPE internal Context Store register - * (REGMAP = d0->p0, d8->p2, d16->p4) - */ -#define IX_NPEDL_CTXT_REG_RESET_REGMAP 0x0820 - -/** - * Reset value of CINDEX NPE internal Context Store register - * (CINDEX = 0) - */ -#define IX_NPEDL_CTXT_REG_RESET_CINDEX 0x00 - - -/* - * Numeric range of context levels available on an NPE - */ -#define IX_NPEDL_CTXT_NUM_MIN 0 -#define IX_NPEDL_CTXT_NUM_MAX 15 - - -/** - * Number of Physical registers currently supported - * Initial NPE implementations will have a 32-word register file. - * Later implementations may have a 64-word register file. - */ -#define IX_NPEDL_TOTAL_NUM_PHYS_REG 32 - -/** - * LSB-offset of Regmap number in Physical NPE register address, used - * for Physical To Logical register address mapping in the NPE - */ -#define IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP 1 - -/** - * Mask to extract a logical NPE register address from a physical - * register address, used for Physical To Logical address mapping - */ -#define IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR 0x1 - -/* - * NPE Message/Mailbox interface. - */ -#define IX_NPESTAT IX_NPEDL_REG_OFFSET_STAT /* status register */ -#define IX_NPECTL IX_NPEDL_REG_OFFSET_CTL /* control register */ -#define IX_NPEFIFO IX_NPEDL_REG_OFFSET_FIFO /* FIFO register */ - -/* control register */ -#define IX_NPECTL_OFE 0x00010000 /* output fifo enable */ -#define IX_NPECTL_IFE 0x00020000 /* input fifo enable */ -#define IX_NPECTL_OFWE 0x01000000 /* output fifo write enable */ -#define IX_NPECTL_IFWE 0x02000000 /* input fifo write enable */ - -/* status register */ -#define IX_NPESTAT_OFNE 0x00010000 /* output fifo not empty */ -#define IX_NPESTAT_IFNF 0x00020000 /* input fifo not full */ -#define IX_NPESTAT_OFNF 0x00040000 /* output fifo not full */ -#define IX_NPESTAT_IFNE 0x00080000 /* input fifo not empty */ -#define IX_NPESTAT_MBINT 0x00100000 /* Mailbox interrupt */ -#define IX_NPESTAT_IFINT 0x00200000 /* input fifo interrupt */ -#define IX_NPESTAT_OFINT 0x00400000 /* output fifo interrupt */ -#define IX_NPESTAT_WFINT 0x00800000 /* watch fifo interrupt */ -#endif /* _IXP425_NPEREG_H_ */ diff --git a/sys/arm/xscale/ixp425/ixp425_npevar.h b/sys/arm/xscale/ixp425/ixp425_npevar.h deleted file mode 100644 index 6c473c4af1ab..000000000000 --- a/sys/arm/xscale/ixp425/ixp425_npevar.h +++ /dev/null @@ -1,124 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 Sam Leffler. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#ifndef _IXP425_NPEVAR_H_ -#define _IXP425_NPEVAR_H_ - -/* - * Intel (R) IXP400 Software NPE Image ID Definition - * - * Firmware Id's for current firmware image. These are typed by - * NPE ID and the feature set. Not all features are available - * on all NPE's. The Image ID has the following structure: - * - * Field [Bit Location] - * ----------------------------------- - * Device ID [28..31] - * NPE ID [24..27] - * NPE Functionality ID [16..23] - * Major Release Number [8..15] - * Minor Release Number [0..7] - * - * The following "feature sets" are known to exist: - * - * HSS-0: supports 32 channelized and 4 packetized. - * HSS-0 + ATM + SPHY: - * For HSS, 16/32 channelized and 4/0 packetized. - * For ATM, AAL5, AAL0 and OAM for UTOPIA SPHY, 1 logical port, 32 VCs. - * Fast Path support. - * HSS-0 + ATM + MPHY: - * For HSS, 16/32 channelized and 4/0 packetized. - * For ATM, AAL5, AAL0 and OAM for UTOPIA MPHY, 1 logical port, 32 VCs. - * Fast Path support. - * ATM-Only: - * AAL5, AAL0 and OAM for UTOPIA MPHY, 12 logical ports, 32 VCs. - * Fast Path support. - * HSS-2: - * HSS-0 and HSS-1. - * Each HSS port supports 32 channelized and 4 packetized. - * ETH: Ethernet Rx/Tx which includes: - * MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL - * ETH+VLAN Ethernet Rx/Tx which includes: - * MAC_FILTERING, MAC_LEARNING, SPANNING_TREE, FIREWALL, VLAN_QOS - * ETH+VLAN+HDR: Ethernet Rx/Tx which includes: - * SPANNING_TREE, FIREWALL, VLAN_QOS, HEADER_CONVERSION - */ -#define NPEIMAGE_DEVID(id) (((id) >> 28) & 0xf) -#define NPEIMAGE_NPEID(id) (((id) >> 24) & 0xf) -#define NPEIMAGE_FUNCID(id) (((id) >> 16) & 0xff) -#define NPEIMAGE_MAJOR(id) (((id) >> 8) & 0xff) -#define NPEIMAGE_MINOR(id) (((id) >> 0) & 0xff) -#define NPEIMAGE_MAKEID(dev, npe, func, maj, min) \ - ((((dev) & 0xf) << 28) | (((npe) & 0xf) << 24) | \ - (((func) & 0xff) << 16) (((maj) & 0xff) << 8) | (((min) & 0xff) << 0)) - -/* XXX not right, revise */ -/* NPE A Firmware Image Id's */ -#define NPEFW_A_HSS0 0x00010000 /* HSS-0: 32 chan+4 packet */ -#define NPEFW_A_HSS0_ATM_S_1 0x00020000 /* HSS-0+ATM UTOPIA SPHY (1 port) */ -#define NPEFW_A_HSS0_ATM_M_1 0x00020000 /* HSS-0+ATM UTOPIA MPHY (1 port) */ -#define NPEFW_A_ATM_M_12 0x00040000 /* ATM UTOPIA MPHY (12 ports) */ -#define NPEFW_A_DMA 0x00150100 /* DMA only */ -#define NPEFW_A_HSS2 0x00090000 /* HSS-0 + HSS-1 */ -#define NPEFW_A_ETH 0x10800200 /* Basic Ethernet */ -#define NPEFW_A_ETH_VLAN 0x10810200 /* NPEFW_A_ETH + VLAN QoS */ -#define NPEFW_A_ETH_VLAN_HDR 0x10820200 /* NPEFW_A_ETH_VLAN + Hdr conv */ -/* XXX ... more not included */ - -/* NPE B Firmware Image Id's */ -#define NPEFW_B_ETH 0x01000200 /* Basic Ethernet */ -#define NPEFW_B_ETH_VLAN 0x01010200 /* NPEFW_B_ETH + VLAN QoS */ -#define NPEFW_B_ETH_VLAN_HDR 0x01020201 /* NPEFW_B_ETH_VLAN + Hdr conv */ -#define NPEFW_B_DMA 0x01020100 /* DMA only */ -/* XXX ... more not include */ - -/* NPE ID's */ -#define NPE_A 0 -#define NPE_B 1 -#define NPE_C 2 -#define NPE_MAX (NPE_C+1) - -#define IXP425_NPE_A_IMAGEID 0x10820200 -#define IXP425_NPE_B_IMAGEID 0x01000201 -#define IXP425_NPE_C_IMAGEID 0x02000201 - -struct ixpnpe_softc; -struct ixpnpe_softc *ixpnpe_attach(device_t, int npeid); -void ixpnpe_detach(struct ixpnpe_softc *); -int ixpnpe_stopandreset(struct ixpnpe_softc *); -int ixpnpe_start(struct ixpnpe_softc *); -int ixpnpe_stop(struct ixpnpe_softc *); -int ixpnpe_init(struct ixpnpe_softc *); -int ixpnpe_getfunctionality(struct ixpnpe_softc *sc); - -int ixpnpe_sendmsg_async(struct ixpnpe_softc *, const uint32_t msg[2]); -int ixpnpe_recvmsg_async(struct ixpnpe_softc *, uint32_t msg[2]); -int ixpnpe_sendandrecvmsg_sync(struct ixpnpe_softc *, - const uint32_t send[2], uint32_t recv[2]); -int ixpnpe_recvmsg_sync(struct ixpnpe_softc *, uint32_t msg[2]); -#endif /* _IXP425_NPEVAR_H_ */ diff --git a/sys/arm/xscale/ixp425/ixp425_pci.c b/sys/arm/xscale/ixp425/ixp425_pci.c deleted file mode 100644 index 9811bd8feb28..000000000000 --- a/sys/arm/xscale/ixp425/ixp425_pci.c +++ /dev/null @@ -1,477 +0,0 @@ -/* $NetBSD: ixp425_pci.c,v 1.6 2009/10/21 14:15:50 rmind Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-2-Clause-NetBSD - * - * Copyright (c) 2003 - * Ichiro FUKUHARA . - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#define _ARM32_BUS_DMA_PRIVATE -#include -#include -#include -#include - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include -#include "pcib_if.h" - -#include -extern struct ixp425_softc *ixp425_softc; - -#define PCI_CSR_WRITE_4(sc, reg, data) \ - bus_write_4(sc->sc_csr, reg, data) - -#define PCI_CSR_READ_4(sc, reg) \ - bus_read_4(sc->sc_csr, reg) - -#define PCI_CONF_LOCK(s) (s) = disable_interrupts(PSR_I) -#define PCI_CONF_UNLOCK(s) restore_interrupts((s)) - -static device_probe_t ixppcib_probe; -static device_attach_t ixppcib_attach; -static bus_read_ivar_t ixppcib_read_ivar; -static bus_write_ivar_t ixppcib_write_ivar; -static bus_setup_intr_t ixppcib_setup_intr; -static bus_teardown_intr_t ixppcib_teardown_intr; -static bus_alloc_resource_t ixppcib_alloc_resource; -static bus_activate_resource_t ixppcib_activate_resource; -static bus_deactivate_resource_t ixppcib_deactivate_resource; -static bus_release_resource_t ixppcib_release_resource; -static pcib_maxslots_t ixppcib_maxslots; -static pcib_read_config_t ixppcib_read_config; -static pcib_write_config_t ixppcib_write_config; -static pcib_route_interrupt_t ixppcib_route_interrupt; - -static int -ixppcib_probe(device_t dev) -{ - device_set_desc(dev, "IXP4XX PCI Bus"); - return (0); -} - -static void -ixp425_pci_conf_reg_write(struct ixppcib_softc *sc, uint32_t reg, - uint32_t data) -{ - PCI_CSR_WRITE_4(sc, PCI_CRP_AD_CBE, ((reg & ~3) | COMMAND_CRP_WRITE)); - PCI_CSR_WRITE_4(sc, PCI_CRP_AD_WDATA, data); -} - -static int -ixppcib_attach(device_t dev) -{ - int rid; - struct ixppcib_softc *sc; - - sc = device_get_softc(dev); - - rid = 0; - sc->sc_csr = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, - IXP425_PCI_HWBASE, IXP425_PCI_HWBASE + IXP425_PCI_SIZE, - IXP425_PCI_SIZE, RF_ACTIVE); - if (sc->sc_csr == NULL) - panic("cannot allocate PCI CSR registers"); - - ixp425_md_attach(dev); - /* always setup the base, incase another OS messes w/ it */ - PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b); - - rid = 0; - sc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, - IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE, - IXP425_PCI_MEM_SIZE, RF_ACTIVE); - if (sc->sc_mem == NULL) - panic("cannot allocate PCI MEM space"); - - /* NB: PCI dma window is 64M so anything above must be bounced */ - if (bus_dma_tag_create(NULL, 1, 0, IXP425_AHB_OFFSET + 64 * 1024 * 1024, - BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0, - NULL, NULL, &sc->sc_dmat)) - panic("couldn't create the PCI dma tag !"); - /* - * Initialize the bus space tags. - */ - ixp425_io_bs_init(&sc->sc_pci_iot, sc); - ixp425_mem_bs_init(&sc->sc_pci_memt, sc); - - sc->sc_dev = dev; - - /* Initialize memory and i/o rmans. */ - sc->sc_io_rman.rm_type = RMAN_ARRAY; - sc->sc_io_rman.rm_descr = "IXP4XX PCI I/O Ports"; - if (rman_init(&sc->sc_io_rman) != 0 || - rman_manage_region(&sc->sc_io_rman, 0, - IXP425_PCI_IO_SIZE) != 0) { - panic("ixppcib_probe: failed to set up I/O rman"); - } - - sc->sc_mem_rman.rm_type = RMAN_ARRAY; - sc->sc_mem_rman.rm_descr = "IXP4XX PCI Memory"; - if (rman_init(&sc->sc_mem_rman) != 0 || - rman_manage_region(&sc->sc_mem_rman, IXP425_PCI_MEM_HWBASE, - IXP425_PCI_MEM_HWBASE + IXP425_PCI_MEM_SIZE) != 0) { - panic("ixppcib_probe: failed to set up memory rman"); - } - - /* - * PCI->AHB address translation - * begin at the physical memory start + OFFSET - */ - PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE, - (IXP425_AHB_OFFSET & 0xFF000000) + - ((IXP425_AHB_OFFSET & 0xFF000000) >> 8) + - ((IXP425_AHB_OFFSET & 0xFF000000) >> 16) + - ((IXP425_AHB_OFFSET & 0xFF000000) >> 24) + - 0x00010203); - -#define IXPPCIB_WRITE_CONF(sc, reg, val) \ - ixp425_pci_conf_reg_write(sc, reg, val) - /* Write Mapping registers PCI Configuration Registers */ - /* Base Address 0 - 3 */ - IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR0, IXP425_AHB_OFFSET + 0x00000000); - IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR1, IXP425_AHB_OFFSET + 0x01000000); - IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR2, IXP425_AHB_OFFSET + 0x02000000); - IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR3, IXP425_AHB_OFFSET + 0x03000000); - - /* Base Address 4 */ - IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR4, 0xffffffff); - - /* Base Address 5 */ - IXPPCIB_WRITE_CONF(sc, PCI_MAPREG_BAR5, 0x00000000); - - /* Assert some PCI errors */ - PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE); - -#ifdef __ARMEB__ - /* - * Set up byte lane swapping between little-endian PCI - * and the big-endian AHB bus - */ - PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS); -#else - PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE); -#endif - - /* - * Enable bus mastering and I/O,memory access - */ - IXPPCIB_WRITE_CONF(sc, PCIR_COMMAND, - PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); - - /* - * Wait some more to ensure PCI devices have stabilised. - */ - DELAY(50000); - - device_add_child(dev, "pci", -1); - return (bus_generic_attach(dev)); -} - -static int -ixppcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) -{ - struct ixppcib_softc *sc; - - sc = device_get_softc(dev); - switch (which) { - case PCIB_IVAR_DOMAIN: - *result = 0; - return (0); - case PCIB_IVAR_BUS: - *result = sc->sc_bus; - return (0); - } - - return (ENOENT); -} - -static int -ixppcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) -{ - struct ixppcib_softc *sc; - - sc = device_get_softc(dev); - switch (which) { - case PCIB_IVAR_DOMAIN: - return (EINVAL); - case PCIB_IVAR_BUS: - sc->sc_bus = value; - return (0); - } - - return (ENOENT); -} - -static int -ixppcib_setup_intr(device_t dev, device_t child, struct resource *ires, - int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, - void **cookiep) -{ - - return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, - filt, intr, arg, cookiep)); -} - -static int -ixppcib_teardown_intr(device_t dev, device_t child, struct resource *vec, - void *cookie) -{ - - return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, vec, cookie)); -} - -static struct resource * -ixppcib_alloc_resource(device_t bus, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ - struct ixppcib_softc *sc = device_get_softc(bus); - struct rman *rmanp; - struct resource *rv; - - rv = NULL; - switch (type) { - case SYS_RES_IRQ: - rmanp = &sc->sc_irq_rman; - break; - - case SYS_RES_IOPORT: - rmanp = &sc->sc_io_rman; - break; - - case SYS_RES_MEMORY: - rmanp = &sc->sc_mem_rman; - break; - - default: - return (rv); - } - - rv = rman_reserve_resource(rmanp, start, end, count, flags & ~RF_ACTIVE, - child); - if (rv == NULL) - return (NULL); - rman_set_rid(rv, *rid); - if (flags & RF_ACTIVE) { - if (bus_activate_resource(child, type, *rid, rv)) { - rman_release_resource(rv); - return (NULL); - } - } - - return (rv); -} - -static int -ixppcib_activate_resource(device_t bus, device_t child, int type, int rid, - struct resource *r) -{ - struct ixppcib_softc *sc = device_get_softc(bus); - int error; - - error = rman_activate_resource(r); - if (error) - return (error); - switch (type) { - case SYS_RES_IOPORT: - rman_set_bustag(r, &sc->sc_pci_iot); - rman_set_bushandle(r, rman_get_start(r)); - break; - case SYS_RES_MEMORY: - rman_set_bustag(r, &sc->sc_pci_memt); - rman_set_bushandle(r, rman_get_bushandle(sc->sc_mem) + - (rman_get_start(r) - IXP425_PCI_MEM_HWBASE)); - break; - } - - return (0); -} - -static int -ixppcib_deactivate_resource(device_t bus, device_t child, int type, int rid, - struct resource *r) -{ - - device_printf(bus, "%s called deactivate_resource (unexpected)\n", - device_get_nameunit(child)); - return (ENXIO); -} - -static int -ixppcib_release_resource(device_t bus, device_t child, int type, int rid, - struct resource *r) -{ - - device_printf(bus, "%s called release_resource (unexpected)\n", - device_get_nameunit(child)); - return (ENXIO); -} - -static bus_dma_tag_t -ixppcib_get_dma_tag(device_t bus, device_t child) -{ - struct ixppcib_softc *sc = device_get_softc(bus); - - return (sc->sc_dmat); -} - -static void -ixppcib_conf_setup(struct ixppcib_softc *sc, int bus, int slot, int func, - int reg) -{ - if (bus == 0) { - /* configuration type 0 */ - PCI_CSR_WRITE_4(sc, PCI_NP_AD, - (1U << (32 - (slot & 0x1f))) | - ((func & 0x7) << 8) | (reg & ~3)); - } else { - /* configuration type 1 */ - PCI_CSR_WRITE_4(sc, PCI_NP_AD, - (bus << 16) | (slot << 11) | - (func << 8) | (reg & ~3) | 1); - } - -} - -static int -ixppcib_maxslots(device_t dev) -{ - - return (PCI_SLOTMAX); -} - -static u_int32_t -ixppcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, - int bytes) -{ - struct ixppcib_softc *sc = device_get_softc(dev); - u_int32_t data, ret; - - ixppcib_conf_setup(sc, bus, slot, func, reg & ~3); - - PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_READ); - ret = PCI_CSR_READ_4(sc, PCI_NP_RDATA); - ret >>= (reg & 3) * 8; - ret &= 0xffffffff >> ((4 - bytes) * 8); -#if 0 - device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n", - __func__, bus, slot, func, reg, bytes, ret); -#endif - /* check & clear PCI abort */ - data = PCI_CSR_READ_4(sc, PCI_ISR); - if (data & ISR_PFE) { - PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE); - return (-1); - } - return (ret); -} - -static const int byteenables[] = { 0, 0x10, 0x30, 0x70, 0xf0 }; - -static void -ixppcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, - u_int32_t val, int bytes) -{ - struct ixppcib_softc *sc = device_get_softc(dev); - u_int32_t data; - -#if 0 - device_printf(dev, "%s: %u:%u:%u %#x(%d) = %#x\n", - __func__, bus, slot, func, reg, bytes, val); -#endif - ixppcib_conf_setup(sc, bus, slot, func, reg & ~3); - - /* Byte enables are active low, so not them first */ - PCI_CSR_WRITE_4(sc, PCI_NP_CBE, COMMAND_NP_CONF_WRITE | - (~(byteenables[bytes] << (reg & 3)) & 0xf0)); - PCI_CSR_WRITE_4(sc, PCI_NP_WDATA, val << ((reg & 3) * 8)); - - /* check & clear PCI abort */ - data = PCI_CSR_READ_4(sc, PCI_ISR); - if (data & ISR_PFE) - PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_PFE); -} - -static int -ixppcib_route_interrupt(device_t bridge, device_t device, int pin) -{ - - return (ixp425_md_route_interrupt(bridge, device, pin)); -} - -static device_method_t ixppcib_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, ixppcib_probe), - DEVMETHOD(device_attach, ixppcib_attach), - - /* Bus interface */ - DEVMETHOD(bus_read_ivar, ixppcib_read_ivar), - DEVMETHOD(bus_write_ivar, ixppcib_write_ivar), - DEVMETHOD(bus_setup_intr, ixppcib_setup_intr), - DEVMETHOD(bus_teardown_intr, ixppcib_teardown_intr), - DEVMETHOD(bus_alloc_resource, ixppcib_alloc_resource), - DEVMETHOD(bus_activate_resource, ixppcib_activate_resource), - DEVMETHOD(bus_deactivate_resource, ixppcib_deactivate_resource), - DEVMETHOD(bus_release_resource, ixppcib_release_resource), - DEVMETHOD(bus_get_dma_tag, ixppcib_get_dma_tag), - - /* pcib interface */ - DEVMETHOD(pcib_maxslots, ixppcib_maxslots), - DEVMETHOD(pcib_read_config, ixppcib_read_config), - DEVMETHOD(pcib_write_config, ixppcib_write_config), - DEVMETHOD(pcib_route_interrupt, ixppcib_route_interrupt), - DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), - - DEVMETHOD_END -}; - -static driver_t ixppcib_driver = { - "pcib", - ixppcib_methods, - sizeof(struct ixppcib_softc), -}; -static devclass_t ixppcib_devclass; - -DRIVER_MODULE(ixppcib, ixp, ixppcib_driver, ixppcib_devclass, 0, 0); diff --git a/sys/arm/xscale/ixp425/ixp425_pci_asm.S b/sys/arm/xscale/ixp425/ixp425_pci_asm.S deleted file mode 100644 index ce668a3e3c84..000000000000 --- a/sys/arm/xscale/ixp425/ixp425_pci_asm.S +++ /dev/null @@ -1,108 +0,0 @@ -/* $NetBSD: ixp425_pci_asm.S,v 1.2 2005/12/11 12:16:51 christos Exp $ */ - -/* - * Copyright (c) 2003 Wasabi Systems, Inc. - * All rights reserved. - * - * Written by Jason R. Thorpe for Wasabi Systems, Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed for the NetBSD Project by - * Wasabi Systems, Inc. - * 4. The name of Wasabi Systems, Inc. may not be used to endorse - * or promote products derived from this software without specific prior - * written permission. - * - * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -#include - -/* - * Bus space functions for IXP425 PCI space access. We have to swizzle - * the address for 1 and 2 byte accesses when in big-endian mode. - */ - -/* - * read single - */ - -ENTRY(ixp425_pci_mem_bs_r_1) -#ifdef __ARMEB__ - add r1, r1, r2 - eor r1, r1, #0x3 - ldrb r0, [r1] -#else - ldrb r0, [r1, r2] -#endif /* __ARMEB__ */ - mov pc, lr -END(ixp425_pci_mem_bs_r_1) - -ENTRY(ixp425_pci_mem_bs_r_2) -#ifdef __ARMEB__ - add r1, r1, r2 - eor r1, r1, #0x2 - ldrh r0, [r1] -#else - ldrh r0, [r1, r2] -#endif /* __ARMEB__ */ - mov pc, lr -END(ixp425_pci_mem_bs_r_2) - -ENTRY(ixp425_pci_mem_bs_r_4) - ldr r0, [r1, r2] - mov pc, lr -END(ixp425_pci_mem_bs_r_4) - -/* - * write single - */ - -ENTRY(ixp425_pci_mem_bs_w_1) -#ifdef __ARMEB__ - add r1, r1, r2 - eor r1, r1, #0x3 - strb r3, [r1] -#else - strb r3, [r1, r2] -#endif /* __ARMEB__ */ - mov pc, lr -END(ixp425_pci_mem_bs_w_1) - -ENTRY(ixp425_pci_mem_bs_w_2) -#ifdef __ARMEB__ - add r1, r1, r2 - eor r1, r1, #0x2 - strh r3, [r1] -#else - strh r3, [r1, r2] -#endif /* __ARMEB__ */ - mov pc, lr -END(ixp425_pci_mem_bs_w_2) - -ENTRY(ixp425_pci_mem_bs_w_4) - str r3, [r1, r2] - mov pc, lr -END(ixp425_pci_mem_bs_w_4) diff --git a/sys/arm/xscale/ixp425/ixp425_pci_space.c b/sys/arm/xscale/ixp425/ixp425_pci_space.c deleted file mode 100644 index d1680dc22f63..000000000000 --- a/sys/arm/xscale/ixp425/ixp425_pci_space.c +++ /dev/null @@ -1,481 +0,0 @@ -/* $NetBSD: ixp425_pci_space.c,v 1.7 2009/10/21 14:15:51 rmind Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-2-Clause-NetBSD - * - * Copyright (c) 2003 - * Ichiro FUKUHARA . - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -/* - * bus_space PCI functions for ixp425 - */ - -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include - -#include - -#include -#include - -/* - * Macros to read/write registers -*/ -#define CSR_READ_4(x) *(volatile uint32_t *) \ - (IXP425_PCI_CSR_BASE + (x)) -#define CSR_WRITE_4(x, v) *(volatile uint32_t *) \ - (IXP425_PCI_CSR_BASE + (x)) = (v) - -/* Proto types for all the bus_space structure functions */ -bs_protos(ixp425_pci); -bs_protos(ixp425_pci_io); -bs_protos(ixp425_pci_mem); - -/* special I/O functions */ -static u_int8_t _pci_io_bs_r_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); -static u_int16_t _pci_io_bs_r_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); -static u_int32_t _pci_io_bs_r_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); - -static void _pci_io_bs_w_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int8_t); -static void _pci_io_bs_w_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int16_t); -static void _pci_io_bs_w_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int32_t); - -#ifdef __ARMEB__ -static u_int8_t _pci_io_bs_r_1_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); -static u_int16_t _pci_io_bs_r_2_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); -static u_int32_t _pci_io_bs_r_4_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); - -static void _pci_io_bs_w_1_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int8_t); -static void _pci_io_bs_w_2_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int16_t); -static void _pci_io_bs_w_4_s(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int32_t); - -static u_int8_t _pci_mem_bs_r_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); -static u_int16_t _pci_mem_bs_r_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); -static u_int32_t _pci_mem_bs_r_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); - -static void _pci_mem_bs_w_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int8_t); -static void _pci_mem_bs_w_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int16_t); -static void _pci_mem_bs_w_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int32_t); -#endif - -struct bus_space ixp425_pci_io_bs_tag_template = { - /* mapping/unmapping */ - .bs_map = ixp425_pci_io_bs_map, - .bs_unmap = ixp425_pci_io_bs_unmap, - .bs_subregion = ixp425_pci_bs_subregion, - - .bs_alloc = ixp425_pci_io_bs_alloc, - .bs_free = ixp425_pci_io_bs_free, - - /* barrier */ - .bs_barrier = ixp425_pci_bs_barrier, - - /* - * IXP425 processor does not have PCI I/O windows - */ - /* read (single) */ - .bs_r_1 = _pci_io_bs_r_1, - .bs_r_2 = _pci_io_bs_r_2, - .bs_r_4 = _pci_io_bs_r_4, - - /* write (single) */ - .bs_w_1 = _pci_io_bs_w_1, - .bs_w_2 = _pci_io_bs_w_2, - .bs_w_4 = _pci_io_bs_w_4, - -#ifdef __ARMEB__ - .bs_r_1_s = _pci_io_bs_r_1_s, - .bs_r_2_s = _pci_io_bs_r_2_s, - .bs_r_4_s = _pci_io_bs_r_4_s, - - .bs_w_1_s = _pci_io_bs_w_1_s, - .bs_w_2_s = _pci_io_bs_w_2_s, - .bs_w_4_s = _pci_io_bs_w_4_s, -#else - .bs_r_1_s = _pci_io_bs_r_1, - .bs_r_2_s = _pci_io_bs_r_2, - .bs_r_4_s = _pci_io_bs_r_4, - - .bs_w_1_s = _pci_io_bs_w_1, - .bs_w_2_s = _pci_io_bs_w_2, - .bs_w_4_s = _pci_io_bs_w_4, -#endif -}; - -void -ixp425_io_bs_init(bus_space_tag_t bs, void *cookie) -{ - *bs = ixp425_pci_io_bs_tag_template; - bs->bs_privdata = cookie; -} - -struct bus_space ixp425_pci_mem_bs_tag_template = { - /* mapping/unmapping */ - .bs_map = ixp425_pci_mem_bs_map, - .bs_unmap = ixp425_pci_mem_bs_unmap, - .bs_subregion = ixp425_pci_bs_subregion, - - .bs_alloc = ixp425_pci_mem_bs_alloc, - .bs_free = ixp425_pci_mem_bs_free, - - /* barrier */ - .bs_barrier = ixp425_pci_bs_barrier, - -#ifdef __ARMEB__ - /* read (single) */ - .bs_r_1_s = _pci_mem_bs_r_1, - .bs_r_2_s = _pci_mem_bs_r_2, - .bs_r_4_s = _pci_mem_bs_r_4, - - .bs_r_1 = ixp425_pci_mem_bs_r_1, - .bs_r_2 = ixp425_pci_mem_bs_r_2, - .bs_r_4 = ixp425_pci_mem_bs_r_4, - - /* write (single) */ - .bs_w_1_s = _pci_mem_bs_w_1, - .bs_w_2_s = _pci_mem_bs_w_2, - .bs_w_4_s = _pci_mem_bs_w_4, - - .bs_w_1 = ixp425_pci_mem_bs_w_1, - .bs_w_2 = ixp425_pci_mem_bs_w_2, - .bs_w_4 = ixp425_pci_mem_bs_w_4, -#else - /* read (single) */ - .bs_r_1 = ixp425_pci_mem_bs_r_1, - .bs_r_2 = ixp425_pci_mem_bs_r_2, - .bs_r_4 = ixp425_pci_mem_bs_r_4, - .bs_r_1_s = ixp425_pci_mem_bs_r_1, - .bs_r_2_s = ixp425_pci_mem_bs_r_2, - .bs_r_4_s = ixp425_pci_mem_bs_r_4, - - /* write (single) */ - .bs_w_1 = ixp425_pci_mem_bs_w_1, - .bs_w_2 = ixp425_pci_mem_bs_w_2, - .bs_w_4 = ixp425_pci_mem_bs_w_4, - .bs_w_1_s = ixp425_pci_mem_bs_w_1, - .bs_w_2_s = ixp425_pci_mem_bs_w_2, - .bs_w_4_s = ixp425_pci_mem_bs_w_4, -#endif -}; - -void -ixp425_mem_bs_init(bus_space_tag_t bs, void *cookie) -{ - *bs = ixp425_pci_mem_bs_tag_template; - bs->bs_privdata = cookie; -} - -/* common routine */ -int -ixp425_pci_bs_subregion(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset, - bus_size_t size, bus_space_handle_t *nbshp) -{ - *nbshp = bsh + offset; - return (0); -} - -void -ixp425_pci_bs_barrier(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset, - bus_size_t len, int flags) -{ - /* NULL */ -} - -/* io bs */ -int -ixp425_pci_io_bs_map(bus_space_tag_t tag, bus_addr_t bpa, bus_size_t size, - int cacheable, bus_space_handle_t *bshp) -{ - *bshp = bpa; - return (0); -} - -void -ixp425_pci_io_bs_unmap(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t size) -{ - /* Nothing to do. */ -} - -int -ixp425_pci_io_bs_alloc(bus_space_tag_t tag, bus_addr_t rstart, bus_addr_t rend, - bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable, - bus_addr_t *bpap, bus_space_handle_t *bshp) -{ - panic("ixp425_pci_io_bs_alloc(): not implemented\n"); -} - -void -ixp425_pci_io_bs_free(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t size) -{ - panic("ixp425_pci_io_bs_free(): not implemented\n"); -} - -/* special I/O functions */ -static __inline u_int32_t -_bs_r(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, u_int32_t be) -{ - u_int32_t data; - - CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); - CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ); - data = CSR_READ_4(PCI_NP_RDATA); - if (CSR_READ_4(PCI_ISR) & ISR_PFE) - CSR_WRITE_4(PCI_ISR, ISR_PFE); - - return data; -} - -static u_int8_t -_pci_io_bs_r_1(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) -{ - u_int32_t data, n, be; - - n = (ioh + off) % 4; - be = (0xf & ~(1U << n)) << NP_CBE_SHIFT; - data = _bs_r(tag, ioh, off, be); - - return data >> (8 * n); -} - -static u_int16_t -_pci_io_bs_r_2(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) -{ - u_int32_t data, n, be; - - n = (ioh + off) % 4; - be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; - data = _bs_r(tag, ioh, off, be); - - return data >> (8 * n); -} - -static u_int32_t -_pci_io_bs_r_4(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) -{ - u_int32_t data; - - data = _bs_r(tag, ioh, off, 0); - return data; -} - -#ifdef __ARMEB__ -static u_int8_t -_pci_io_bs_r_1_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) -{ - u_int32_t data, n, be; - - n = (ioh + off) % 4; - be = (0xf & ~(1U << n)) << NP_CBE_SHIFT; - data = _bs_r(tag, ioh, off, be); - - return data >> (8 * n); -} - -static u_int16_t -_pci_io_bs_r_2_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) -{ - u_int32_t data, n, be; - - n = (ioh + off) % 4; - be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; - data = _bs_r(tag, ioh, off, be); - - return data >> (8 * n); -} - -static u_int32_t -_pci_io_bs_r_4_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) -{ - u_int32_t data; - - data = _bs_r(tag, ioh, off, 0); - return le32toh(data); -} -#endif /* __ARMEB__ */ - -static __inline void -_bs_w(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, - u_int32_t be, u_int32_t data) -{ - CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3); - CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE); - CSR_WRITE_4(PCI_NP_WDATA, data); - if (CSR_READ_4(PCI_ISR) & ISR_PFE) - CSR_WRITE_4(PCI_ISR, ISR_PFE); -} - -static void -_pci_io_bs_w_1(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, - u_int8_t val) -{ - u_int32_t data, n, be; - - n = (ioh + off) % 4; - be = (0xf & ~(1U << n)) << NP_CBE_SHIFT; - data = val << (8 * n); - _bs_w(tag, ioh, off, be, data); -} - -static void -_pci_io_bs_w_2(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, - u_int16_t val) -{ - u_int32_t data, n, be; - - n = (ioh + off) % 4; - be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; - data = val << (8 * n); - _bs_w(tag, ioh, off, be, data); -} - -static void -_pci_io_bs_w_4(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, - u_int32_t val) -{ - _bs_w(tag, ioh, off, 0, val); -} - -#ifdef __ARMEB__ -static void -_pci_io_bs_w_1_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, - u_int8_t val) -{ - u_int32_t data, n, be; - - n = (ioh + off) % 4; - be = (0xf & ~(1U << n)) << NP_CBE_SHIFT; - data = val << (8 * n); - _bs_w(tag, ioh, off, be, data); -} - -static void -_pci_io_bs_w_2_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, - u_int16_t val) -{ - u_int32_t data, n, be; - - n = (ioh + off) % 4; - be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT; - data = val << (8 * n); - _bs_w(tag, ioh, off, be, data); -} - -static void -_pci_io_bs_w_4_s(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, - u_int32_t val) -{ - _bs_w(tag, ioh, off, 0, htole32(val)); -} -#endif /* __ARMEB__ */ - -/* mem bs */ -int -ixp425_pci_mem_bs_map(bus_space_tag_t tag, bus_addr_t bpa, bus_size_t size, - int cacheable, bus_space_handle_t *bshp) -{ - *bshp = (vm_offset_t)pmap_mapdev(bpa, size); - return (0); -} - -void -ixp425_pci_mem_bs_unmap(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t size) -{ - - pmap_unmapdev((vm_offset_t)h, size); -} - -int -ixp425_pci_mem_bs_alloc(bus_space_tag_t tag, bus_addr_t rstart, bus_addr_t rend, - bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable, - bus_addr_t *bpap, bus_space_handle_t *bshp) -{ - panic("ixp425_mem_bs_alloc(): not implemented\n"); -} - -void -ixp425_pci_mem_bs_free(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t size) -{ - panic("ixp425_mem_bs_free(): not implemented\n"); -} - -#ifdef __ARMEB__ -static u_int8_t -_pci_mem_bs_r_1(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) -{ - return ixp425_pci_mem_bs_r_1(tag, ioh, off); -} - -static u_int16_t -_pci_mem_bs_r_2(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) -{ - return (ixp425_pci_mem_bs_r_2(tag, ioh, off)); -} - -static u_int32_t -_pci_mem_bs_r_4(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off) -{ - u_int32_t data; - - data = ixp425_pci_mem_bs_r_4(tag, ioh, off); - return (le32toh(data)); -} - -static void -_pci_mem_bs_w_1(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, - u_int8_t val) -{ - ixp425_pci_mem_bs_w_1(tag, ioh, off, val); -} - -static void -_pci_mem_bs_w_2(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, - u_int16_t val) -{ - ixp425_pci_mem_bs_w_2(tag, ioh, off, val); -} - -static void -_pci_mem_bs_w_4(bus_space_tag_t tag, bus_space_handle_t ioh, bus_size_t off, - u_int32_t val) -{ - ixp425_pci_mem_bs_w_4(tag, ioh, off, htole32(val)); -} -#endif /* __ARMEB__ */ - -/* End of ixp425_pci_space.c */ diff --git a/sys/arm/xscale/ixp425/ixp425_qmgr.c b/sys/arm/xscale/ixp425/ixp425_qmgr.c deleted file mode 100644 index 914c7c72c747..000000000000 --- a/sys/arm/xscale/ixp425/ixp425_qmgr.c +++ /dev/null @@ -1,1104 +0,0 @@ -/*- - * Copyright (c) 2006 Sam Leffler, Errno Consulting - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - */ - -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2001-2005, Intel Corporation. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. -*/ -#include -__FBSDID("$FreeBSD$"); - -/* - * Intel XScale Queue Manager support. - * - * Each IXP4XXX device has a hardware block that implements a priority - * queue manager that is shared between the XScale cpu and the backend - * devices (such as the NPE). Queues are accessed by reading/writing - * special memory locations. The queue contents are mapped into a shared - * SRAM region with entries managed in a circular buffer. The XScale - * processor can receive interrupts based on queue contents (a condition - * code determines when interrupts should be delivered). - * - * The code here basically replaces the qmgr class in the Intel Access - * Library (IAL). - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include - -/* - * State per AQM hw queue. - * This structure holds q configuration and dispatch state. - */ -struct qmgrInfo { - int qSizeInWords; /* queue size in words */ - - uint32_t qOflowStatBitMask; /* overflow status mask */ - int qWriteCount; /* queue write count */ - - bus_size_t qAccRegAddr; /* access register */ - bus_size_t qUOStatRegAddr; /* status register */ - bus_size_t qConfigRegAddr; /* config register */ - int qSizeInEntries; /* queue size in entries */ - - uint32_t qUflowStatBitMask; /* underflow status mask */ - int qReadCount; /* queue read count */ - - /* XXX union */ - uint32_t qStatRegAddr; - uint32_t qStatBitsOffset; - uint32_t qStat0BitMask; - uint32_t qStat1BitMask; - - uint32_t intRegCheckMask; /* interrupt reg check mask */ - void (*cb)(int, void *); /* callback function */ - void *cbarg; /* callback argument */ - int priority; /* dispatch priority */ -#if 0 - /* NB: needed only for A0 parts */ - u_int statusWordOffset; /* status word offset */ - uint32_t statusMask; /* status mask */ - uint32_t statusCheckValue; /* status check value */ -#endif -}; - -struct ixpqmgr_softc { - device_t sc_dev; - bus_space_tag_t sc_iot; - bus_space_handle_t sc_ioh; - - struct resource *sc_irq1; /* IRQ resource */ - void *sc_ih1; /* interrupt handler */ - int sc_rid1; /* resource id for irq */ - - struct resource *sc_irq2; - void *sc_ih2; - int sc_rid2; - - struct qmgrInfo qinfo[IX_QMGR_MAX_NUM_QUEUES]; - /* - * This array contains a list of queue identifiers ordered by - * priority. The table is split logically between queue - * identifiers 0-31 and 32-63. To optimize lookups bit masks - * are kept for the first-32 and last-32 q's. When the - * table needs to be rebuilt mark rebuildTable and it'll - * happen after the next interrupt. - */ - int priorityTable[IX_QMGR_MAX_NUM_QUEUES]; - uint32_t lowPriorityTableFirstHalfMask; - uint32_t uppPriorityTableFirstHalfMask; - int rebuildTable; /* rebuild priorityTable */ - - uint32_t aqmFreeSramAddress; /* SRAM free space */ -}; - -static int qmgr_debug; -SYSCTL_INT(_debug, OID_AUTO, qmgr, CTLFLAG_RWTUN, &qmgr_debug, - 0, "IXP4XX Q-Manager debug msgs"); -#define DPRINTF(dev, fmt, ...) do { \ - if (qmgr_debug) printf(fmt, __VA_ARGS__); \ -} while (0) -#define DPRINTFn(n, dev, fmt, ...) do { \ - if (qmgr_debug >= n) printf(fmt, __VA_ARGS__); \ -} while (0) - -static struct ixpqmgr_softc *ixpqmgr_sc = NULL; - -static void ixpqmgr_rebuild(struct ixpqmgr_softc *); -static void ixpqmgr_intr(void *); - -static void aqm_int_enable(struct ixpqmgr_softc *sc, int qId); -static void aqm_int_disable(struct ixpqmgr_softc *sc, int qId); -static void aqm_qcfg(struct ixpqmgr_softc *sc, int qId, u_int ne, u_int nf); -static void aqm_srcsel_write(struct ixpqmgr_softc *sc, int qId, int sourceId); -static void aqm_reset(struct ixpqmgr_softc *sc); - -static void -dummyCallback(int qId, void *arg) -{ - /* XXX complain */ -} - -static uint32_t -aqm_reg_read(struct ixpqmgr_softc *sc, bus_size_t off) -{ - DPRINTFn(9, sc->sc_dev, "%s(0x%x)\n", __func__, (int)off); - return bus_space_read_4(sc->sc_iot, sc->sc_ioh, off); -} - -static void -aqm_reg_write(struct ixpqmgr_softc *sc, bus_size_t off, uint32_t val) -{ - DPRINTFn(9, sc->sc_dev, "%s(0x%x, 0x%x)\n", __func__, (int)off, val); - bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val); -} - -static int -ixpqmgr_probe(device_t dev) -{ - device_set_desc(dev, "IXP4XX Q-Manager"); - return 0; -} - -static int -ixpqmgr_attach(device_t dev) -{ - struct ixpqmgr_softc *sc = device_get_softc(dev); - struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); - int i, err; - - ixpqmgr_sc = sc; - - sc->sc_dev = dev; - sc->sc_iot = sa->sc_iot; - if (bus_space_map(sc->sc_iot, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE, - 0, &sc->sc_ioh)) - panic("%s: Cannot map registers", device_get_name(dev)); - - /* NB: we only use the lower 32 q's */ - - /* Set up QMGR interrupts */ - sc->sc_rid1 = 0; - sc->sc_irq1 = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->sc_rid1, - IXP425_INT_QUE1_32, IXP425_INT_QUE1_32, 1, RF_ACTIVE); - sc->sc_rid2 = 1; - sc->sc_irq2 = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->sc_rid2, - IXP425_INT_QUE33_64, IXP425_INT_QUE33_64, 1, RF_ACTIVE); - - if (sc->sc_irq1 == NULL || sc->sc_irq2 == NULL) - panic("Unable to allocate the qmgr irqs.\n"); - - err = bus_setup_intr(dev, sc->sc_irq1, INTR_TYPE_NET | INTR_MPSAFE, - NULL, ixpqmgr_intr, NULL, &sc->sc_ih1); - if (err) { - device_printf(dev, "failed to set up qmgr irq=%d\n", - IXP425_INT_QUE1_32); - return (ENXIO); - } - err = bus_setup_intr(dev, sc->sc_irq2, INTR_TYPE_NET | INTR_MPSAFE, - NULL, ixpqmgr_intr, NULL, &sc->sc_ih2); - if (err) { - device_printf(dev, "failed to set up qmgr irq=%d\n", - IXP425_INT_QUE33_64); - return (ENXIO); - } - - /* NB: softc is pre-zero'd */ - for (i = 0; i < IX_QMGR_MAX_NUM_QUEUES; i++) { - struct qmgrInfo *qi = &sc->qinfo[i]; - - qi->cb = dummyCallback; - qi->priority = IX_QMGR_Q_PRIORITY_0; /* default priority */ - /* - * There are two interrupt registers, 32 bits each. One - * for the lower queues(0-31) and one for the upper - * queues(32-63). Therefore need to mod by 32 i.e the - * min upper queue identifier. - */ - qi->intRegCheckMask = (1<<(i%(IX_QMGR_MIN_QUEUPP_QID))); - - /* - * Register addresses and bit masks are calculated and - * stored here to optimize QRead, QWrite and QStatusGet - * functions. - */ - - /* AQM Queue access reg addresses, per queue */ - qi->qAccRegAddr = IX_QMGR_Q_ACCESS_ADDR_GET(i); - qi->qAccRegAddr = IX_QMGR_Q_ACCESS_ADDR_GET(i); - qi->qConfigRegAddr = IX_QMGR_Q_CONFIG_ADDR_GET(i); - - /* AQM Queue lower-group (0-31), only */ - if (i < IX_QMGR_MIN_QUEUPP_QID) { - /* AQM Q underflow/overflow status reg address, per queue */ - qi->qUOStatRegAddr = IX_QMGR_QUEUOSTAT0_OFFSET + - ((i / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD) * - sizeof(uint32_t)); - - /* AQM Q underflow status bit masks for status reg per queue */ - qi->qUflowStatBitMask = - (IX_QMGR_UNDERFLOW_BIT_OFFSET + 1) << - ((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) * - (32 / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD)); - - /* AQM Q overflow status bit masks for status reg, per queue */ - qi->qOflowStatBitMask = - (IX_QMGR_OVERFLOW_BIT_OFFSET + 1) << - ((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) * - (32 / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD)); - - /* AQM Q lower-group (0-31) status reg addresses, per queue */ - qi->qStatRegAddr = IX_QMGR_QUELOWSTAT0_OFFSET + - ((i / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) * - sizeof(uint32_t)); - - /* AQM Q lower-group (0-31) status register bit offset */ - qi->qStatBitsOffset = - (i & (IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD - 1)) * - (32 / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD); - } else { /* AQM Q upper-group (32-63), only */ - qi->qUOStatRegAddr = 0; /* XXX */ - - /* AQM Q upper-group (32-63) Nearly Empty status reg bitmasks */ - qi->qStat0BitMask = (1 << (i - IX_QMGR_MIN_QUEUPP_QID)); - - /* AQM Q upper-group (32-63) Full status register bitmasks */ - qi->qStat1BitMask = (1 << (i - IX_QMGR_MIN_QUEUPP_QID)); - } - } - - sc->aqmFreeSramAddress = 0x100; /* Q buffer space starts at 0x2100 */ - - ixpqmgr_rebuild(sc); /* build initial priority table */ - aqm_reset(sc); /* reset h/w */ - return (0); -} - -static int -ixpqmgr_detach(device_t dev) -{ - struct ixpqmgr_softc *sc = device_get_softc(dev); - - aqm_reset(sc); /* disable interrupts */ - bus_teardown_intr(dev, sc->sc_irq1, sc->sc_ih1); - bus_teardown_intr(dev, sc->sc_irq2, sc->sc_ih2); - bus_release_resource(dev, SYS_RES_IRQ, sc->sc_rid1, sc->sc_irq1); - bus_release_resource(dev, SYS_RES_IRQ, sc->sc_rid2, sc->sc_irq2); - bus_space_unmap(sc->sc_iot, sc->sc_ioh, IXP425_QMGR_SIZE); - return (0); -} - -int -ixpqmgr_qconfig(int qId, int qEntries, int ne, int nf, int srcSel, - qconfig_hand_t *cb, void *cbarg) -{ - struct ixpqmgr_softc *sc = ixpqmgr_sc; - struct qmgrInfo *qi = &sc->qinfo[qId]; - - DPRINTF(sc->sc_dev, "%s(%u, %u, %u, %u, %u, %p, %p)\n", - __func__, qId, qEntries, ne, nf, srcSel, cb, cbarg); - - /* NB: entry size is always 1 */ - qi->qSizeInWords = qEntries; - - qi->qReadCount = 0; - qi->qWriteCount = 0; - qi->qSizeInEntries = qEntries; /* XXX kept for code clarity */ - - if (cb == NULL) { - /* Reset to dummy callback */ - qi->cb = dummyCallback; - qi->cbarg = NULL; - } else { - qi->cb = cb; - qi->cbarg = cbarg; - } - - /* Write the config register; NB must be AFTER qinfo setup */ - aqm_qcfg(sc, qId, ne, nf); - /* - * Account for space just allocated to queue. - */ - sc->aqmFreeSramAddress += (qi->qSizeInWords * sizeof(uint32_t)); - - /* Set the interrupt source if this queue is in the range 0-31 */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - aqm_srcsel_write(sc, qId, srcSel); - - if (cb != NULL) /* Enable the interrupt */ - aqm_int_enable(sc, qId); - - sc->rebuildTable = TRUE; - - return 0; /* XXX */ -} - -int -ixpqmgr_qwrite(int qId, uint32_t entry) -{ - struct ixpqmgr_softc *sc = ixpqmgr_sc; - struct qmgrInfo *qi = &sc->qinfo[qId]; - - DPRINTFn(3, sc->sc_dev, "%s(%u, 0x%x) writeCount %u size %u\n", - __func__, qId, entry, qi->qWriteCount, qi->qSizeInEntries); - - /* write the entry */ - aqm_reg_write(sc, qi->qAccRegAddr, entry); - - /* NB: overflow is available for lower queues only */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) { - int qSize = qi->qSizeInEntries; - /* - * Increment the current number of entries in the queue - * and check for overflow . - */ - if (qi->qWriteCount++ == qSize) { /* check for overflow */ - uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr); - int qPtrs; - - /* - * Read the status twice because the status may - * not be immediately ready after the write operation - */ - if ((status & qi->qOflowStatBitMask) || - ((status = aqm_reg_read(sc, qi->qUOStatRegAddr)) & qi->qOflowStatBitMask)) { - /* - * The queue is full, clear the overflow status bit if set. - */ - aqm_reg_write(sc, qi->qUOStatRegAddr, - status & ~qi->qOflowStatBitMask); - qi->qWriteCount = qSize; - DPRINTFn(5, sc->sc_dev, - "%s(%u, 0x%x) Q full, overflow status cleared\n", - __func__, qId, entry); - return ENOSPC; - } - /* - * No overflow occurred : someone is draining the queue - * and the current counter needs to be - * updated from the current number of entries in the queue - */ - - /* calculate number of words in q */ - qPtrs = aqm_reg_read(sc, qi->qConfigRegAddr); - DPRINTFn(2, sc->sc_dev, - "%s(%u, 0x%x) Q full, no overflow status, qConfig 0x%x\n", - __func__, qId, entry, qPtrs); - qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f; - - if (qPtrs == 0) { - /* - * The queue may be full at the time of the - * snapshot. Next access will check - * the overflow status again. - */ - qi->qWriteCount = qSize; - } else { - /* convert the number of words to a number of entries */ - qi->qWriteCount = qPtrs & (qSize - 1); - } - } - } - return 0; -} - -int -ixpqmgr_qread(int qId, uint32_t *entry) -{ - struct ixpqmgr_softc *sc = ixpqmgr_sc; - struct qmgrInfo *qi = &sc->qinfo[qId]; - bus_size_t off = qi->qAccRegAddr; - - *entry = aqm_reg_read(sc, off); - - /* - * Reset the current read count : next access to the read function - * will force a underflow status check. - */ - qi->qReadCount = 0; - - /* Check if underflow occurred on the read */ - if (*entry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID) { - /* get the queue status */ - uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr); - - if (status & qi->qUflowStatBitMask) { /* clear underflow status */ - aqm_reg_write(sc, qi->qUOStatRegAddr, - status &~ qi->qUflowStatBitMask); - return ENOSPC; - } - } - return 0; -} - -int -ixpqmgr_qreadm(int qId, uint32_t n, uint32_t *p) -{ - struct ixpqmgr_softc *sc = ixpqmgr_sc; - struct qmgrInfo *qi = &sc->qinfo[qId]; - uint32_t entry; - bus_size_t off = qi->qAccRegAddr; - - entry = aqm_reg_read(sc, off); - while (--n) { - if (entry == 0) { - /* if we read a NULL entry, stop. We have underflowed */ - break; - } - *p++ = entry; /* store */ - entry = aqm_reg_read(sc, off); - } - *p = entry; - - /* - * Reset the current read count : next access to the read function - * will force a underflow status check. - */ - qi->qReadCount = 0; - - /* Check if underflow occurred on the read */ - if (entry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID) { - /* get the queue status */ - uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr); - - if (status & qi->qUflowStatBitMask) { /* clear underflow status */ - aqm_reg_write(sc, qi->qUOStatRegAddr, - status &~ qi->qUflowStatBitMask); - return ENOSPC; - } - } - return 0; -} - -uint32_t -ixpqmgr_getqstatus(int qId) -{ -#define QLOWSTATMASK \ - ((1 << (32 / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD)) - 1) - struct ixpqmgr_softc *sc = ixpqmgr_sc; - const struct qmgrInfo *qi = &sc->qinfo[qId]; - uint32_t status; - - if (qId < IX_QMGR_MIN_QUEUPP_QID) { - /* read the status of a queue in the range 0-31 */ - status = aqm_reg_read(sc, qi->qStatRegAddr); - - /* mask out the status bits relevant only to this queue */ - status = (status >> qi->qStatBitsOffset) & QLOWSTATMASK; - } else { /* read status of a queue in the range 32-63 */ - status = 0; - if (aqm_reg_read(sc, IX_QMGR_QUEUPPSTAT0_OFFSET)&qi->qStat0BitMask) - status |= IX_QMGR_Q_STATUS_NE_BIT_MASK; /* nearly empty */ - if (aqm_reg_read(sc, IX_QMGR_QUEUPPSTAT1_OFFSET)&qi->qStat1BitMask) - status |= IX_QMGR_Q_STATUS_F_BIT_MASK; /* full */ - } - return status; -#undef QLOWSTATMASK -} - -uint32_t -ixpqmgr_getqconfig(int qId) -{ - struct ixpqmgr_softc *sc = ixpqmgr_sc; - - return aqm_reg_read(sc, IX_QMGR_Q_CONFIG_ADDR_GET(qId)); -} - -void -ixpqmgr_dump(void) -{ - struct ixpqmgr_softc *sc = ixpqmgr_sc; - int i, a; - - /* status registers */ - printf("0x%04x: %08x %08x %08x %08x\n" - , 0x400 - , aqm_reg_read(sc, 0x400) - , aqm_reg_read(sc, 0x400+4) - , aqm_reg_read(sc, 0x400+8) - , aqm_reg_read(sc, 0x400+12) - ); - printf("0x%04x: %08x %08x %08x %08x\n" - , 0x410 - , aqm_reg_read(sc, 0x410) - , aqm_reg_read(sc, 0x410+4) - , aqm_reg_read(sc, 0x410+8) - , aqm_reg_read(sc, 0x410+12) - ); - printf("0x%04x: %08x %08x %08x %08x\n" - , 0x420 - , aqm_reg_read(sc, 0x420) - , aqm_reg_read(sc, 0x420+4) - , aqm_reg_read(sc, 0x420+8) - , aqm_reg_read(sc, 0x420+12) - ); - printf("0x%04x: %08x %08x %08x %08x\n" - , 0x430 - , aqm_reg_read(sc, 0x430) - , aqm_reg_read(sc, 0x430+4) - , aqm_reg_read(sc, 0x430+8) - , aqm_reg_read(sc, 0x430+12) - ); - /* q configuration registers */ - for (a = 0x2000; a < 0x20ff; a += 32) - printf("0x%04x: %08x %08x %08x %08x %08x %08x %08x %08x\n" - , a - , aqm_reg_read(sc, a) - , aqm_reg_read(sc, a+4) - , aqm_reg_read(sc, a+8) - , aqm_reg_read(sc, a+12) - , aqm_reg_read(sc, a+16) - , aqm_reg_read(sc, a+20) - , aqm_reg_read(sc, a+24) - , aqm_reg_read(sc, a+28) - ); - /* allocated SRAM */ - for (i = 0x100; i < sc->aqmFreeSramAddress; i += 32) { - a = 0x2000 + i; - printf("0x%04x: %08x %08x %08x %08x %08x %08x %08x %08x\n" - , a - , aqm_reg_read(sc, a) - , aqm_reg_read(sc, a+4) - , aqm_reg_read(sc, a+8) - , aqm_reg_read(sc, a+12) - , aqm_reg_read(sc, a+16) - , aqm_reg_read(sc, a+20) - , aqm_reg_read(sc, a+24) - , aqm_reg_read(sc, a+28) - ); - } - for (i = 0; i < 16; i++) { - printf("Q[%2d] config 0x%08x status 0x%02x " - "Q[%2d] config 0x%08x status 0x%02x\n" - , i, ixpqmgr_getqconfig(i), ixpqmgr_getqstatus(i) - , i+16, ixpqmgr_getqconfig(i+16), ixpqmgr_getqstatus(i+16) - ); - } -} - -void -ixpqmgr_notify_enable(int qId, int srcSel) -{ - struct ixpqmgr_softc *sc = ixpqmgr_sc; -#if 0 - /* Calculate the checkMask and checkValue for this q */ - aqm_calc_statuscheck(sc, qId, srcSel); -#endif - /* Set the interrupt source if this queue is in the range 0-31 */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - aqm_srcsel_write(sc, qId, srcSel); - - /* Enable the interrupt */ - aqm_int_enable(sc, qId); -} - -void -ixpqmgr_notify_disable(int qId) -{ - struct ixpqmgr_softc *sc = ixpqmgr_sc; - - aqm_int_disable(sc, qId); -} - -/* - * Rebuild the priority table used by the dispatcher. - */ -static void -ixpqmgr_rebuild(struct ixpqmgr_softc *sc) -{ - int q, pri; - int lowQuePriorityTableIndex, uppQuePriorityTableIndex; - struct qmgrInfo *qi; - - sc->lowPriorityTableFirstHalfMask = 0; - sc->uppPriorityTableFirstHalfMask = 0; - - lowQuePriorityTableIndex = 0; - uppQuePriorityTableIndex = 32; - for (pri = 0; pri < IX_QMGR_NUM_PRIORITY_LEVELS; pri++) { - /* low priority q's */ - for (q = 0; q < IX_QMGR_MIN_QUEUPP_QID; q++) { - qi = &sc->qinfo[q]; - if (qi->priority == pri) { - /* - * Build the priority table bitmask which match the - * queues of the first half of the priority table. - */ - if (lowQuePriorityTableIndex < 16) { - sc->lowPriorityTableFirstHalfMask |= - qi->intRegCheckMask; - } - sc->priorityTable[lowQuePriorityTableIndex++] = q; - } - } - /* high priority q's */ - for (; q < IX_QMGR_MAX_NUM_QUEUES; q++) { - qi = &sc->qinfo[q]; - if (qi->priority == pri) { - /* - * Build the priority table bitmask which match the - * queues of the first half of the priority table . - */ - if (uppQuePriorityTableIndex < 48) { - sc->uppPriorityTableFirstHalfMask |= - qi->intRegCheckMask; - } - sc->priorityTable[uppQuePriorityTableIndex++] = q; - } - } - } - sc->rebuildTable = FALSE; -} - -/* - * Count the number of leading zero bits in a word, - * and return the same value than the CLZ instruction. - * Note this is similar to the standard ffs function but - * it counts zero's from the MSB instead of the LSB. - * - * word (in) return value (out) - * 0x80000000 0 - * 0x40000000 1 - * ,,, ,,, - * 0x00000002 30 - * 0x00000001 31 - * 0x00000000 32 - * - * The C version of this function is used as a replacement - * for system not providing the equivalent of the CLZ - * assembly language instruction. - * - * Note that this version is big-endian - */ -static unsigned int -_lzcount(uint32_t word) -{ - unsigned int lzcount = 0; - - if (word == 0) - return 32; - while ((word & 0x80000000) == 0) { - word <<= 1; - lzcount++; - } - return lzcount; -} - -static void -ixpqmgr_intr(void *arg) -{ - struct ixpqmgr_softc *sc = ixpqmgr_sc; - uint32_t intRegVal; /* Interrupt reg val */ - struct qmgrInfo *qi; - int priorityTableIndex; /* Priority table index */ - int qIndex; /* Current queue being processed */ - - /* Read the interrupt register */ - intRegVal = aqm_reg_read(sc, IX_QMGR_QINTREG0_OFFSET); - /* Write back to clear interrupt */ - aqm_reg_write(sc, IX_QMGR_QINTREG0_OFFSET, intRegVal); - - DPRINTFn(5, sc->sc_dev, "%s: ISR0 0x%x ISR1 0x%x\n", - __func__, intRegVal, aqm_reg_read(sc, IX_QMGR_QINTREG1_OFFSET)); - - /* No queue has interrupt register set */ - if (intRegVal != 0) { - /* get the first queue Id from the interrupt register value */ - qIndex = (32 - 1) - _lzcount(intRegVal); - - DPRINTFn(2, sc->sc_dev, "%s: ISR0 0x%x qIndex %u\n", - __func__, intRegVal, qIndex); - - /* - * Optimize for single callback case. - */ - qi = &sc->qinfo[qIndex]; - if (intRegVal == qi->intRegCheckMask) { - /* - * Only 1 queue event triggered a notification. - * Call the callback function for this queue - */ - qi->cb(qIndex, qi->cbarg); - } else { - /* - * The event is triggered by more than 1 queue, - * the queue search will start from the beginning - * or the middle of the priority table. - * - * The search will end when all the bits of the interrupt - * register are cleared. There is no need to maintain - * a separate value and test it at each iteration. - */ - if (intRegVal & sc->lowPriorityTableFirstHalfMask) { - priorityTableIndex = 0; - } else { - priorityTableIndex = 16; - } - /* - * Iterate over the priority table until all the bits - * of the interrupt register are cleared. - */ - do { - qIndex = sc->priorityTable[priorityTableIndex++]; - qi = &sc->qinfo[qIndex]; - - /* If this queue caused this interrupt to be raised */ - if (intRegVal & qi->intRegCheckMask) { - /* Call the callback function for this queue */ - qi->cb(qIndex, qi->cbarg); - /* Clear the interrupt register bit */ - intRegVal &= ~qi->intRegCheckMask; - } - } while (intRegVal); - } - } - - /* Rebuild the priority table if needed */ - if (sc->rebuildTable) - ixpqmgr_rebuild(sc); -} - -#if 0 -/* - * Generate the parameters used to check if a Q's status matches - * the specified source select. We calculate which status word - * to check (statusWordOffset), the value to check the status - * against (statusCheckValue) and the mask (statusMask) to mask - * out all but the bits to check in the status word. - */ -static void -aqm_calc_statuscheck(int qId, IxQMgrSourceId srcSel) -{ - struct qmgrInfo *qi = &qinfo[qId]; - uint32_t shiftVal; - - if (qId < IX_QMGR_MIN_QUEUPP_QID) { - switch (srcSel) { - case IX_QMGR_Q_SOURCE_ID_E: - qi->statusCheckValue = IX_QMGR_Q_STATUS_E_BIT_MASK; - qi->statusMask = IX_QMGR_Q_STATUS_E_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NE: - qi->statusCheckValue = IX_QMGR_Q_STATUS_NE_BIT_MASK; - qi->statusMask = IX_QMGR_Q_STATUS_NE_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NF: - qi->statusCheckValue = IX_QMGR_Q_STATUS_NF_BIT_MASK; - qi->statusMask = IX_QMGR_Q_STATUS_NF_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_F: - qi->statusCheckValue = IX_QMGR_Q_STATUS_F_BIT_MASK; - qi->statusMask = IX_QMGR_Q_STATUS_F_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_E: - qi->statusCheckValue = 0; - qi->statusMask = IX_QMGR_Q_STATUS_E_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_NE: - qi->statusCheckValue = 0; - qi->statusMask = IX_QMGR_Q_STATUS_NE_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_NF: - qi->statusCheckValue = 0; - qi->statusMask = IX_QMGR_Q_STATUS_NF_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_F: - qi->statusCheckValue = 0; - qi->statusMask = IX_QMGR_Q_STATUS_F_BIT_MASK; - break; - default: - /* Should never hit */ - IX_OSAL_ASSERT(0); - break; - } - - /* One nibble of status per queue so need to shift the - * check value and mask out to the correct position. - */ - shiftVal = (qId % IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) * - IX_QMGR_QUELOWSTAT_BITS_PER_Q; - - /* Calculate the which status word to check from the qId, - * 8 Qs status per word - */ - qi->statusWordOffset = qId / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD; - - qi->statusCheckValue <<= shiftVal; - qi->statusMask <<= shiftVal; - } else { - /* One status word */ - qi->statusWordOffset = 0; - /* Single bits per queue and int source bit hardwired NE, - * Qs start at 32. - */ - qi->statusMask = 1 << (qId - IX_QMGR_MIN_QUEUPP_QID); - qi->statusCheckValue = qi->statusMask; - } -} -#endif - -static void -aqm_int_enable(struct ixpqmgr_softc *sc, int qId) -{ - bus_size_t reg; - uint32_t v; - - if (qId < IX_QMGR_MIN_QUEUPP_QID) - reg = IX_QMGR_QUEIEREG0_OFFSET; - else - reg = IX_QMGR_QUEIEREG1_OFFSET; - v = aqm_reg_read(sc, reg); - aqm_reg_write(sc, reg, v | (1 << (qId % IX_QMGR_MIN_QUEUPP_QID))); - - DPRINTF(sc->sc_dev, "%s(%u) 0x%lx: 0x%x => 0x%x\n", - __func__, qId, reg, v, aqm_reg_read(sc, reg)); -} - -static void -aqm_int_disable(struct ixpqmgr_softc *sc, int qId) -{ - bus_size_t reg; - uint32_t v; - - if (qId < IX_QMGR_MIN_QUEUPP_QID) - reg = IX_QMGR_QUEIEREG0_OFFSET; - else - reg = IX_QMGR_QUEIEREG1_OFFSET; - v = aqm_reg_read(sc, reg); - aqm_reg_write(sc, reg, v &~ (1 << (qId % IX_QMGR_MIN_QUEUPP_QID))); - - DPRINTF(sc->sc_dev, "%s(%u) 0x%lx: 0x%x => 0x%x\n", - __func__, qId, reg, v, aqm_reg_read(sc, reg)); -} - -static unsigned -log2(unsigned n) -{ - unsigned count; - /* - * N.B. this function will return 0 if supplied 0. - */ - for (count = 0; n/2; count++) - n /= 2; - return count; -} - -static __inline unsigned -toAqmEntrySize(int entrySize) -{ - /* entrySize 1("00"),2("01"),4("10") */ - return log2(entrySize); -} - -static __inline unsigned -toAqmBufferSize(unsigned bufferSizeInWords) -{ - /* bufferSize 16("00"),32("01),64("10"),128("11") */ - return log2(bufferSizeInWords / IX_QMGR_MIN_BUFFER_SIZE); -} - -static __inline unsigned -toAqmWatermark(int watermark) -{ - /* - * Watermarks 0("000"),1("001"),2("010"),4("011"), - * 8("100"),16("101"),32("110"),64("111") - */ - return log2(2 * watermark); -} - -static void -aqm_qcfg(struct ixpqmgr_softc *sc, int qId, u_int ne, u_int nf) -{ - const struct qmgrInfo *qi = &sc->qinfo[qId]; - uint32_t qCfg; - uint32_t baseAddress; - - /* Build config register */ - qCfg = ((toAqmEntrySize(1) & IX_QMGR_ENTRY_SIZE_MASK) << - IX_QMGR_Q_CONFIG_ESIZE_OFFSET) - | ((toAqmBufferSize(qi->qSizeInWords) & IX_QMGR_SIZE_MASK) << - IX_QMGR_Q_CONFIG_BSIZE_OFFSET); - - /* baseAddress, calculated relative to start address */ - baseAddress = sc->aqmFreeSramAddress; - - /* base address must be word-aligned */ - KASSERT((baseAddress % IX_QMGR_BASE_ADDR_16_WORD_ALIGN) == 0, - ("address not word-aligned")); - - /* Now convert to a 16 word pointer as required by QUECONFIG register */ - baseAddress >>= IX_QMGR_BASE_ADDR_16_WORD_SHIFT; - qCfg |= baseAddress << IX_QMGR_Q_CONFIG_BADDR_OFFSET; - - /* set watermarks */ - qCfg |= (toAqmWatermark(ne) << IX_QMGR_Q_CONFIG_NE_OFFSET) - | (toAqmWatermark(nf) << IX_QMGR_Q_CONFIG_NF_OFFSET); - - DPRINTF(sc->sc_dev, "%s(%u, %u, %u) 0x%x => 0x%x @ 0x%x\n", - __func__, qId, ne, nf, - aqm_reg_read(sc, IX_QMGR_Q_CONFIG_ADDR_GET(qId)), - qCfg, IX_QMGR_Q_CONFIG_ADDR_GET(qId)); - - aqm_reg_write(sc, IX_QMGR_Q_CONFIG_ADDR_GET(qId), qCfg); -} - -static void -aqm_srcsel_write(struct ixpqmgr_softc *sc, int qId, int sourceId) -{ - bus_size_t off; - uint32_t v; - - /* - * Calculate the register offset; multiple queues split across registers - */ - off = IX_QMGR_INT0SRCSELREG0_OFFSET + - ((qId / IX_QMGR_INTSRC_NUM_QUE_PER_WORD) * sizeof(uint32_t)); - - v = aqm_reg_read(sc, off); - if (off == IX_QMGR_INT0SRCSELREG0_OFFSET && qId == 0) { - /* Queue 0 at INT0SRCSELREG should not corrupt the value bit-3 */ - v |= 0x7; - } else { - const uint32_t bpq = 32 / IX_QMGR_INTSRC_NUM_QUE_PER_WORD; - uint32_t mask; - int qshift; - - qshift = (qId & (IX_QMGR_INTSRC_NUM_QUE_PER_WORD-1)) * bpq; - mask = ((1 << bpq) - 1) << qshift; /* q's status mask */ - - /* merge sourceId */ - v = (v &~ mask) | ((sourceId << qshift) & mask); - } - - DPRINTF(sc->sc_dev, "%s(%u, %u) 0x%x => 0x%x @ 0x%lx\n", - __func__, qId, sourceId, aqm_reg_read(sc, off), v, off); - aqm_reg_write(sc, off, v); -} - -/* - * Reset AQM registers to default values. - */ -static void -aqm_reset(struct ixpqmgr_softc *sc) -{ - int i; - - /* Reset queues 0..31 status registers 0..3 */ - aqm_reg_write(sc, IX_QMGR_QUELOWSTAT0_OFFSET, - IX_QMGR_QUELOWSTAT_RESET_VALUE); - aqm_reg_write(sc, IX_QMGR_QUELOWSTAT1_OFFSET, - IX_QMGR_QUELOWSTAT_RESET_VALUE); - aqm_reg_write(sc, IX_QMGR_QUELOWSTAT2_OFFSET, - IX_QMGR_QUELOWSTAT_RESET_VALUE); - aqm_reg_write(sc, IX_QMGR_QUELOWSTAT3_OFFSET, - IX_QMGR_QUELOWSTAT_RESET_VALUE); - - /* Reset underflow/overflow status registers 0..1 */ - aqm_reg_write(sc, IX_QMGR_QUEUOSTAT0_OFFSET, - IX_QMGR_QUEUOSTAT_RESET_VALUE); - aqm_reg_write(sc, IX_QMGR_QUEUOSTAT1_OFFSET, - IX_QMGR_QUEUOSTAT_RESET_VALUE); - - /* Reset queues 32..63 nearly empty status registers */ - aqm_reg_write(sc, IX_QMGR_QUEUPPSTAT0_OFFSET, - IX_QMGR_QUEUPPSTAT0_RESET_VALUE); - - /* Reset queues 32..63 full status registers */ - aqm_reg_write(sc, IX_QMGR_QUEUPPSTAT1_OFFSET, - IX_QMGR_QUEUPPSTAT1_RESET_VALUE); - - /* Reset int0 status flag source select registers 0..3 */ - aqm_reg_write(sc, IX_QMGR_INT0SRCSELREG0_OFFSET, - IX_QMGR_INT0SRCSELREG_RESET_VALUE); - aqm_reg_write(sc, IX_QMGR_INT0SRCSELREG1_OFFSET, - IX_QMGR_INT0SRCSELREG_RESET_VALUE); - aqm_reg_write(sc, IX_QMGR_INT0SRCSELREG2_OFFSET, - IX_QMGR_INT0SRCSELREG_RESET_VALUE); - aqm_reg_write(sc, IX_QMGR_INT0SRCSELREG3_OFFSET, - IX_QMGR_INT0SRCSELREG_RESET_VALUE); - - /* Reset queue interrupt enable register 0..1 */ - aqm_reg_write(sc, IX_QMGR_QUEIEREG0_OFFSET, - IX_QMGR_QUEIEREG_RESET_VALUE); - aqm_reg_write(sc, IX_QMGR_QUEIEREG1_OFFSET, - IX_QMGR_QUEIEREG_RESET_VALUE); - - /* Reset queue interrupt register 0..1 */ - aqm_reg_write(sc, IX_QMGR_QINTREG0_OFFSET, IX_QMGR_QINTREG_RESET_VALUE); - aqm_reg_write(sc, IX_QMGR_QINTREG1_OFFSET, IX_QMGR_QINTREG_RESET_VALUE); - - /* Reset queue configuration words 0..63 */ - for (i = 0; i < IX_QMGR_MAX_NUM_QUEUES; i++) - aqm_reg_write(sc, sc->qinfo[i].qConfigRegAddr, - IX_QMGR_QUECONFIG_RESET_VALUE); - - /* XXX zero SRAM to simplify debugging */ - for (i = IX_QMGR_QUEBUFFER_SPACE_OFFSET; - i < IX_QMGR_AQM_SRAM_SIZE_IN_BYTES; i += sizeof(uint32_t)) - aqm_reg_write(sc, i, 0); -} - -static device_method_t ixpqmgr_methods[] = { - DEVMETHOD(device_probe, ixpqmgr_probe), - DEVMETHOD(device_attach, ixpqmgr_attach), - DEVMETHOD(device_detach, ixpqmgr_detach), - - { 0, 0 } -}; - -static driver_t ixpqmgr_driver = { - "ixpqmgr", - ixpqmgr_methods, - sizeof(struct ixpqmgr_softc), -}; -static devclass_t ixpqmgr_devclass; - -DRIVER_MODULE(ixpqmgr, ixp, ixpqmgr_driver, ixpqmgr_devclass, 0, 0); diff --git a/sys/arm/xscale/ixp425/ixp425_qmgr.h b/sys/arm/xscale/ixp425/ixp425_qmgr.h deleted file mode 100644 index 62a3edcba85e..000000000000 --- a/sys/arm/xscale/ixp425/ixp425_qmgr.h +++ /dev/null @@ -1,247 +0,0 @@ -/*- - * Copyright (c) 2006 Sam Leffler, Errno Consulting - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - * - * $FreeBSD$ - */ - -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2001-2005, Intel Corporation. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Intel Corporation nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. -*/ - -#ifndef ARM_XSCALE_IXP425_QMGR_H -#define ARM_XSCALE_IXP425_QMGR_H - -#define IX_QMGR_MAX_NUM_QUEUES 64 -#define IX_QMGR_MIN_QUEUPP_QID 32 - -#define IX_QMGR_MIN_ENTRY_SIZE_IN_WORDS 16 - -/* Total size of SRAM */ -#define IX_QMGR_AQM_SRAM_SIZE_IN_BYTES 0x4000 - -#define IX_QMGR_Q_PRIORITY_0 0 -#define IX_QMGR_Q_PRIORITY_1 1 -#define IX_QMGR_Q_PRIORITY_2 2 -#define IX_QMGR_NUM_PRIORITY_LEVELS 3 /* number of priority levels */ - -#define IX_QMGR_Q_STATUS_E_BIT_MASK 0x1 /* Empty */ -#define IX_QMGR_Q_STATUS_NE_BIT_MASK 0x2 /* Nearly Empty */ -#define IX_QMGR_Q_STATUS_NF_BIT_MASK 0x4 /* Nearly Full */ -#define IX_QMGR_Q_STATUS_F_BIT_MASK 0x8 /* Full */ -#define IX_QMGR_Q_STATUS_UF_BIT_MASK 0x10 /* Underflow */ -#define IX_QMGR_Q_STATUS_OF_BIT_MASK 0x20 /* Overflow */ - -#define IX_QMGR_Q_SOURCE_ID_E 0 /* Q Empty after last read */ -#define IX_QMGR_Q_SOURCE_ID_NE 1 /* Q Nearly Empty after last read */ -#define IX_QMGR_Q_SOURCE_ID_NF 2 /* Q Nearly Full after last write */ -#define IX_QMGR_Q_SOURCE_ID_F 3 /* Q Full after last write */ -#define IX_QMGR_Q_SOURCE_ID_NOT_E 4 /* Q !Empty after last write */ -#define IX_QMGR_Q_SOURCE_ID_NOT_NE 5 /* Q !Nearly Empty after last write */ -#define IX_QMGR_Q_SOURCE_ID_NOT_NF 6 /* Q !Nearly Full after last read */ -#define IX_QMGR_Q_SOURCE_ID_NOT_F 7 /* Q !Full after last read */ - -#define IX_QMGR_UNDERFLOW_BIT_OFFSET 0x0 /* underflow bit mask */ -#define IX_QMGR_OVERFLOW_BIT_OFFSET 0x1 /* overflow bit mask */ - -#define IX_QMGR_QUEACC0_OFFSET 0x0000 /* q 0 access register */ -#define IX_QMGR_QUEACC_SIZE 0x4/*words*/ - -#define IX_QMGR_QUELOWSTAT0_OFFSET 0x400 /* Q status, q's 0-7 */ -#define IX_QMGR_QUELOWSTAT1_OFFSET 0x404 /* Q status, q's 8-15 */ -#define IX_QMGR_QUELOWSTAT2_OFFSET 0x408 /* Q status, q's 16-23 */ -#define IX_QMGR_QUELOWSTAT3_OFFSET 0x40c /* Q status, q's 24-31 */ - -/* Queue status register Q status bits mask */ -#define IX_QMGR_QUELOWSTAT_QUE_STS_BITS_MASK 0xF -/* Size of queue 0-31 status register */ -#define IX_QMGR_QUELOWSTAT_SIZE 0x4 /*words*/ -#define IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD 8 /* # status/word */ - -#define IX_QMGR_QUEUOSTAT0_OFFSET 0x410 /* Q UF/OF status, q's 0-15 */ -#define IX_QMGR_QUEUOSTAT1_OFFSET 0x414 /* Q UF/OF status, q's 16-31 */ - -#define IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD 16 /* # UF/OF status/word */ - -#define IX_QMGR_QUEUPPSTAT0_OFFSET 0x418 /* NE status, q's 32-63 */ -#define IX_QMGR_QUEUPPSTAT1_OFFSET 0x41c /* F status, q's 32-63 */ - -#define IX_QMGR_INT0SRCSELREG0_OFFSET 0x420 /* INT src select, q's 0-7 */ -#define IX_QMGR_INT0SRCSELREG1_OFFSET 0x424 /* INT src select, q's 8-15 */ -#define IX_QMGR_INT0SRCSELREG2_OFFSET 0x428 /* INT src select, q's 16-23 */ -#define IX_QMGR_INT0SRCSELREG3_OFFSET 0x42c /* INT src select, q's 24-31 */ - -#define IX_QMGR_INTSRC_NUM_QUE_PER_WORD 8 /* # INT src select/word */ - -#define IX_QMGR_QUEIEREG0_OFFSET 0x430 /* INT enable, q's 0-31 */ -#define IX_QMGR_QUEIEREG1_OFFSET 0x434 /* INT enable, q's 32-63 */ -#define IX_QMGR_QINTREG0_OFFSET 0x438 /* INT status, q's 0-31 */ -#define IX_QMGR_QINTREG1_OFFSET 0x43c /* INT status, q's 32-63 */ - -#define IX_QMGR_QUECONFIG_BASE_OFFSET 0x2000 /* Q config register, q 0 */ - -#define IX_QMGR_QUECONFIG_SIZE 0x100 /* total size of Q config regs*/ - -#define IX_QMGR_QUEBUFFER_SPACE_OFFSET 0x2100 /* start of SRAM */ - -/* Total bits in a word */ -#define BITS_PER_WORD 32 - -/* Size of queue buffer space */ -#define IX_QMGR_QUE_BUFFER_SPACE_SIZE 0x1F00 - -/* - * This macro will return the address of the access register for the - * queue specified by qId - */ -#define IX_QMGR_Q_ACCESS_ADDR_GET(qId)\ - (((qId) * (IX_QMGR_QUEACC_SIZE * sizeof(uint32_t)))\ - + IX_QMGR_QUEACC0_OFFSET) - -/* - * Bit location of bit-3 of INT0SRCSELREG0 register to enabled - * sticky interrupt register. - */ -#define IX_QMGR_INT0SRCSELREG0_BIT3 3 - -/* - * These defines are the bit offsets of the various fields of - * the queue configuration register. - */ -#if 0 -#define IX_QMGR_Q_CONFIG_WRPTR_OFFSET 0x00 -#define IX_QMGR_Q_CONFIG_RDPTR_OFFSET 0x07 -#define IX_QMGR_Q_CONFIG_BADDR_OFFSET 0x0E -#define IX_QMGR_Q_CONFIG_ESIZE_OFFSET 0x16 -#define IX_QMGR_Q_CONFIG_BSIZE_OFFSET 0x18 -#define IX_QMGR_Q_CONFIG_NE_OFFSET 0x1A -#define IX_QMGR_Q_CONFIG_NF_OFFSET 0x1D - -#define IX_QMGR_NE_NF_CLEAR_MASK 0x03FFFFFF -#define IX_QMGR_NE_MASK 0x7 -#define IX_QMGR_NF_MASK 0x7 -#define IX_QMGR_SIZE_MASK 0x3 -#define IX_QMGR_ENTRY_SIZE_MASK 0x3 -#define IX_QMGR_BADDR_MASK 0x003FC000 -#define IX_QMGR_RDPTR_MASK 0x7F -#define IX_QMGR_WRPTR_MASK 0x7F -#define IX_QMGR_RDWRPTR_MASK 0x00003FFF -#else -#define IX_QMGR_Q_CONFIG_WRPTR_OFFSET 0 -#define IX_QMGR_WRPTR_MASK 0x7F -#define IX_QMGR_Q_CONFIG_RDPTR_OFFSET 7 -#define IX_QMGR_RDPTR_MASK 0x7F -#define IX_QMGR_Q_CONFIG_BADDR_OFFSET 14 -#define IX_QMGR_BADDR_MASK 0x3FC000 /* XXX not used */ -#define IX_QMGR_Q_CONFIG_ESIZE_OFFSET 22 -#define IX_QMGR_ENTRY_SIZE_MASK 0x3 -#define IX_QMGR_Q_CONFIG_BSIZE_OFFSET 24 -#define IX_QMGR_SIZE_MASK 0x3 -#define IX_QMGR_Q_CONFIG_NE_OFFSET 26 -#define IX_QMGR_NE_MASK 0x7 -#define IX_QMGR_Q_CONFIG_NF_OFFSET 29 -#define IX_QMGR_NF_MASK 0x7 - -#define IX_QMGR_RDWRPTR_MASK 0x00003FFF -#define IX_QMGR_NE_NF_CLEAR_MASK 0x03FFFFFF -#endif - -#define IX_QMGR_BASE_ADDR_16_WORD_ALIGN 64 -#define IX_QMGR_BASE_ADDR_16_WORD_SHIFT 6 - -#define IX_QMGR_AQM_ADDRESS_SPACE_SIZE_IN_WORDS 0x1000 - -/* Base address of AQM SRAM */ -#define IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET \ -((IX_QMGR_QUECONFIG_BASE_OFFSET) + (IX_QMGR_QUECONFIG_SIZE)) - -/* Min buffer size used for generating buffer size in QUECONFIG */ -#define IX_QMGR_MIN_BUFFER_SIZE 16 - -/* Reset values of QMgr hardware registers */ -#define IX_QMGR_QUELOWSTAT_RESET_VALUE 0x33333333 -#define IX_QMGR_QUEUOSTAT_RESET_VALUE 0x00000000 -#define IX_QMGR_QUEUPPSTAT0_RESET_VALUE 0xFFFFFFFF -#define IX_QMGR_QUEUPPSTAT1_RESET_VALUE 0x00000000 -#define IX_QMGR_INT0SRCSELREG_RESET_VALUE 0x00000000 -#define IX_QMGR_QUEIEREG_RESET_VALUE 0x00000000 -#define IX_QMGR_QINTREG_RESET_VALUE 0xFFFFFFFF -#define IX_QMGR_QUECONFIG_RESET_VALUE 0x00000000 - -#define IX_QMGR_QUELOWSTAT_BITS_PER_Q \ - (BITS_PER_WORD/IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) - -#define IX_QMGR_QUELOWSTAT_QID_MASK 0x7 -#define IX_QMGR_Q_CONFIG_ADDR_GET(qId)\ - (((qId) * sizeof(uint32_t)) + IX_QMGR_QUECONFIG_BASE_OFFSET) - -#define IX_QMGR_ENTRY1_OFFSET 0 -#define IX_QMGR_ENTRY2_OFFSET 1 -#define IX_QMGR_ENTRY4_OFFSET 3 - -typedef void qconfig_hand_t(int, void *); - -int ixpqmgr_qconfig(int qId, int qSizeInWords, int ne, int nf, int srcSel, - qconfig_hand_t *cb, void *cbarg); -int ixpqmgr_qwrite(int qId, uint32_t entry); -int ixpqmgr_qread(int qId, uint32_t *entry); -int ixpqmgr_qreadm(int qId, uint32_t n, uint32_t *p); -uint32_t ixpqmgr_getqstatus(int qId); -uint32_t ixpqmgr_getqconfig(int qId); -void ixpqmgr_notify_enable(int qId, int srcSel); -void ixpqmgr_notify_disable(int qId); -void ixpqmgr_dump(void); - -#endif /* ARM_XSCALE_IXP425_QMGR_H */ diff --git a/sys/arm/xscale/ixp425/ixp425_space.c b/sys/arm/xscale/ixp425/ixp425_space.c deleted file mode 100644 index 1dcc545ea224..000000000000 --- a/sys/arm/xscale/ixp425/ixp425_space.c +++ /dev/null @@ -1,125 +0,0 @@ -/* $NetBSD: ixp425_space.c,v 1.7 2009/10/21 14:15:51 rmind Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-2-Clause-NetBSD - * - * Copyright (c) 2003 - * Ichiro FUKUHARA . - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -/* - * bus_space I/O functions for ixp425 - */ - -#include -#include -#include - -#include - -#include -#include -#include -#include -#include - -#include - -#include -#include - -/* Proto types for all the bus_space structure functions */ -bs_protos(generic); - -struct bus_space ixp425_bs_tag = { - /* cookie */ - .bs_privdata = (void *) 0, - - /* mapping/unmapping */ - .bs_map = generic_bs_map, - .bs_unmap = generic_bs_unmap, - .bs_subregion = generic_bs_subregion, - - /* allocation/deallocation */ - .bs_alloc = generic_bs_alloc, - .bs_free = generic_bs_free, - - /* barrier */ - .bs_barrier = generic_bs_barrier, - - /* read (single) */ - .bs_r_1 = generic_bs_r_1, - .bs_r_2 = generic_bs_r_2, - .bs_r_4 = generic_bs_r_4, - .bs_r_8 = NULL, - - /* read multiple */ - .bs_rm_1 = generic_bs_rm_1, - .bs_rm_2 = generic_bs_rm_2, - .bs_rm_4 = generic_bs_rm_4, - .bs_rm_8 = NULL, - - /* read region */ - .bs_rr_1 = generic_bs_rr_1, - .bs_rr_2 = generic_bs_rr_2, - .bs_rr_4 = generic_bs_rr_4, - .bs_rr_8 = NULL, - - /* write (single) */ - .bs_w_1 = generic_bs_w_1, - .bs_w_2 = generic_bs_w_2, - .bs_w_4 = generic_bs_w_4, - .bs_w_8 = NULL, - - /* write multiple */ - .bs_wm_1 = generic_bs_wm_1, - .bs_wm_2 = generic_bs_wm_2, - .bs_wm_4 = generic_bs_wm_4, - .bs_wm_8 = NULL, - - /* write region */ - .bs_wr_1 = generic_bs_wr_1, - .bs_wr_2 = generic_bs_wr_2, - .bs_wr_4 = generic_bs_wr_4, - .bs_wr_8 = NULL, - - /* set multiple */ - /* XXX not implemented */ - - /* set region */ - .bs_sr_1 = NULL, - .bs_sr_2 = generic_bs_sr_2, - .bs_sr_4 = generic_bs_sr_4, - .bs_sr_8 = NULL, - - /* copy */ - .bs_c_1 = NULL, - .bs_c_2 = generic_bs_c_2, - .bs_c_4 = NULL, - .bs_c_8 = NULL, -}; diff --git a/sys/arm/xscale/ixp425/ixp425_timer.c b/sys/arm/xscale/ixp425/ixp425_timer.c deleted file mode 100644 index c0d9109d91d2..000000000000 --- a/sys/arm/xscale/ixp425/ixp425_timer.c +++ /dev/null @@ -1,266 +0,0 @@ -/* $NetBSD: ixp425_timer.c,v 1.15 2009/10/21 14:15:51 rmind Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-2-Clause-NetBSD - * - * Copyright (c) 2003 - * Ichiro FUKUHARA . - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -static uint32_t counts_per_hz; - -/* callback functions for intr_functions */ -int ixpclk_intr(void *); - -struct ixpclk_softc { - device_t sc_dev; - bus_addr_t sc_baseaddr; - bus_space_tag_t sc_iot; - bus_space_handle_t sc_ioh; -}; - -static unsigned ixp425_timer_get_timecount(struct timecounter *tc); - -#ifndef IXP425_CLOCK_FREQ -#define COUNTS_PER_SEC 66666600 /* 66MHz */ -#else -#define COUNTS_PER_SEC IXP425_CLOCK_FREQ -#endif -#define COUNTS_PER_USEC ((COUNTS_PER_SEC / 1000000) + 1) - -static struct ixpclk_softc *ixpclk_sc = NULL; - -#define GET_TS_VALUE(sc) (*(volatile u_int32_t *) \ - (IXP425_TIMER_VBASE + IXP425_OST_TS)) - -static struct timecounter ixp425_timer_timecounter = { - ixp425_timer_get_timecount, /* get_timecount */ - NULL, /* no poll_pps */ - ~0u, /* counter_mask */ - COUNTS_PER_SEC, /* frequency */ - "IXP4XX Timer", /* name */ - 1000, /* quality */ -}; - -static int -ixpclk_probe(device_t dev) -{ - device_set_desc(dev, "IXP4XX Timer"); - return (0); -} - -static int -ixpclk_attach(device_t dev) -{ - struct ixpclk_softc *sc = device_get_softc(dev); - struct ixp425_softc *sa = device_get_softc(device_get_parent(dev)); - - ixpclk_sc = sc; - - sc->sc_dev = dev; - sc->sc_iot = sa->sc_iot; - sc->sc_baseaddr = IXP425_TIMER_HWBASE; - - if (bus_space_map(sc->sc_iot, sc->sc_baseaddr, 8, 0, - &sc->sc_ioh)) - panic("%s: Cannot map registers", device_get_name(dev)); - - return (0); -} - -static device_method_t ixpclk_methods[] = { - DEVMETHOD(device_probe, ixpclk_probe), - DEVMETHOD(device_attach, ixpclk_attach), - {0, 0}, -}; - -static driver_t ixpclk_driver = { - "ixpclk", - ixpclk_methods, - sizeof(struct ixpclk_softc), -}; -static devclass_t ixpclk_devclass; - -DRIVER_MODULE(ixpclk, ixp, ixpclk_driver, ixpclk_devclass, 0, 0); -static unsigned -ixp425_timer_get_timecount(struct timecounter *tc) -{ - uint32_t ret; - - ret = GET_TS_VALUE(sc); - return (ret); -} - -/* - * cpu_initclocks: - * - * Initialize the clock and get them going. - */ -void -cpu_initclocks(void) -{ - struct ixpclk_softc* sc = ixpclk_sc; - struct resource *irq; - device_t dev = sc->sc_dev; - u_int oldirqstate; - int rid = 0; - void *ihl; - - if (hz < 50 || COUNTS_PER_SEC % hz) { - printf("Cannot get %d Hz clock; using 100 Hz\n", hz); - hz = 100; - } - tick = 1000000 / hz; /* number of microseconds between interrupts */ - - /* - * We only have one timer available; stathz and profhz are - * always left as 0 (the upper-layer clock code deals with - * this situation). - */ - if (stathz != 0) - printf("Cannot get %d Hz statclock\n", stathz); - stathz = 0; - - if (profhz != 0) - printf("Cannot get %d Hz profclock\n", profhz); - profhz = 0; - - /* Report the clock frequency. */ - - oldirqstate = disable_interrupts(PSR_I); - - irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, IXP425_INT_TMR0, - IXP425_INT_TMR0, 1, RF_ACTIVE); - if (!irq) - panic("Unable to setup the clock irq handler.\n"); - else - bus_setup_intr(dev, irq, INTR_TYPE_CLK, ixpclk_intr, NULL, - NULL, &ihl); - - /* Set up the new clock parameters. */ - - /* clear interrupt */ - bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_STATUS, - OST_WARM_RESET | OST_WDOG_INT | OST_TS_INT | - OST_TIM1_INT | OST_TIM0_INT); - - counts_per_hz = COUNTS_PER_SEC / hz; - - /* reload value & Timer enable */ - bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_TIM0_RELOAD, - (counts_per_hz & TIMERRELOAD_MASK) | OST_TIMER_EN); - - tc_init(&ixp425_timer_timecounter); - restore_interrupts(oldirqstate); - rid = 0; -} - - -/* - * DELAY: - * - * Delay for at least N microseconds. - */ -void -DELAY(int n) -{ - u_int32_t first, last; - int usecs; - - if (n == 0) - return; - TSENTER(); - - /* - * Clamp the timeout at a maximum value (about 32 seconds with - * a 66MHz clock). *Nobody* should be delay()ing for anywhere - * near that length of time and if they are, they should be hung - * out to dry. - */ - if (n >= (0x80000000U / COUNTS_PER_USEC)) - usecs = (0x80000000U / COUNTS_PER_USEC) - 1; - else - usecs = n * COUNTS_PER_USEC; - - /* Note: Timestamp timer counts *up*, unlike the other timers */ - first = GET_TS_VALUE(); - - while (usecs > 0) { - last = GET_TS_VALUE(); - usecs -= (int)(last - first); - first = last; - } - TSEXIT(); -} - -/* - * ixpclk_intr: - * - * Handle the hardclock interrupt. - */ -int -ixpclk_intr(void *arg) -{ - struct ixpclk_softc* sc = ixpclk_sc; - struct trapframe *frame = arg; - - bus_space_write_4(sc->sc_iot, sc->sc_ioh, IXP425_OST_STATUS, - OST_TIM0_INT); - - hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); - return (FILTER_HANDLED); -} - -void -cpu_startprofclock(void) -{ -} - -void -cpu_stopprofclock(void) -{ -} diff --git a/sys/arm/xscale/ixp425/ixp425_wdog.c b/sys/arm/xscale/ixp425/ixp425_wdog.c deleted file mode 100644 index ede52063d114..000000000000 --- a/sys/arm/xscale/ixp425/ixp425_wdog.c +++ /dev/null @@ -1,117 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 Sam Leffler. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -__FBSDID("$FreeBSD$"); - -/* - * IXP4XX Watchdog Timer Support. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -struct ixpwdog_softc { - device_t sc_dev; -}; - -static __inline uint32_t -RD4(struct ixpwdog_softc *sc, bus_size_t off) -{ - return bus_space_read_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, off); -} - -static __inline void -WR4(struct ixpwdog_softc *sc, bus_size_t off, uint32_t val) -{ - bus_space_write_4(&ixp425_bs_tag, IXP425_TIMER_VBASE, off, val); -} - -static void -ixp425_watchdog(void *arg, u_int cmd, int *error) -{ - struct ixpwdog_softc *sc = arg; - u_int u = cmd & WD_INTERVAL; - - WR4(sc, IXP425_OST_WDOG_KEY, OST_WDOG_KEY_MAJICK); - if (4 <= u && u <= 35) { - WR4(sc, IXP425_OST_WDOG_ENAB, 0); - /* approximate 66.66MHz cycles */ - WR4(sc, IXP425_OST_WDOG, 2<<(u - 4)); - /* NB: reset on timer expiration */ - WR4(sc, IXP425_OST_WDOG_ENAB, - OST_WDOG_ENAB_CNT_ENA | OST_WDOG_ENAB_RST_ENA); - *error = 0; - } else { - /* disable watchdog */ - WR4(sc, IXP425_OST_WDOG_ENAB, 0); - } - WR4(sc, IXP425_OST_WDOG_KEY, 0); -} - -static int -ixpwdog_probe(device_t dev) -{ - device_set_desc(dev, "IXP4XX Watchdog Timer"); - return (0); -} - -static int -ixpwdog_attach(device_t dev) -{ - struct ixpwdog_softc *sc = device_get_softc(dev); - - sc->sc_dev = dev; - - EVENTHANDLER_REGISTER(watchdog_list, ixp425_watchdog, sc, 0); - return (0); -} - -static device_method_t ixpwdog_methods[] = { - DEVMETHOD(device_probe, ixpwdog_probe), - DEVMETHOD(device_attach, ixpwdog_attach), - {0, 0}, -}; - -static driver_t ixpwdog_driver = { - "ixpwdog", - ixpwdog_methods, - sizeof(struct ixpwdog_softc), -}; -static devclass_t ixpwdog_devclass; -DRIVER_MODULE(ixpwdog, ixp, ixpwdog_driver, ixpwdog_devclass, 0, 0); diff --git a/sys/arm/xscale/ixp425/ixp425reg.h b/sys/arm/xscale/ixp425/ixp425reg.h deleted file mode 100644 index 14a3c9aab22d..000000000000 --- a/sys/arm/xscale/ixp425/ixp425reg.h +++ /dev/null @@ -1,710 +0,0 @@ -/* $NetBSD: ixp425reg.h,v 1.21 2009/10/21 14:15:51 rmind Exp $ */ -/*- - * SPDX-License-Identifier: BSD-2-Clause-NetBSD - * - * Copyright (c) 2003 - * Ichiro FUKUHARA . - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -#ifndef _IXP425REG_H_ -#define _IXP425REG_H_ - -/* - * Physical memory map for the Intel IXP425 - */ -/* - * CC00 00FF --------------------------- - * SDRAM Configuration Registers - * CC00 0000 --------------------------- - * - * C800 BFFF --------------------------- - * System and Peripheral Registers - * C800 0000 --------------------------- - * Expansion Bus Configuration Registers - * C400 0000 --------------------------- - * PCI Configuration and Status Registers - * C000 0000 --------------------------- - * - * 6400 0000 --------------------------- - * Queue manager - * 6000 0000 --------------------------- - * Expansion Bus Data - * 5000 0000 --------------------------- - * PCI Data - * 4800 0000 --------------------------- - * - * 4000 0000 --------------------------- - * SDRAM - * 0000 0000 --------------------------- - */ - -/* - * Virtual memory map for the Intel IXP425/IXP435 integrated devices - */ -/* - * FFFF FFFF --------------------------- - * - * Global cache clean area - * FF00 0000 --------------------------- - * - * FE00 0000 --------------------------- - * 16M CFI Flash (on ext bus) - * FD00 0000 --------------------------- - * - * FC00 0000 --------------------------- - * PCI Data (memory space) - * F800 0000 --------------------------- IXP425_PCI_MEM_VBASE - * - * F020 1000 --------------------------- - * SDRAM/DDR Memory Controller - * F020 0000 --------------------------- IXP425_MCU_VBASE - * - * F001 F000 RS485 (Cambria) CAMBRIA_RS485_VBASE - * F001 E000 GPS (Cambria) CAMBRIA_GPS_VBASE - * F001 D000 EHCI USB 2 (IXP435) IXP435_USB2_VBASE - * F001 C000 EHCI USB 1 (IXP435) IXP435_USB1_VBASE - * Queue manager - * F001 8000 --------------------------- IXP425_QMGR_VBASE - * PCI Configuration and Status - * F001 7000 --------------------------- IXP425_PCI_VBASE - * - * (NB: gap for future addition of EXP CS5-7) - * F001 4000 Expansion Bus Chip Select 4 - * F001 3000 Expansion Bus Chip Select 3 - * F001 2000 Expansion Bus Chip Select 2 - * F001 1000 Expansion Bus Chip Select 1 - * Expansion Bus Configuration - * F001 0000 --------------------------- IXP425_EXP_VBASE - * - * F000 C000 MAC-A (IXP435) - * F000 B000 USB (option on IXP425) - * F000 A000 MAC-B (IXP425) | MAC-C (IXP435) - * F000 9000 MAC-A (IXP425) - * F000 8000 NPE-C - * F000 7000 NPE-B (IXP425) - * F000 6000 NPE-A - * F000 5000 Timers - * F000 4000 GPIO Controller - * F000 3000 Interrupt Controller - * F000 2000 Performance Monitor Controller (PMC) - * F000 1000 UART 1 (IXP425) - * F000 0000 UART 0 - * F000 0000 --------------------------- IXP425_IO_VBASE - * - * 0000 0000 --------------------------- - * - */ - -/* Physical/Virtual address for I/O space */ - -#define IXP425_IO_VBASE 0xf0000000UL -#define IXP425_IO_HWBASE 0xc8000000UL -#define IXP425_IO_SIZE 0x00010000UL - -/* Physical/Virtual addresss offsets */ -#define IXP425_UART0_OFFSET 0x00000000UL -#define IXP425_UART1_OFFSET 0x00001000UL -#define IXP425_PMC_OFFSET 0x00002000UL -#define IXP425_INTR_OFFSET 0x00003000UL -#define IXP425_GPIO_OFFSET 0x00004000UL -#define IXP425_TIMER_OFFSET 0x00005000UL -#define IXP425_NPE_A_OFFSET 0x00006000UL /* Not User Programmable */ -#define IXP425_NPE_B_OFFSET 0x00007000UL /* Not User Programmable */ -#define IXP425_NPE_C_OFFSET 0x00008000UL /* Not User Programmable */ -#define IXP425_MAC_B_OFFSET 0x00009000UL /* Ethernet MAC on NPE-B */ -#define IXP425_MAC_C_OFFSET 0x0000a000UL /* Ethernet MAC on NPE-C */ -#define IXP425_USB_OFFSET 0x0000b000UL - -#define IXP435_MAC_A_OFFSET 0x0000c000UL /* Ethernet MAC on NPE-A */ - -#define IXP425_REG_SIZE 0x1000 - -/* - * UART - * UART0 0xc8000000 - * UART1 0xc8001000 - * - */ -/* I/O space */ -#define IXP425_UART0_HWBASE (IXP425_IO_HWBASE + IXP425_UART0_OFFSET) -#define IXP425_UART1_HWBASE (IXP425_IO_HWBASE + IXP425_UART1_OFFSET) - -#define IXP425_UART0_VBASE (IXP425_IO_VBASE + IXP425_UART0_OFFSET) - /* 0xf0000000 */ -#define IXP425_UART1_VBASE (IXP425_IO_VBASE + IXP425_UART1_OFFSET) - /* 0xf0001000 */ - -#define IXP425_UART_FREQ 14745600 - -#define IXP425_UART_IER 0x01 /* interrupt enable register */ -#define IXP425_UART_IER_RTOIE 0x10 /* receiver timeout interrupt enable */ -#define IXP425_UART_IER_UUE 0x40 /* UART Unit enable */ - -/*#define IXP4XX_COM_NPORTS 8*/ - -/* - * Timers - */ -#define IXP425_TIMER_HWBASE (IXP425_IO_HWBASE + IXP425_TIMER_OFFSET) -#define IXP425_TIMER_VBASE (IXP425_IO_VBASE + IXP425_TIMER_OFFSET) - -#define IXP425_OST_TS 0x0000 -#define IXP425_OST_TIM0 0x0004 -#define IXP425_OST_TIM1 0x000C - -#define IXP425_OST_TIM0_RELOAD 0x0008 -#define IXP425_OST_TIM1_RELOAD 0x0010 -#define TIMERRELOAD_MASK 0xFFFFFFFC -#define OST_ONESHOT_EN (1U << 1) -#define OST_TIMER_EN (1U << 0) - -#define IXP425_OST_STATUS 0x0020 -#define OST_WARM_RESET (1U << 4) -#define OST_WDOG_INT (1U << 3) -#define OST_TS_INT (1U << 2) -#define OST_TIM1_INT (1U << 1) -#define OST_TIM0_INT (1U << 0) - -#define IXP425_OST_WDOG 0x0014 -#define IXP425_OST_WDOG_ENAB 0x0018 -#define IXP425_OST_WDOG_KEY 0x001c -#define OST_WDOG_KEY_MAJICK 0x482e -#define OST_WDOG_ENAB_RST_ENA (1u << 0) -#define OST_WDOG_ENAB_INT_ENA (1u << 1) -#define OST_WDOG_ENAB_CNT_ENA (1u << 2) - -/* - * Interrupt Controller Unit. - * PA 0xc8003000 - */ - -#define IXP425_IRQ_HWBASE IXP425_IO_HWBASE + IXP425_INTR_OFFSET -#define IXP425_IRQ_VBASE IXP425_IO_VBASE + IXP425_INTR_OFFSET - /* 0xf0003000 */ -#define IXP425_IRQ_SIZE 0x00000020UL - -#define IXP425_INT_STATUS (IXP425_IRQ_VBASE + 0x00) -#define IXP425_INT_ENABLE (IXP425_IRQ_VBASE + 0x04) -#define IXP425_INT_SELECT (IXP425_IRQ_VBASE + 0x08) -#define IXP425_IRQ_STATUS (IXP425_IRQ_VBASE + 0x0C) -#define IXP425_FIQ_STATUS (IXP425_IRQ_VBASE + 0x10) -#define IXP425_INT_PRTY (IXP425_IRQ_VBASE + 0x14) -#define IXP425_IRQ_ENC (IXP425_IRQ_VBASE + 0x18) -#define IXP425_FIQ_ENC (IXP425_IRQ_VBASE + 0x1C) - -#define IXP425_INT_SW1 31 /* SW Interrupt 1 */ -#define IXP425_INT_SW0 30 /* SW Interrupt 0 */ -#define IXP425_INT_GPIO_12 29 /* GPIO 12 */ -#define IXP425_INT_GPIO_11 28 /* GPIO 11 */ -#define IXP425_INT_GPIO_10 27 /* GPIO 11 */ -#define IXP425_INT_GPIO_9 26 /* GPIO 9 */ -#define IXP425_INT_GPIO_8 25 /* GPIO 8 */ -#define IXP425_INT_GPIO_7 24 /* GPIO 7 */ -#define IXP425_INT_GPIO_6 23 /* GPIO 6 */ -#define IXP425_INT_GPIO_5 22 /* GPIO 5 */ -#define IXP425_INT_GPIO_4 21 /* GPIO 4 */ -#define IXP425_INT_GPIO_3 20 /* GPIO 3 */ -#define IXP425_INT_GPIO_2 19 /* GPIO 2 */ -#define IXP425_INT_XSCALE_PMU 18 /* XScale PMU */ -#define IXP425_INT_AHB_PMU 17 /* AHB PMU */ -#define IXP425_INT_WDOG 16 /* Watchdog Timer */ -#define IXP425_INT_UART0 15 /* HighSpeed UART */ -#define IXP425_INT_STAMP 14 /* Timestamp Timer */ -#define IXP425_INT_UART1 13 /* Console UART */ -#define IXP425_INT_USB 12 /* USB */ -#define IXP425_INT_TMR1 11 /* General-Purpose Timer1 */ -#define IXP425_INT_PCIDMA2 10 /* PCI DMA Channel 2 */ -#define IXP425_INT_PCIDMA1 9 /* PCI DMA Channel 1 */ -#define IXP425_INT_PCIINT 8 /* PCI Interrupt */ -#define IXP425_INT_GPIO_1 7 /* GPIO 1 */ -#define IXP425_INT_GPIO_0 6 /* GPIO 0 */ -#define IXP425_INT_TMR0 5 /* General-Purpose Timer0 */ -#define IXP425_INT_QUE33_64 4 /* Queue Manager 33-64 */ -#define IXP425_INT_QUE1_32 3 /* Queue Manager 1-32 */ -#define IXP425_INT_NPE_C 2 /* NPE C */ -#define IXP425_INT_NPE_B 1 /* NPE B */ -#define IXP425_INT_NPE_A 0 /* NPE A */ - -/* NB: IXP435 has an additional 32 IRQ's */ -#define IXP435_INT_STATUS2 (IXP425_IRQ_VBASE + 0x20) -#define IXP435_INT_ENABLE2 (IXP425_IRQ_VBASE + 0x24) -#define IXP435_INT_SELECT2 (IXP425_IRQ_VBASE + 0x28) -#define IXP435_IRQ_STATUS2 (IXP425_IRQ_VBASE + 0x2C) -#define IXP435_FIQ_STATUS2 (IXP425_IRQ_VBASE + 0x30) - -#define IXP435_INT_USB0 32 /* USB Host 2.0 Host 0 */ -#define IXP435_INT_USB1 33 /* USB Host 2.0 Host 1 */ -#define IXP435_INT_QMGR_PER 60 /* Queue manager parity error */ -#define IXP435_INT_ECC 61 /* Single or multi-bit ECC error */ - -/* - * software interrupt - */ -#define IXP425_INT_bit31 31 -#define IXP425_INT_bit30 30 -#define IXP425_INT_bit14 14 -#define IXP425_INT_bit11 11 - -#define IXP425_INT_HWMASK (0xffffffff & \ - ~((1 << IXP425_INT_bit31) | \ - (1 << IXP425_INT_bit30) | \ - (1 << IXP425_INT_bit14) | \ - (1 << IXP425_INT_bit11))) -#define IXP425_INT_GPIOMASK (0x3ff800c0u) - -#define IXP435_INT_HWMASK ((1 << (IXP435_INT_USB0 - 32)) | \ - (1 << (IXP435_INT_USB1 - 32)) | \ - (1 << (IXP435_INT_QMGR_PER - 32)) | \ - (1 << (IXP435_INT_ECC - 32))) - -/* - * GPIO - */ -#define IXP425_GPIO_HWBASE IXP425_IO_HWBASE + IXP425_GPIO_OFFSET -#define IXP425_GPIO_VBASE IXP425_IO_VBASE + IXP425_GPIO_OFFSET - /* 0xf0004000 */ -#define IXP425_GPIO_SIZE 0x00000020UL - -#define IXP425_GPIO_GPOUTR 0x00 -#define IXP425_GPIO_GPOER 0x04 -#define IXP425_GPIO_GPINR 0x08 -#define IXP425_GPIO_GPISR 0x0c -#define IXP425_GPIO_GPIT1R 0x10 -#define IXP425_GPIO_GPIT2R 0x14 -#define IXP425_GPIO_GPCLKR 0x18 -# define GPCLKR_MUX14 (1U << 8) -# define GPCLKR_CLK0TC_SHIFT 4 -# define GPCLKR_CLK0DC_SHIFT 0 - -/* GPIO Output */ -#define GPOUT_ON 0x1 -#define GPOUT_OFF 0x0 - -/* GPIO direction */ -#define GPOER_INPUT 0x1 -#define GPOER_OUTPUT 0x0 - -/* GPIO Type bits */ -#define GPIO_TYPE_ACT_HIGH 0x0 -#define GPIO_TYPE_ACT_LOW 0x1 -#define GPIO_TYPE_EDG_RISING 0x2 -#define GPIO_TYPE_EDG_FALLING 0x3 -#define GPIO_TYPE_TRANSITIONAL 0x4 -#define GPIO_TYPE_MASK 0x7 -#define GPIO_TYPE(b,v) ((v) << (((b) & 0x7) * 3)) -#define GPIO_TYPE_REG(b) (((b)&8)?IXP425_GPIO_GPIT2R:IXP425_GPIO_GPIT1R) - -#define IXP4XX_GPIO_PINS 16 - -/* - * Expansion Bus Configuration Space. - */ -#define IXP425_EXP_HWBASE 0xc4000000UL -#define IXP425_EXP_VBASE 0xf0010000UL -#define IXP425_EXP_SIZE 0x1000 - -/* offset */ -#define EXP_TIMING_CS0_OFFSET 0x0000 -#define EXP_TIMING_CS1_OFFSET 0x0004 -#define EXP_TIMING_CS2_OFFSET 0x0008 -#define EXP_TIMING_CS3_OFFSET 0x000c -#define EXP_TIMING_CS4_OFFSET 0x0010 -#define EXP_TIMING_CS5_OFFSET 0x0014 -#define EXP_TIMING_CS6_OFFSET 0x0018 -#define EXP_TIMING_CS7_OFFSET 0x001c -#define EXP_CNFG0_OFFSET 0x0020 -#define EXP_CNFG1_OFFSET 0x0024 -#define EXP_FCTRL_OFFSET 0x0028 - -#define IXP425_EXP_RECOVERY_SHIFT 16 -#define IXP425_EXP_HOLD_SHIFT 20 -#define IXP425_EXP_STROBE_SHIFT 22 -#define IXP425_EXP_SETUP_SHIFT 26 -#define IXP425_EXP_ADDR_SHIFT 28 -#define IXP425_EXP_CS_EN (1U << 31) - -#define IXP425_EXP_RECOVERY_T(x) (((x) & 15) << IXP425_EXP_RECOVERY_SHIFT) -#define IXP425_EXP_HOLD_T(x) (((x) & 3) << IXP425_EXP_HOLD_SHIFT) -#define IXP425_EXP_STROBE_T(x) (((x) & 15) << IXP425_EXP_STROBE_SHIFT) -#define IXP425_EXP_SETUP_T(x) (((x) & 3) << IXP425_EXP_SETUP_SHIFT) -#define IXP425_EXP_ADDR_T(x) (((x) & 3) << IXP425_EXP_ADDR_SHIFT) - -/* EXP_CSn bits */ -#define EXP_BYTE_EN 0x00000001 /* bus uses only 8-bit data */ -#define EXP_WR_EN 0x00000002 /* ena writes to CS region */ -/* bit 2 is reserved */ -#define EXP_SPLT_EN 0x00000008 /* ena AHB split transfers */ -#define EXP_MUX_EN 0x00000010 /* multiplexed address/data */ -#define EXP_HRDY_POL 0x00000020 /* HPI|HRDY polarity */ -#define EXP_BYTE_RD16 0x00000040 /* byte rd access to word dev */ -#define EXP_CNFG 0x00003c00 /* device config size */ -#define EXP_SZ_512 (0 << 10) -#define EXP_SZ_1K (1 << 10) -#define EXP_SZ_2K (2 << 10) -#define EXP_SZ_4K (3 << 10) -#define EXP_SZ_8K (4 << 10) -#define EXP_SZ_16K (5 << 10) -#define EXP_SZ_32K (6 << 10) -#define EXP_SZ_64K (7 << 10) -#define EXP_SZ_128K (8 << 10) -#define EXP_SZ_256K (9 << 10) -#define EXP_SZ_512K (10 << 10) -#define EXP_SZ_1M (11 << 10) -#define EXP_SZ_2M (12 << 10) -#define EXP_SZ_4M (13 << 10) -#define EXP_SZ_8M (14 << 10) -#define EXP_SZ_16M (15 << 10) -#define EXP_CYC_TYPE 0x0000c000 /* bus cycle "type" */ -#define EXP_CYC_INTEL (0 << 14) -#define EXP_CYC_MOTO (1 << 14) -#define EXP_CYC_HPI (2 << 14) -#define EXP_T5 0x000f0000 /* recovery timing */ -#define EXP_T4 0x00300000 /* hold timing */ -#define EXP_T3 0x03c00000 /* strobe timing */ -#define EXP_T2 0x0c000000 /* setup/chip select timing */ -#define EXP_T1 0x30000000 /* address timing */ -/* bit 30 is reserved */ -#define EXP_CS_EN 0x80000000 /* chip select enabled */ - -/* EXP_CNFG0 bits */ -#define EXP_CNFG0_8BIT (1 << 0) -#define EXP_CNFG0_PCI_HOST (1 << 1) -#define EXP_CNFG0_PCI_ARB (1 << 2) -#define EXP_CNFG0_PCI_66MHZ (1 << 4) -#define EXP_CNFG0_MEM_MAP (1U << 31) - -/* EXP_CNFG1 bits */ -#define EXP_CNFG1_SW_INT0 (1 << 0) -#define EXP_CNFG1_SW_INT1 (1 << 1) - -#define EXP_FCTRL_RCOMP (1<<0) -#define EXP_FCTRL_USB_DEVICE (1<<1) -#define EXP_FCTRL_HASH (1<<2) -#define EXP_FCTRL_AES (1<<3) -#define EXP_FCTRL_DES (1<<4) -#define EXP_FCTRL_HDLC (1<<5) -#define EXP_FCTRL_AAL (1<<6) -#define EXP_FCTRL_HSS (1<<7) -#define EXP_FCTRL_UTOPIA (1<<8) -#define EXP_FCTRL_ETH0 (1<<9) -#define EXP_FCTRL_ETH1 (1<<10) -#define EXP_FCTRL_NPEA (1<<11) /* reset */ -#define EXP_FCTRL_NPEB (1<<12) /* reset */ -#define EXP_FCTRL_NPEC (1<<13) /* reset */ -#define EXP_FCTRL_PCI (1<<14) -#define EXP_FCTRL_ECC_TIMESYNC (1<<15) -#define EXP_FCTRL_UTOPIA_PHY (3<<16) /* PHY limit */ -#define EXP_FCTRL_USB_HOST (1<<18) -#define EXP_FCTRL_NPEA_ETH (1<<19) -#define EXP_FCTRL_NPEB_ETH (1<<20) -#define EXP_FCTRL_RSA (1<<21) -#define EXP_FCTRL_MAXFREQ (3<<22) /* XScale frequency */ -#define EXP_FCTRL_RESVD (0xff<<24) - -#define EXP_FCTRL_IXP46X_ONLY \ - (EXP_FCTRL_ECC_TIMESYNC | EXP_FCTRL_USB_HOST | EXP_FCTRL_NPEA_ETH | \ - EXP_FCTRL_NPEB_ETH | EXP_FCTRL_RSA | EXP_FCTRL_MAXFREQ) - -#define EXP_FCTRL_BITS \ - "\20\1RCOMP\2USB\3HASH\4AES\5DES\6HDLC\7AAL\10HSS\11UTOPIA\12ETH0" \ - "\13ETH1\17PCI\20ECC\23USB_HOST\24NPEA_ETH\25NPEB_ETH\26RSA" - -/* - * PCI - */ -#define IXP425_PCI_HWBASE 0xc0000000 -#define IXP425_PCI_VBASE 0xf0017000UL -#define IXP425_PCI_SIZE 0x1000 - -#define IXP425_AHB_OFFSET 0x00000000UL /* AHB bus */ - -/* - * Mapping registers of IXP425 PCI Configuration - */ -/* PCI_ID_REG 0x00 */ -/* PCI_COMMAND_STATUS_REG 0x04 */ -/* PCI_CLASS_REG 0x08 */ -/* PCI_BHLC_REG 0x0c */ -#define PCI_MAPREG_BAR0 0x10 /* Base Address 0 */ -#define PCI_MAPREG_BAR1 0x14 /* Base Address 1 */ -#define PCI_MAPREG_BAR2 0x18 /* Base Address 2 */ -#define PCI_MAPREG_BAR3 0x1c /* Base Address 3 */ -#define PCI_MAPREG_BAR4 0x20 /* Base Address 4 */ -#define PCI_MAPREG_BAR5 0x24 /* Base Address 5 */ -/* PCI_SUBSYS_ID_REG 0x2c */ -/* PCI_INTERRUPT_REG 0x3c */ -#define PCI_RTOTTO 0x40 - -/* PCI Controller CSR Base Address */ -#define IXP425_PCI_CSR_BASE IXP425_PCI_VBASE - -/* PCI Memory Space */ -#define IXP425_PCI_MEM_HWBASE 0x48000000UL -#define IXP425_PCI_MEM_VBASE 0xf8000000UL -#define IXP425_PCI_MEM_SIZE 0x04000000UL /* 64MB */ - -/* PCI I/O Space */ -#define IXP425_PCI_IO_HWBASE 0x00000000UL -#define IXP425_PCI_IO_SIZE 0x00100000UL /* 1Mbyte */ - -/* PCI Controller Configuration Offset */ -#define PCI_NP_AD 0x00 -#define PCI_NP_CBE 0x04 -# define NP_CBE_SHIFT 4 -#define PCI_NP_WDATA 0x08 -#define PCI_NP_RDATA 0x0c -#define PCI_CRP_AD_CBE 0x10 -#define PCI_CRP_AD_WDATA 0x14 -#define PCI_CRP_AD_RDATA 0x18 -#define PCI_CSR 0x1c -# define CSR_PRST (1U << 16) -# define CSR_IC (1U << 15) -# define CSR_ABE (1U << 4) -# define CSR_PDS (1U << 3) -# define CSR_ADS (1U << 2) -# define CSR_HOST (1U << 0) -#define PCI_ISR 0x20 -# define ISR_AHBE (1U << 3) -# define ISR_PPE (1U << 2) -# define ISR_PFE (1U << 1) -# define ISR_PSE (1U << 0) -#define PCI_INTEN 0x24 -#define PCI_DMACTRL 0x28 -#define PCI_AHBMEMBASE 0x2c -#define PCI_AHBIOBASE 0x30 -#define PCI_PCIMEMBASE 0x34 -#define PCI_AHBDOORBELL 0x38 -#define PCI_PCIDOORBELL 0x3c -#define PCI_ATPDMA0_AHBADDR 0x40 -#define PCI_ATPDMA0_PCIADDR 0x44 -#define PCI_ATPDMA0_LENGTH 0x48 -#define PCI_ATPDMA1_AHBADDR 0x4c -#define PCI_ATPDMA1_PCIADDR 0x50 -#define PCI_ATPDMA1_LENGTH 0x54 -#define PCI_PTADMA0_AHBADDR 0x58 -#define PCI_PTADMA0_PCIADDR 0x5c -#define PCI_PTADMA0_LENGTH 0x60 -#define PCI_PTADMA1_AHBADDR 0x64 -#define PCI_PTADMA1_PCIADDR 0x68 -#define PCI_PTADMA1_LENGTH 0x6c - -/* PCI target(T)/initiator(I) Interface Commands for PCI_NP_CBE register */ -#define COMMAND_NP_IA 0x0 /* Interrupt Acknowledge (I)*/ -#define COMMAND_NP_SC 0x1 /* Special Cycle (I)*/ -#define COMMAND_NP_IO_READ 0x2 /* I/O Read (T)(I) */ -#define COMMAND_NP_IO_WRITE 0x3 /* I/O Write (T)(I) */ -#define COMMAND_NP_MEM_READ 0x6 /* Memory Read (T)(I) */ -#define COMMAND_NP_MEM_WRITE 0x7 /* Memory Write (T)(I) */ -#define COMMAND_NP_CONF_READ 0xa /* Configuration Read (T)(I) */ -#define COMMAND_NP_CONF_WRITE 0xb /* Configuration Write (T)(I) */ - -/* PCI byte enables */ -#define BE_8BIT(a) ((0x10u << ((a) & 0x03)) ^ 0xf0) -#define BE_16BIT(a) ((0x30u << ((a) & 0x02)) ^ 0xf0) -#define BE_32BIT(a) 0x00 - -/* PCI byte selects */ -#define READ_8BIT(v,a) ((u_int8_t)((v) >> (((a) & 3) * 8))) -#define READ_16BIT(v,a) ((u_int16_t)((v) >> (((a) & 2) * 8))) -#define WRITE_8BIT(v,a) (((u_int32_t)(v)) << (((a) & 3) * 8)) -#define WRITE_16BIT(v,a) (((u_int32_t)(v)) << (((a) & 2) * 8)) - -/* PCI Controller Configuration Commands for PCI_CRP_AD_CBE */ -#define COMMAND_CRP_READ 0x00 -#define COMMAND_CRP_WRITE (1U << 16) - -/* - * SDRAM Configuration Register - */ -#define IXP425_MCU_HWBASE 0xcc000000UL -#define IXP425_MCU_VBASE 0xf0200000UL -#define IXP425_MCU_SIZE 0x1000 /* Actually only 256 bytes */ -#define MCU_SDR_CONFIG 0x00 -#define MCU_SDR_CONFIG_MCONF(x) ((x) & 0x7) -#define MCU_SDR_CONFIG_64MBIT (1u << 5) -#define MCU_SDR_REFRESH 0x04 -#define MCU_SDR_IR 0x08 - -/* - * IXP435 DDR MCU Registers - */ -#define IXP435_MCU_HWBASE 0xcc00e500UL -#define MCU_DDR_SDIR 0x00 /* DDR SDAM Initialization Reg*/ -#define MCU_DDR_SDCR0 0x04 /* DDR SDRAM Control Reg 0 */ -#define MCU_DDR_SDCR1 0x08 /* DDR SDRAM Control Reg 1 */ -#define MCU_DDR_SDBR 0x0c /* SDRAM Base Register */ -#define MCU_DDR_SBR0 0x10 /* SDRAM Boundary Register 0 */ -#define MCU_DDR_SBR1 0x14 /* SDRAM Boundary Register 1 */ -#define MCU_DDR_ECCR 0x1c /* ECC Control Register */ -#define MCU_DDR_ELOG0 0x20 /* ECC Log Register 0 */ -#define MCU_DDR_ELOG1 0x24 /* ECC Log Register 1 */ -#define MCU_DDR_ECAR0 0x28 /* ECC Address Register 0 */ -#define MCU_DDR_ECAR1 0x2c /* ECC Address Register 1 */ -#define MCU_DDR_ECTST 0x30 /* ECC Test Register */ -#define MCU_DDR_MCISR 0x34 /* MC Interrupt Status Reg */ -#define MCU_DDR_MPTCR 0x3c /* MC Port Transaction Cnt Reg*/ -#define MCU_DDR_RFR 0x48 /* Refresh Frequency Register */ -#define MCU_DDR_SDPR(n) (0x50+(n)*4) /* SDRAM Page Register 0-7 */ -/* NB: RCVDLY at 0x1050 and LEGOVERIDE at 0x1074 */ - -/* - * Performance Monitoring Unit (CP14) - * - * CP14.0.1 Performance Monitor Control Register(PMNC) - * CP14.1.1 Clock Counter(CCNT) - * CP14.4.1 Interrupt Enable Register(INTEN) - * CP14.5.1 Overflow Flag Register(FLAG) - * CP14.8.1 Event Selection Register(EVTSEL) - * CP14.0.2 Performance Counter Register 0(PMN0) - * CP14.1.2 Performance Counter Register 0(PMN1) - * CP14.2.2 Performance Counter Register 0(PMN2) - * CP14.3.2 Performance Counter Register 0(PMN3) - */ - -#define PMNC_E 0x00000001 /* enable all counters */ -#define PMNC_P 0x00000002 /* reset all PMNs to 0 */ -#define PMNC_C 0x00000004 /* clock counter reset */ -#define PMNC_D 0x00000008 /* clock counter / 64 */ - -#define INTEN_CC_IE 0x00000001 /* enable clock counter interrupt */ -#define INTEN_PMN0_IE 0x00000002 /* enable PMN0 interrupt */ -#define INTEN_PMN1_IE 0x00000004 /* enable PMN1 interrupt */ -#define INTEN_PMN2_IE 0x00000008 /* enable PMN2 interrupt */ -#define INTEN_PMN3_IE 0x00000010 /* enable PMN3 interrupt */ - -#define FLAG_CC_IF 0x00000001 /* clock counter overflow */ -#define FLAG_PMN0_IF 0x00000002 /* PMN0 overflow */ -#define FLAG_PMN1_IF 0x00000004 /* PMN1 overflow */ -#define FLAG_PMN2_IF 0x00000008 /* PMN2 overflow */ -#define FLAG_PMN3_IF 0x00000010 /* PMN3 overflow */ - -#define EVTSEL_EVCNT_MASK 0x0000000ff /* event to count for PMNs */ -#define PMNC_EVCNT0_SHIFT 0 -#define PMNC_EVCNT1_SHIFT 8 -#define PMNC_EVCNT2_SHIFT 16 -#define PMNC_EVCNT3_SHIFT 24 - -/* - * Queue Manager - */ -#define IXP425_QMGR_HWBASE 0x60000000UL -#define IXP425_QMGR_VBASE 0xf0018000UL -#define IXP425_QMGR_SIZE 0x4000 - -/* - * Network Processing Engines (NPE's) and associated Ethernet MAC's. - */ -#define IXP425_NPE_A_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_A_OFFSET) -#define IXP425_NPE_A_VBASE (IXP425_IO_VBASE + IXP425_NPE_A_OFFSET) -#define IXP425_NPE_A_SIZE 0x1000 /* Actually only 256 bytes */ - -#define IXP425_NPE_B_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_B_OFFSET) -#define IXP425_NPE_B_VBASE (IXP425_IO_VBASE + IXP425_NPE_B_OFFSET) -#define IXP425_NPE_B_SIZE 0x1000 /* Actually only 256 bytes */ - -#define IXP425_NPE_C_HWBASE (IXP425_IO_HWBASE + IXP425_NPE_C_OFFSET) -#define IXP425_NPE_C_VBASE (IXP425_IO_VBASE + IXP425_NPE_C_OFFSET) -#define IXP425_NPE_C_SIZE 0x1000 /* Actually only 256 bytes */ - -#define IXP425_MAC_B_HWBASE (IXP425_IO_HWBASE + IXP425_MAC_B_OFFSET) -#define IXP425_MAC_B_VBASE (IXP425_IO_VBASE + IXP425_MAC_B_OFFSET) -#define IXP425_MAC_B_SIZE 0x1000 /* Actually only 256 bytes */ - -#define IXP425_MAC_C_HWBASE (IXP425_IO_HWBASE + IXP425_MAC_C_OFFSET) -#define IXP425_MAC_C_VBASE (IXP425_IO_VBASE + IXP425_MAC_C_OFFSET) -#define IXP425_MAC_C_SIZE 0x1000 /* Actually only 256 bytes */ - -#define IXP435_MAC_A_HWBASE (IXP425_IO_HWBASE + IXP435_MAC_A_OFFSET) -#define IXP435_MAC_A_VBASE (IXP425_IO_VBASE + IXP435_MAC_A_OFFSET) -#define IXP435_MAC_A_SIZE 0x1000 /* Actually only 256 bytes */ - -/* - * Expansion Bus Data Space. - */ -#define IXP425_EXP_BUS_HWBASE 0x50000000UL -#define IXP425_EXP_BUS_SIZE 0x01000000 /* max, typically smaller */ - -#define IXP425_EXP_BUS_CSx_HWBASE(i) \ - (IXP425_EXP_BUS_HWBASE + (i)*IXP425_EXP_BUS_SIZE) -#define IXP425_EXP_BUS_CSx_SIZE 0x1000 -#define IXP425_EXP_BUS_CSx_VBASE(i) \ - (0xF0011000UL + (((i)-1)*IXP425_EXP_BUS_CSx_SIZE)) - -/* NB: CS0 is special; it maps flash */ -#define IXP425_EXP_BUS_CS0_HWBASE IXP425_EXP_BUS_CSx_HWBASE(0) -#define IXP425_EXP_BUS_CS0_VBASE 0xFD000000UL -#ifndef IXP4XX_FLASH_SIZE -#define IXP425_EXP_BUS_CS0_SIZE 0x01000000 /* NB: 16M */ -#else -#define IXP425_EXP_BUS_CS0_SIZE IXP4XX_FLASH_SIZE -#endif -#define IXP425_EXP_BUS_CS1_HWBASE IXP425_EXP_BUS_CSx_HWBASE(1) -#define IXP425_EXP_BUS_CS1_VBASE IXP425_EXP_BUS_CSx_VBASE(1) -#define IXP425_EXP_BUS_CS1_SIZE IXP425_EXP_BUS_CSx_SIZE -#define IXP425_EXP_BUS_CS2_HWBASE IXP425_EXP_BUS_CSx_HWBASE(2) -#define IXP425_EXP_BUS_CS2_VBASE IXP425_EXP_BUS_CSx_VBASE(2) -#define IXP425_EXP_BUS_CS2_SIZE IXP425_EXP_BUS_CSx_SIZE -#define IXP425_EXP_BUS_CS3_HWBASE IXP425_EXP_BUS_CSx_HWBASE(3) -#define IXP425_EXP_BUS_CS3_VBASE IXP425_EXP_BUS_CSx_VBASE(3) -#define IXP425_EXP_BUS_CS3_SIZE IXP425_EXP_BUS_CSx_SIZE -#define IXP425_EXP_BUS_CS4_HWBASE IXP425_EXP_BUS_CSx_HWBASE(4) -#define IXP425_EXP_BUS_CS4_VBASE IXP425_EXP_BUS_CSx_VBASE(4) -#define IXP425_EXP_BUS_CS4_SIZE IXP425_EXP_BUS_CSx_SIZE - -/* NB: not mapped (yet) */ -#define IXP425_EXP_BUS_CS5_HWBASE IXP425_EXP_BUS_CSx_HWBASE(5) -#define IXP425_EXP_BUS_CS6_HWBASE IXP425_EXP_BUS_CSx_HWBASE(6) -#define IXP425_EXP_BUS_CS7_HWBASE IXP425_EXP_BUS_CSx_HWBASE(7) - -/* - * IXP435/Gateworks Cambria - */ -#define IXP435_USB1_HWBASE 0xCD000000UL /* USB host controller 1 */ -#define IXP435_USB1_VBASE 0xF001C000UL -#define IXP435_USB1_SIZE 0x1000 /* NB: only uses 0x300 */ - -#define IXP435_USB2_HWBASE 0xCE000000UL /* USB host controller 2 */ -#define IXP435_USB2_VBASE 0xF001D000UL -#define IXP435_USB2_SIZE 0x1000 /* NB: only uses 0x300 */ - -#define CAMBRIA_GPS_HWBASE 0x53FC0000UL /* optional GPS Serial Port */ -#define CAMBRIA_GPS_VBASE 0xF001E000UL -#define CAMBRIA_GPS_SIZE 0x1000 -#define CAMBRIA_RS485_HWBASE 0x53F80000UL /* optional RS485 Serial Port */ -#define CAMBRIA_RS485_VBASE 0xF001F000UL -#define CAMBRIA_RS485_SIZE 0x1000 - -/* NB: these are mapped on the fly, so no fixed virtual addresses */ -#define CAMBRIA_OCTAL_LED_HWBASE 0x53F40000UL /* Octal Status LED Latch */ -#define CAMBRIA_OCTAL_LED_SIZE 0x1000 -#define CAMBRIA_CFSEL1_HWBASE 0x53E40000UL /* Compact Flash Socket Sel 0 */ -#define CAMBRIA_CFSEL1_SIZE 0x40000 -#define CAMBRIA_CFSEL0_HWBASE 0x53E00000UL /* Compact Flash Socket Sel 1 */ -#define CAMBRIA_CFSEL0_SIZE 0x40000 - -#endif /* _IXP425REG_H_ */ diff --git a/sys/arm/xscale/ixp425/ixp425var.h b/sys/arm/xscale/ixp425/ixp425var.h deleted file mode 100644 index 27d38c15dbf3..000000000000 --- a/sys/arm/xscale/ixp425/ixp425var.h +++ /dev/null @@ -1,124 +0,0 @@ -/* $NetBSD: ixp425var.h,v 1.12 2009/10/21 14:15:51 rmind Exp $ */ - -/*- - * SPDX-License-Identifier: BSD-2-Clause-NetBSD - * - * Copyright (c) 2003 - * Ichiro FUKUHARA . - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - * - */ - -#ifndef _IXP425VAR_H_ -#define _IXP425VAR_H_ - -#include -#include - -#include - -#include - -/* NB: cputype is setup by set_cpufuncs */ -#define cpu_is_ixp42x() (cputype == CPU_ID_IXP425) -#define cpu_is_ixp43x() (cputype == CPU_ID_IXP435) -#define cpu_is_ixp46x() (cputype == CPU_ID_IXP465) - -struct ixp425_softc { - device_t sc_dev; - bus_space_tag_t sc_iot; - bus_space_handle_t sc_gpio_ioh; - bus_space_handle_t sc_exp_ioh; - - u_int32_t sc_intrmask; - - struct rman sc_irq_rman; - struct rman sc_mem_rman; - bus_dma_tag_t sc_dmat; -}; - -void ixp425_set_gpio(struct ixp425_softc *sc, int pin, int type); - -struct ixppcib_softc { - device_t sc_dev; - - u_int sc_bus; - - struct resource *sc_csr; - struct resource *sc_mem; - - struct rman sc_io_rman; - struct rman sc_mem_rman; - struct rman sc_irq_rman; - - struct bus_space sc_pci_memt; - struct bus_space sc_pci_iot; - bus_dma_tag_t sc_dmat; -}; - -#define EXP_BUS_WRITE_4(sc, reg, data) \ - bus_space_write_4(sc->sc_iot, sc->sc_exp_ioh, reg, data) -#define EXP_BUS_READ_4(sc, reg) \ - bus_space_read_4(sc->sc_iot, sc->sc_exp_ioh, reg) - -#define GPIO_CONF_WRITE_4(sc, reg, data) \ - bus_space_write_4(sc->sc_iot, sc->sc_gpio_ioh, reg, data) -#define GPIO_CONF_READ_4(sc, reg) \ - bus_space_read_4(sc->sc_iot, sc->sc_gpio_ioh, reg) -#define IXP4XX_GPIO_LOCK() mtx_lock(&ixp425_gpio_mtx) -#define IXP4XX_GPIO_UNLOCK() mtx_unlock(&ixp425_gpio_mtx) -extern struct mtx ixp425_gpio_mtx; - -extern struct bus_space ixp425_bs_tag; -extern struct bus_space ixp425_a4x_bs_tag; - -extern struct bus_space cambria_exp_bs_tag; -void cambria_exp_bus_init(struct ixp425_softc *); - -void ixp425_io_bs_init(bus_space_tag_t, void *); -void ixp425_mem_bs_init(bus_space_tag_t, void *); - -uint32_t ixp425_sdram_size(void); -uint32_t ixp435_ddram_size(void); -uint32_t ixp4xx_read_feature_bits(void); -void ixp4xx_write_feature_bits(uint32_t); - -int ixp425_md_route_interrupt(device_t, device_t, int); -void ixp425_md_attach(device_t); - -int getvbase(uint32_t, uint32_t, uint32_t *); - -struct ixp425_ivar { - uint32_t addr; - int irq; -}; -#define IXP425_IVAR(d) ((struct ixp425_ivar *) device_get_ivars(d)) - -enum { - IXP425_IVAR_ADDR, /* base physical address */ - IXP425_IVAR_IRQ /* irq/gpio pin assignment */ -}; -#endif /* _IXP425VAR_H_ */ diff --git a/sys/arm/xscale/ixp425/std.avila b/sys/arm/xscale/ixp425/std.avila deleted file mode 100644 index 8f67379345f0..000000000000 --- a/sys/arm/xscale/ixp425/std.avila +++ /dev/null @@ -1,20 +0,0 @@ -#$FreeBSD$ - -# -# Gateworks GW23XX board configuration -# -files "../xscale/ixp425/files.avila" -# -# Physical memory starts at 0. We assume images are loaded at -# 0x200000, e.g. from redboot with load -b 0x200000 kernel. -# -# Redboot is expected to handle unmapping the flash memory that -# appears at 0 on boot. Likewise we expect the expansion bus to -# be remapped away from 0. -# -options PHYSADDR=0x00000000 -makeoptions KERNPHYSADDR=0x00200000 -options KERNVIRTADDR=0xc0200000 # Used in ldscript.arm -makeoptions KERNVIRTADDR=0xc0200000 -options FLASHADDR=0x50000000 -options LOADERRAMADDR=0x00000000 diff --git a/sys/arm/xscale/ixp425/std.ixp425 b/sys/arm/xscale/ixp425/std.ixp425 deleted file mode 100644 index 27d807b77ca3..000000000000 --- a/sys/arm/xscale/ixp425/std.ixp425 +++ /dev/null @@ -1,5 +0,0 @@ -#XScale IXP425 generic configuration -#$FreeBSD$ -files "../xscale/ixp425/files.ixp425" -include "../xscale/std.xscale-be" -cpu CPU_XSCALE_IXP425 diff --git a/sys/arm/xscale/ixp425/std.ixp435 b/sys/arm/xscale/ixp425/std.ixp435 deleted file mode 100644 index c80e3b42311a..000000000000 --- a/sys/arm/xscale/ixp425/std.ixp435 +++ /dev/null @@ -1,7 +0,0 @@ -#XScale IXP435 generic configuration -#$FreeBSD$ - -files "../xscale/ixp425/files.ixp425" -include "../xscale/std.xscale-be" -cpu CPU_XSCALE_IXP435 -cpu CPU_XSCALE_IXP425 diff --git a/sys/arm/xscale/ixp425/uart_bus_ixp425.c b/sys/arm/xscale/ixp425/uart_bus_ixp425.c deleted file mode 100644 index d818371113d8..000000000000 --- a/sys/arm/xscale/ixp425/uart_bus_ixp425.c +++ /dev/null @@ -1,84 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 Kevin Lo. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include -#include - -#include "uart_if.h" - -static int uart_ixp425_probe(device_t dev); - -static device_method_t uart_ixp425_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, uart_ixp425_probe), - DEVMETHOD(device_attach, uart_bus_attach), - DEVMETHOD(device_detach, uart_bus_detach), - { 0, 0 } -}; - -static driver_t uart_ixp425_driver = { - uart_driver_name, - uart_ixp425_methods, - sizeof(struct uart_softc), -}; -DRIVER_MODULE(uart, ixp, uart_ixp425_driver, uart_devclass, 0, 0); - -static int -uart_ixp425_probe(device_t dev) -{ - struct uart_softc *sc; - int unit = device_get_unit(dev); - u_int rclk; - - sc = device_get_softc(dev); - sc->sc_class = &uart_ns8250_class; - if (resource_int_value("uart", unit, "rclk", &rclk)) - rclk = IXP425_UART_FREQ; - if (bootverbose) - device_printf(dev, "rclk %u\n", rclk); - - return uart_bus_probe(dev, 0, 0, rclk, 0, 0); -} diff --git a/sys/arm/xscale/ixp425/uart_cpu_ixp425.c b/sys/arm/xscale/ixp425/uart_cpu_ixp425.c deleted file mode 100644 index ce068f4f5ea8..000000000000 --- a/sys/arm/xscale/ixp425/uart_cpu_ixp425.c +++ /dev/null @@ -1,98 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2003 Marcel Moolenaar - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -bus_space_tag_t uart_bus_space_io; -bus_space_tag_t uart_bus_space_mem; - -int -uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) -{ - return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); -} - -int -uart_cpu_getdev(int devtype, struct uart_devinfo *di) -{ - uint32_t i, ivar, vaddr; - - /* - * Scan the hints. The IXP425 only have 2 serial ports, so only - * scan them. - */ - for (i = 0; i < 2; i++) { - if (resource_int_value("uart", i, "flags", &ivar)) - continue; - if (devtype == UART_DEV_CONSOLE && !UART_FLAGS_CONSOLE(ivar)) - continue; - if (devtype == UART_DEV_DBGPORT && !UART_FLAGS_DBGPORT(ivar)) - continue; - /* - * We have a possible device. Make sure it's enabled and - * that we have an I/O port. - */ - if (resource_int_value("uart", i, "disabled", &ivar) == 0 && - ivar != 0) - continue; - if (resource_int_value("uart", i, "addr", &ivar) != 0 || - ivar == 0) - continue; - /* Got it. Fill in the instance and return it. */ - di->ops = uart_getops(&uart_ns8250_class); - di->bas.chan = 0; - di->bas.bst = &ixp425_a4x_bs_tag; - di->bas.regshft = 0; - di->bas.rclk = IXP425_UART_FREQ; - di->baudrate = 115200; - di->databits = 8; - di->stopbits = 1; - di->parity = UART_PARITY_NONE; - uart_bus_space_io = NULL; - uart_bus_space_mem = &ixp425_a4x_bs_tag; - - getvbase(ivar, IXP425_REG_SIZE, &vaddr); - di->bas.bsh = vaddr; - return (0); - } - - return (ENXIO); -} diff --git a/sys/arm/xscale/std.xscale-be b/sys/arm/xscale/std.xscale-be deleted file mode 100644 index 6ba7a25d871d..000000000000 --- a/sys/arm/xscale/std.xscale-be +++ /dev/null @@ -1,5 +0,0 @@ -#Big-Endian XScale generic configuration -#$FreeBSD$ - -include "../xscale/std.xscale" -machine arm armeb diff --git a/sys/conf/files.arm b/sys/conf/files.arm index 10c86e5ce4ac..9117f5c51024 100644 --- a/sys/conf/files.arm +++ b/sys/conf/files.arm @@ -33,14 +33,14 @@ arm/arm/cpufunc_asm.S standard arm/arm/cpufunc_asm_arm9.S optional cpu_arm9 | cpu_arm9e arm/arm/cpufunc_asm_arm11.S optional cpu_arm1176 arm/arm/cpufunc_asm_arm11x6.S optional cpu_arm1176 -arm/arm/cpufunc_asm_armv4.S optional cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_81342 +arm/arm/cpufunc_asm_armv4.S optional cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_xscale_pxa2x0 | cpu_xscale_81342 arm/arm/cpufunc_asm_armv5_ec.S optional cpu_arm9e arm/arm/cpufunc_asm_armv6.S optional cpu_arm1176 arm/arm/cpufunc_asm_armv7.S optional cpu_cortexa | cpu_krait | cpu_mv_pj4b arm/arm/cpufunc_asm_fa526.S optional cpu_fa526 arm/arm/cpufunc_asm_pj4b.S optional cpu_mv_pj4b arm/arm/cpufunc_asm_sheeva.S optional cpu_arm9e -arm/arm/cpufunc_asm_xscale.S optional cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_81342 +arm/arm/cpufunc_asm_xscale.S optional cpu_xscale_pxa2x0 | cpu_xscale_81342 arm/arm/cpufunc_asm_xscale_c3.S optional cpu_xscale_81342 arm/arm/cpuinfo.c standard arm/arm/cpu_asm-v6.S optional armv7 | armv6 diff --git a/sys/conf/kern.mk b/sys/conf/kern.mk index 00616c7f38ca..910992c3ef7b 100644 --- a/sys/conf/kern.mk +++ b/sys/conf/kern.mk @@ -279,7 +279,6 @@ CFLAGS+= -std=${CSTD} LD_EMULATION_aarch64=aarch64elf LD_EMULATION_amd64=elf_x86_64_fbsd LD_EMULATION_arm=armelf_fbsd -LD_EMULATION_armeb=armelfb_fbsd LD_EMULATION_armv6=armelf_fbsd LD_EMULATION_armv7=armelf_fbsd LD_EMULATION_i386=elf_i386_fbsd diff --git a/sys/conf/options.arm b/sys/conf/options.arm index 3f91b2896e52..0c5809c5f021 100644 --- a/sys/conf/options.arm +++ b/sys/conf/options.arm @@ -17,8 +17,6 @@ CPU_KRAIT opt_global.h CPU_FA526 opt_global.h CPU_MV_PJ4B opt_global.h CPU_XSCALE_81342 opt_global.h -CPU_XSCALE_IXP425 opt_global.h -CPU_XSCALE_IXP435 opt_global.h CPU_XSCALE_PXA2X0 opt_global.h SMP_ON_UP opt_global.h # Runtime detection of MP extensions DEV_GIC opt_global.h @@ -30,7 +28,6 @@ INTRNG opt_global.h IPI_IRQ_START opt_smp.h IPI_IRQ_END opt_smp.h FREEBSD_BOOT_LOADER opt_global.h -IXP4XX_FLASH_SIZE opt_global.h KERNBASE opt_global.h KERNVIRTADDR opt_global.h LINUX_BOOT_ABI opt_global.h diff --git a/sys/dev/cfi/cfi_bus_ixp4xx.c b/sys/dev/cfi/cfi_bus_ixp4xx.c deleted file mode 100644 index dd74f3f4ed0a..000000000000 --- a/sys/dev/cfi/cfi_bus_ixp4xx.c +++ /dev/null @@ -1,82 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2009 Roelof Jonkman, Carlson Wireless Inc. - * Copyright (c) 2009 Sam Leffler, Errno Consulting - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -#include -#include - -static int -cfi_ixp4xx_probe(device_t dev) -{ - struct cfi_softc *sc = device_get_softc(dev); - /* - * NB: we assume the boot loader sets up EXP_TIMING_CS0_OFFSET - * according to the flash on the board. If it does not then it - * can be done here. - */ - if (bootverbose) { - struct ixp425_softc *sa = - device_get_softc(device_get_parent(dev)); - device_printf(dev, "EXP_TIMING_CS0_OFFSET 0x%x\n", - EXP_BUS_READ_4(sa, EXP_TIMING_CS0_OFFSET)); - } - sc->sc_width = 2; /* NB: don't probe interface width */ - return cfi_probe(dev); -} - -static device_method_t cfi_ixp4xx_methods[] = { - /* device interface */ - DEVMETHOD(device_probe, cfi_ixp4xx_probe), - DEVMETHOD(device_attach, cfi_attach), - DEVMETHOD(device_detach, cfi_detach), - - DEVMETHOD_END -}; - -static driver_t cfi_ixp4xx_driver = { - cfi_driver_name, - cfi_ixp4xx_methods, - sizeof(struct cfi_softc), -}; -DRIVER_MODULE(cfi, ixp, cfi_ixp4xx_driver, cfi_devclass, 0, 0); diff --git a/sys/dev/hwpmc/hwpmc_xscale.h b/sys/dev/hwpmc/hwpmc_xscale.h index 112a722c8c03..384586451adb 100644 --- a/sys/dev/hwpmc/hwpmc_xscale.h +++ b/sys/dev/hwpmc/hwpmc_xscale.h @@ -42,9 +42,6 @@ #define XSCALE_PMNC_PMNRESET 0x02 /* Performance Counter Reset */ #define XSCALE_PMNC_CCNTRESET 0x04 /* Clock Counter Reset */ #define XSCALE_PMNC_CCNTDIV 0x08 /* Clock Counter Divider */ -/* IXP425 only -- first generation */ -#define XSCALE_PMNC_EVT0_MASK 0x00ff000 -#define XSCALE_PMNC_EVT1_MASK 0xff00000 #define XSCALE_INTEN_CCNT 0x01 /* Enable Clock Counter Int. */ #define XSCALE_INTEN_PMN0 0x02 /* Enable PMN0 Interrupts */ diff --git a/sys/dev/usb/controller/ehci_ixp4xx.c b/sys/dev/usb/controller/ehci_ixp4xx.c deleted file mode 100644 index 52d45a33b0bd..000000000000 --- a/sys/dev/usb/controller/ehci_ixp4xx.c +++ /dev/null @@ -1,323 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2008 Sam Leffler. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * IXP435 attachment driver for the USB Enhanced Host Controller. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include "opt_bus.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -#define EHCI_VENDORID_IXP4XX 0x42fa05 -#define EHCI_HC_DEVSTR "IXP4XX Integrated USB 2.0 controller" - -struct ixp_ehci_softc { - ehci_softc_t base; /* storage for EHCI code */ - bus_space_tag_t iot; - bus_space_handle_t ioh; - struct bus_space tag; /* tag for private bus space ops */ -}; - -static device_attach_t ehci_ixp_attach; -static device_detach_t ehci_ixp_detach; - -static uint8_t ehci_bs_r_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); -static void ehci_bs_w_1(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, u_int8_t); -static uint16_t ehci_bs_r_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); -static void ehci_bs_w_2(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, uint16_t); -static uint32_t ehci_bs_r_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t); -static void ehci_bs_w_4(bus_space_tag_t tag, bus_space_handle_t, bus_size_t, uint32_t); - -static void -ehci_ixp_post_reset(struct ehci_softc *ehci_softc) -{ - uint32_t usbmode; - - /* Force HOST mode, select big-endian mode */ - usbmode = EOREAD4(ehci_softc, EHCI_USBMODE_NOLPM); - usbmode &= ~EHCI_UM_CM; - usbmode |= EHCI_UM_CM_HOST; - usbmode |= EHCI_UM_ES_BE; - EOWRITE4(ehci_softc, EHCI_USBMODE_NOLPM, usbmode); -} - -static int -ehci_ixp_probe(device_t self) -{ - - device_set_desc(self, EHCI_HC_DEVSTR); - - return (BUS_PROBE_DEFAULT); -} - -static int -ehci_ixp_attach(device_t self) -{ - struct ixp_ehci_softc *isc = device_get_softc(self); - ehci_softc_t *sc = &isc->base; - int err; - int rid; - - /* initialise some bus fields */ - sc->sc_bus.parent = self; - sc->sc_bus.devices = sc->sc_devices; - sc->sc_bus.devices_max = EHCI_MAX_DEVICES; - sc->sc_bus.dma_bits = 32; - - /* get all DMA memory */ - if (usb_bus_mem_alloc_all(&sc->sc_bus, - USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) { - return (ENOMEM); - } - - /* NB: hints fix the memory location and irq */ - - rid = 0; - sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); - if (!sc->sc_io_res) { - device_printf(self, "Could not map memory\n"); - goto error; - } - - /* - * Craft special resource for bus space ops that handle - * byte-alignment of non-word addresses. Also, since - * we're already intercepting bus space ops we handle - * the register window offset that could otherwise be - * done with bus_space_subregion. - */ - isc->iot = rman_get_bustag(sc->sc_io_res); - isc->tag.bs_privdata = isc->iot; - /* read single */ - isc->tag.bs_r_1 = ehci_bs_r_1; - isc->tag.bs_r_2 = ehci_bs_r_2; - isc->tag.bs_r_4 = ehci_bs_r_4; - /* write (single) */ - isc->tag.bs_w_1 = ehci_bs_w_1; - isc->tag.bs_w_2 = ehci_bs_w_2; - isc->tag.bs_w_4 = ehci_bs_w_4; - - sc->sc_io_tag = &isc->tag; - sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); - sc->sc_io_size = IXP435_USB1_SIZE - 0x100; - - rid = 0; - sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, - RF_ACTIVE); - if (sc->sc_irq_res == NULL) { - device_printf(self, "Could not allocate irq\n"); - goto error; - } - sc->sc_bus.bdev = device_add_child(self, "usbus", -1); - if (!sc->sc_bus.bdev) { - device_printf(self, "Could not add USB device\n"); - goto error; - } - device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); - device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR); - - sprintf(sc->sc_vendor, "Intel"); - - - err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, - NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl); - if (err) { - device_printf(self, "Could not setup irq, %d\n", err); - sc->sc_intr_hdl = NULL; - goto error; - } - - /* - * Select big-endian byte alignment and arrange to not terminate - * reset operations (the adapter will ignore it if we do but might - * as well save a reg write). Also, the controller has an embedded - * Transaction Translator which means port speed must be read from - * the Port Status register following a port enable. - */ - sc->sc_flags |= EHCI_SCFLG_TT - | EHCI_SCFLG_BIGEDESC - | EHCI_SCFLG_NORESTERM - ; - - /* Setup callbacks. */ - sc->sc_vendor_post_reset = ehci_ixp_post_reset; - sc->sc_vendor_get_port_speed = ehci_get_port_speed_portsc; - - err = ehci_init(sc); - if (!err) { - err = device_probe_and_attach(sc->sc_bus.bdev); - } - if (err) { - device_printf(self, "USB init failed err=%d\n", err); - goto error; - } - return (0); - -error: - ehci_ixp_detach(self); - return (ENXIO); -} - -static int -ehci_ixp_detach(device_t self) -{ - struct ixp_ehci_softc *isc = device_get_softc(self); - ehci_softc_t *sc = &isc->base; - int err; - - /* during module unload there are lots of children leftover */ - device_delete_children(self); - - if (sc->sc_irq_res && sc->sc_intr_hdl) { - /* - * only call ehci_detach() after ehci_init() - */ - ehci_detach(sc); - - err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); - - if (err) - /* XXX or should we panic? */ - device_printf(self, "Could not tear down irq, %d\n", - err); - sc->sc_intr_hdl = NULL; - } - - if (sc->sc_irq_res) { - bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res); - sc->sc_irq_res = NULL; - } - if (sc->sc_io_res) { - bus_release_resource(self, SYS_RES_MEMORY, 0, - sc->sc_io_res); - sc->sc_io_res = NULL; - } - usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc); - - return (0); -} - -/* - * Bus space accessors for PIO operations. - */ - -static uint8_t -ehci_bs_r_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o) -{ - return bus_space_read_1((bus_space_tag_t)tag->bs_privdata, h, - 0x100 + (o &~ 3) + (3 - (o & 3))); -} - -static void -ehci_bs_w_1(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, u_int8_t v) -{ - panic("%s", __func__); -} - -static uint16_t -ehci_bs_r_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o) -{ - return bus_space_read_2((bus_space_tag_t)tag->bs_privdata, h, - 0x100 + (o &~ 3) + (2 - (o & 3))); -} - -static void -ehci_bs_w_2(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, uint16_t v) -{ - panic("%s", __func__); -} - -static uint32_t -ehci_bs_r_4(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o) -{ - return bus_space_read_4((bus_space_tag_t) tag->bs_privdata, h, 0x100 + o); -} - -static void -ehci_bs_w_4(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t o, uint32_t v) -{ - bus_space_write_4((bus_space_tag_t) tag->bs_privdata, h, 0x100 + o, v); -} - -static device_method_t ehci_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, ehci_ixp_probe), - DEVMETHOD(device_attach, ehci_ixp_attach), - DEVMETHOD(device_detach, ehci_ixp_detach), - DEVMETHOD(device_suspend, bus_generic_suspend), - DEVMETHOD(device_resume, bus_generic_resume), - DEVMETHOD(device_shutdown, bus_generic_shutdown), - - DEVMETHOD_END -}; - -static driver_t ehci_driver = { - "ehci", - ehci_methods, - sizeof(struct ixp_ehci_softc), -}; - -static devclass_t ehci_devclass; - -DRIVER_MODULE(ehci, ixp, ehci_driver, ehci_devclass, 0, 0); -MODULE_DEPEND(ehci, usb, 1, 1, 1); diff --git a/sys/modules/cfi/Makefile b/sys/modules/cfi/Makefile index 59ec4d693df7..6f8a8af4ab4b 100644 --- a/sys/modules/cfi/Makefile +++ b/sys/modules/cfi/Makefile @@ -3,16 +3,9 @@ .PATH: ${SRCTOP}/sys/dev/cfi KMOD= cfi -SRCS= ${_cfi_bus} cfi_core.c cfi_dev.c +SRCS= cfi_bus_fdt.c ofw_bus_if.h cfi_core.c cfi_dev.c SRCS+= bus_if.h device_if.h opt_cfi.h -.if ${MACHINE} == "arm" -_cfi_bus= cfi_bus_fdt.c cfi_bus_ixp4xx.c ofw_bus_if.h -.endif -.if ${MACHINE} == "powerpc" -_cfi_bus= cfi_bus_fdt.c ofw_bus_if.h -.endif - opt_cfi.h: echo "#define CFI_SUPPORT_STRATAFLASH 1" > ${.TARGET}