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x86: Support multiple PCI MCFG regions
In particular, this enables support for PCI config access for domains (segments) other than 0. Reported by: cperciva Tested by: cperciva (m7i.metal-48xl AWS instance) Reviewed by: imp Relnotes: yes Differential Revision: https://reviews.freebsd.org/D42828
This commit is contained in:
John Baldwin
parent
9893a4fd31
commit
f54a3890b1
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@ -33,6 +33,7 @@
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/sysctl.h>
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#include <dev/pci/pcivar.h>
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@ -41,12 +42,21 @@
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#include <vm/pmap.h>
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#include <machine/pci_cfgreg.h>
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struct pcie_mcfg_region {
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char *base;
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uint16_t domain;
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uint8_t minbus;
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uint8_t maxbus;
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};
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static uint32_t pci_docfgregread(int domain, int bus, int slot, int func,
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int reg, int bytes);
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static int pciereg_cfgread(int domain, int bus, unsigned slot,
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unsigned func, unsigned reg, unsigned bytes);
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static void pciereg_cfgwrite(int domain, int bus, unsigned slot,
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unsigned func, unsigned reg, int data, unsigned bytes);
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static struct pcie_mcfg_region *pcie_lookup_region(int domain, int bus);
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static int pciereg_cfgread(struct pcie_mcfg_region *region, int bus,
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unsigned slot, unsigned func, unsigned reg, unsigned bytes);
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static void pciereg_cfgwrite(struct pcie_mcfg_region *region, int bus,
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unsigned slot, unsigned func, unsigned reg, int data,
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unsigned bytes);
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static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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@ -59,11 +69,12 @@ SYSCTL_DECL(_hw_pci);
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*/
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int cfgmech = CFGMECH_1;
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static vm_offset_t pcie_base;
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static int pcie_minbus, pcie_maxbus;
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static struct pcie_mcfg_region *mcfg_regions;
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static int mcfg_numregions;
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static uint32_t pcie_badslots;
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static struct mtx pcicfg_mtx;
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MTX_SYSINIT(pcicfg_mtx, &pcicfg_mtx, "pcicfg_mtx", MTX_SPIN);
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static int mcfg_enable = 1;
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SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0,
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"Enable support for PCI-e memory mapped config access");
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@ -75,16 +86,33 @@ pci_cfgregopen(void)
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return (1);
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}
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static struct pcie_mcfg_region *
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pcie_lookup_region(int domain, int bus)
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{
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for (int i = 0; i < mcfg_numregions; i++)
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if (mcfg_regions[i].domain == domain &&
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bus >= mcfg_regions[i].minbus &&
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bus <= mcfg_regions[i].maxbus)
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return (&mcfg_regions[i]);
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return (NULL);
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}
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static uint32_t
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pci_docfgregread(int domain, int bus, int slot, int func, int reg, int bytes)
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{
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if (domain == 0 && bus == 0 && (1 << slot & pcie_badslots) != 0)
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return (pcireg_cfgread(bus, slot, func, reg, bytes));
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if (cfgmech == CFGMECH_PCIE &&
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(bus >= pcie_minbus && bus <= pcie_maxbus))
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return (pciereg_cfgread(domain, bus, slot, func, reg, bytes));
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else if (domain == 0)
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if (cfgmech == CFGMECH_PCIE) {
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struct pcie_mcfg_region *region;
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region = pcie_lookup_region(domain, bus);
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if (region != NULL)
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return (pciereg_cfgread(region, bus, slot, func, reg,
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bytes));
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}
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if (domain == 0)
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return (pcireg_cfgread(bus, slot, func, reg, bytes));
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else
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return (-1);
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@ -128,10 +156,18 @@ pci_cfgregwrite(int domain, int bus, int slot, int func, int reg, uint32_t data,
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return;
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}
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if (cfgmech == CFGMECH_PCIE &&
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(bus >= pcie_minbus && bus <= pcie_maxbus))
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pciereg_cfgwrite(domain, bus, slot, func, reg, data, bytes);
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else if (domain == 0)
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if (cfgmech == CFGMECH_PCIE) {
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struct pcie_mcfg_region *region;
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region = pcie_lookup_region(domain, bus);
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if (region != NULL) {
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pciereg_cfgwrite(region, bus, slot, func, reg, data,
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bytes);
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return;
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}
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}
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if (domain == 0)
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
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}
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@ -217,7 +253,7 @@ pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes)
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}
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static void
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pcie_init_badslots(void)
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pcie_init_badslots(struct pcie_mcfg_region *region)
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{
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uint32_t val1, val2;
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int slot;
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@ -234,7 +270,7 @@ pcie_init_badslots(void)
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if (val1 == 0xffffffff)
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continue;
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val2 = pciereg_cfgread(0, 0, slot, 0, 0, 4);
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val2 = pciereg_cfgread(region, 0, slot, 0, 0, 4);
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if (val2 != val1)
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pcie_badslots |= (1 << slot);
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}
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@ -242,26 +278,34 @@ pcie_init_badslots(void)
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}
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int
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pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
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pcie_cfgregopen(uint64_t base, uint16_t domain, uint8_t minbus, uint8_t maxbus)
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{
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struct pcie_mcfg_region *region;
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if (!mcfg_enable)
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return (0);
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if (minbus != 0)
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return (0);
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if (bootverbose)
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printf("PCIe: Memory Mapped configuration base @ 0x%lx\n",
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base);
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printf("PCI: MCFG domain %u bus %u-%u base @ 0x%lx\n",
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domain, minbus, maxbus, base);
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/* Resize the array. */
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mcfg_regions = realloc(mcfg_regions,
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sizeof(*mcfg_regions) * (mcfg_numregions + 1), M_DEVBUF, M_WAITOK);
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region = &mcfg_regions[mcfg_numregions];
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/* XXX: We should make sure this really fits into the direct map. */
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pcie_base = (vm_offset_t)pmap_mapdev_pciecfg(base, (maxbus + 1) << 20);
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pcie_minbus = minbus;
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pcie_maxbus = maxbus;
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region->base = pmap_mapdev_pciecfg(base, (maxbus + 1 - minbus) << 20);
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region->domain = domain;
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region->minbus = minbus;
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region->maxbus = maxbus;
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mcfg_numregions++;
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cfgmech = CFGMECH_PCIE;
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pcie_init_badslots();
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if (domain == 0 && minbus == 0)
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pcie_init_badslots(region);
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return (1);
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}
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@ -282,17 +326,18 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
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*/
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static int
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pciereg_cfgread(int domain, int bus, unsigned slot, unsigned func, unsigned reg,
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unsigned bytes)
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pciereg_cfgread(struct pcie_mcfg_region *region, int bus, unsigned slot,
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unsigned func, unsigned reg, unsigned bytes)
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{
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vm_offset_t va;
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char *va;
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int data = -1;
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if (domain != 0 || bus < pcie_minbus || bus > pcie_maxbus ||
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slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)
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MPASS(bus >= region->minbus && bus <= region->maxbus);
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if (slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)
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return (-1);
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va = PCIE_VADDR(pcie_base, reg, bus, slot, func);
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va = PCIE_VADDR(region->base, reg, bus - region->minbus, slot, func);
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switch (bytes) {
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case 4:
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@ -313,16 +358,17 @@ pciereg_cfgread(int domain, int bus, unsigned slot, unsigned func, unsigned reg,
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}
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static void
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pciereg_cfgwrite(int domain, int bus, unsigned slot, unsigned func,
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unsigned reg, int data, unsigned bytes)
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pciereg_cfgwrite(struct pcie_mcfg_region *region, int bus, unsigned slot,
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unsigned func, unsigned reg, int data, unsigned bytes)
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{
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vm_offset_t va;
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char *va;
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if (domain != 0 || bus < pcie_minbus || bus > pcie_maxbus ||
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slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)
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MPASS(bus >= region->minbus && bus <= region->maxbus);
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if (slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)
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return;
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va = PCIE_VADDR(pcie_base, reg, bus, slot, func);
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va = PCIE_VADDR(region->base, reg, bus - region->minbus, slot, func);
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switch (bytes) {
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case 4:
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@ -2226,11 +2226,8 @@ acpi_enable_pcie(void)
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end = (ACPI_MCFG_ALLOCATION *)((char *)hdr + hdr->Length);
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alloc = (ACPI_MCFG_ALLOCATION *)((ACPI_TABLE_MCFG *)hdr + 1);
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while (alloc < end) {
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if (alloc->PciSegment == 0) {
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pcie_cfgregopen(alloc->Address, alloc->StartBusNumber,
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alloc->EndBusNumber);
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return;
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}
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pcie_cfgregopen(alloc->Address, alloc->PciSegment,
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alloc->StartBusNumber, alloc->EndBusNumber);
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alloc++;
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}
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#endif
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@ -54,6 +54,13 @@
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printf a ; \
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} while(0)
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struct pcie_mcfg_region {
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uint64_t base;
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uint16_t domain;
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uint8_t minbus;
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uint8_t maxbus;
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};
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#define PCIE_CACHE 8
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struct pcie_cfg_elem {
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TAILQ_ENTRY(pcie_cfg_elem) elem;
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@ -63,26 +70,30 @@ struct pcie_cfg_elem {
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SYSCTL_DECL(_hw_pci);
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static struct pcie_mcfg_region *mcfg_regions;
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static int mcfg_numregions;
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static TAILQ_HEAD(pcie_cfg_list, pcie_cfg_elem) pcie_list[MAXCPU];
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static uint64_t pcie_base;
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static int pcie_minbus, pcie_maxbus;
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static int pcie_cache_initted;
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static uint32_t pcie_badslots;
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int cfgmech;
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static int devmax;
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static struct mtx pcicfg_mtx;
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static int mcfg_enable = 1;
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SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0,
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"Enable support for PCI-e memory mapped config access");
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static uint32_t pci_docfgregread(int domain, int bus, int slot, int func,
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int reg, int bytes);
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static struct pcie_mcfg_region *pcie_lookup_region(int domain, int bus);
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static int pcireg_cfgread(int bus, int slot, int func, int reg, int bytes);
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static void pcireg_cfgwrite(int bus, int slot, int func, int reg, int data, int bytes);
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static int pcireg_cfgopen(void);
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static int pciereg_cfgread(int domain, int bus, unsigned slot,
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unsigned func, unsigned reg, unsigned bytes);
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static void pciereg_cfgwrite(int domain, int bus, unsigned slot,
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unsigned func, unsigned reg, int data, unsigned bytes);
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static int pciereg_cfgread(struct pcie_mcfg_region *region, int bus,
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unsigned slot, unsigned func, unsigned reg, unsigned bytes);
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static void pciereg_cfgwrite(struct pcie_mcfg_region *region, int bus,
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unsigned slot, unsigned func, unsigned reg, int data,
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unsigned bytes);
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/*
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* Some BIOS writers seem to want to ignore the spec and put
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@ -149,16 +160,33 @@ pci_cfgregopen(void)
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return (1);
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}
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static struct pcie_mcfg_region *
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pcie_lookup_region(int domain, int bus)
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{
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for (int i = 0; i < mcfg_numregions; i++)
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if (mcfg_regions[i].domain == domain &&
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bus >= mcfg_regions[i].minbus &&
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bus <= mcfg_regions[i].maxbus)
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return (&mcfg_regions[i]);
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return (NULL);
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}
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static uint32_t
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pci_docfgregread(int domain, int bus, int slot, int func, int reg, int bytes)
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{
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if (domain == 0 && bus == 0 && (1 << slot & pcie_badslots) != 0)
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return (pcireg_cfgread(bus, slot, func, reg, bytes));
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if (cfgmech == CFGMECH_PCIE &&
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(bus >= pcie_minbus && bus <= pcie_maxbus))
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return (pciereg_cfgread(domain, bus, slot, func, reg, bytes));
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else if (domain == 0)
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if (cfgmech == CFGMECH_PCIE) {
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struct pcie_mcfg_region *region;
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region = pcie_lookup_region(domain, bus);
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if (region != NULL)
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return (pciereg_cfgread(region, bus, slot, func, reg,
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bytes));
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}
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if (domain == 0)
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return (pcireg_cfgread(bus, slot, func, reg, bytes));
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else
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return (-1);
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@ -197,10 +225,18 @@ pci_cfgregwrite(int domain, int bus, int slot, int func, int reg, uint32_t data,
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return;
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}
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if (cfgmech == CFGMECH_PCIE &&
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(bus >= pcie_minbus && bus <= pcie_maxbus))
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pciereg_cfgwrite(domain, bus, slot, func, reg, data, bytes);
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else if (domain == 0)
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if (cfgmech == CFGMECH_PCIE) {
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struct pcie_mcfg_region *region;
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region = pcie_lookup_region(domain, bus);
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if (region != NULL) {
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pciereg_cfgwrite(region, bus, slot, func, reg, data,
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bytes);
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return;
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}
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}
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if (domain == 0)
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pcireg_cfgwrite(bus, slot, func, reg, data, bytes);
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}
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@ -479,7 +515,7 @@ pcie_init_cache(void)
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}
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static void
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pcie_init_badslots(void)
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pcie_init_badslots(struct pcie_mcfg_region *region)
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{
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uint32_t val1, val2;
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int slot;
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@ -496,7 +532,7 @@ pcie_init_badslots(void)
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if (val1 == 0xffffffff)
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continue;
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val2 = pciereg_cfgread(0, 0, slot, 0, 0, 4);
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val2 = pciereg_cfgread(region, 0, slot, 0, 0, 4);
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if (val2 != val1)
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pcie_badslots |= (1 << slot);
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}
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@ -504,37 +540,51 @@ pcie_init_badslots(void)
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}
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int
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pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
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pcie_cfgregopen(uint64_t base, uint16_t domain, uint8_t minbus, uint8_t maxbus)
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{
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struct pcie_mcfg_region *region;
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if (!mcfg_enable)
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return (0);
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if (minbus != 0)
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return (0);
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if (!pae_mode && base >= 0x100000000) {
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if (bootverbose)
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printf(
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"PCI: Memory Mapped PCI configuration area base 0x%jx too high\n",
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(uintmax_t)base);
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"PCI: MCFG domain %u bus %u-%u base 0x%jx too high\n",
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domain, minbus, maxbus, (uintmax_t)base);
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return (0);
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}
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if (bootverbose)
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printf("PCIe: Memory Mapped configuration base @ 0x%jx\n",
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(uintmax_t)base);
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printf("PCI: MCFG domain %u bus %u-%u base @ 0x%jx\n",
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domain, minbus, maxbus, (uintmax_t)base);
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if (!pcie_init_cache())
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if (pcie_cache_initted == 0) {
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if (!pcie_init_cache())
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pcie_cache_initted = -1;
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else
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pcie_cache_initted = 1;
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}
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if (pcie_cache_initted == -1)
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return (0);
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pcie_base = base;
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pcie_minbus = minbus;
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pcie_maxbus = maxbus;
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/* Resize the array. */
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mcfg_regions = realloc(mcfg_regions,
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sizeof(*mcfg_regions) * (mcfg_numregions + 1), M_DEVBUF, M_WAITOK);
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region = &mcfg_regions[mcfg_numregions];
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region->base = base;
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region->domain = domain;
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region->minbus = minbus;
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region->maxbus = maxbus;
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mcfg_numregions++;
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cfgmech = CFGMECH_PCIE;
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devmax = 32;
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pcie_init_badslots();
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if (domain == 0 && minbus == 0)
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pcie_init_badslots(region);
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return (1);
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}
|
||||
|
|
@ -547,13 +597,16 @@ pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus)
|
|||
((reg) & 0xfff)))
|
||||
|
||||
static __inline vm_offset_t
|
||||
pciereg_findaddr(int bus, unsigned slot, unsigned func, unsigned reg)
|
||||
pciereg_findaddr(struct pcie_mcfg_region *region, int bus, unsigned slot,
|
||||
unsigned func, unsigned reg)
|
||||
{
|
||||
struct pcie_cfg_list *pcielist;
|
||||
struct pcie_cfg_elem *elem;
|
||||
vm_paddr_t pa, papage;
|
||||
|
||||
pa = PCIE_PADDR(pcie_base, reg, bus, slot, func);
|
||||
MPASS(bus >= region->minbus && bus <= region->maxbus);
|
||||
|
||||
pa = PCIE_PADDR(region->base, reg, bus - region->minbus, slot, func);
|
||||
papage = pa & ~PAGE_MASK;
|
||||
|
||||
/*
|
||||
|
|
@ -594,18 +647,17 @@ pciereg_findaddr(int bus, unsigned slot, unsigned func, unsigned reg)
|
|||
*/
|
||||
|
||||
static int
|
||||
pciereg_cfgread(int domain, int bus, unsigned slot, unsigned func, unsigned reg,
|
||||
unsigned bytes)
|
||||
pciereg_cfgread(struct pcie_mcfg_region *region, int bus, unsigned slot,
|
||||
unsigned func, unsigned reg, unsigned bytes)
|
||||
{
|
||||
vm_offset_t va;
|
||||
int data = -1;
|
||||
|
||||
if (domain != 0 || bus < pcie_minbus || bus > pcie_maxbus ||
|
||||
slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)
|
||||
if (slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)
|
||||
return (-1);
|
||||
|
||||
critical_enter();
|
||||
va = pciereg_findaddr(bus, slot, func, reg);
|
||||
va = pciereg_findaddr(region, bus, slot, func, reg);
|
||||
|
||||
switch (bytes) {
|
||||
case 4:
|
||||
|
|
@ -627,17 +679,16 @@ pciereg_cfgread(int domain, int bus, unsigned slot, unsigned func, unsigned reg,
|
|||
}
|
||||
|
||||
static void
|
||||
pciereg_cfgwrite(int domain, int bus, unsigned slot, unsigned func,
|
||||
unsigned reg, int data, unsigned bytes)
|
||||
pciereg_cfgwrite(struct pcie_mcfg_region *region, int bus, unsigned slot,
|
||||
unsigned func, unsigned reg, int data, unsigned bytes)
|
||||
{
|
||||
vm_offset_t va;
|
||||
|
||||
if (domain != 0 || bus < pcie_minbus || bus > pcie_maxbus ||
|
||||
slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)
|
||||
if (slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > PCIE_REGMAX)
|
||||
return;
|
||||
|
||||
critical_enter();
|
||||
va = pciereg_findaddr(bus, slot, func, reg);
|
||||
va = pciereg_findaddr(region, bus, slot, func, reg);
|
||||
|
||||
switch (bytes) {
|
||||
case 4:
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ enum {
|
|||
extern int cfgmech;
|
||||
|
||||
rman_res_t hostb_alloc_start(int type, rman_res_t start, rman_res_t end, rman_res_t count);
|
||||
int pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus);
|
||||
int pcie_cfgregopen(uint64_t base, uint16_t domain, uint8_t minbus, uint8_t maxbus);
|
||||
int pci_cfgregopen(void);
|
||||
u_int32_t pci_cfgregread(int domain, int bus, int slot, int func, int reg, int bytes);
|
||||
void pci_cfgregwrite(int domain, int bus, int slot, int func, int reg, u_int32_t data, int bytes);
|
||||
|
|
|
|||
|
|
@ -133,14 +133,14 @@ legacy_pci_cfgregopen(device_t dev)
|
|||
case 0x3592:
|
||||
/* Intel 7520 or 7320 */
|
||||
pciebar = pci_cfgregread(0, 0, 0, 0, 0xce, 2) << 16;
|
||||
pcie_cfgregopen(pciebar, 0, 255);
|
||||
pcie_cfgregopen(pciebar, 0, 0, 255);
|
||||
break;
|
||||
case 0x2580:
|
||||
case 0x2584:
|
||||
case 0x2590:
|
||||
/* Intel 915, 925, or 915GM */
|
||||
pciebar = pci_cfgregread(0, 0, 0, 0, 0x48, 4);
|
||||
pcie_cfgregopen(pciebar, 0, 255);
|
||||
pcie_cfgregopen(pciebar, 0, 0, 255);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue