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https://github.com/freebsd/freebsd-src
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bhyve: Add PL011 UART emulation
This will be use for arm64 guests, instead of the existing ns16550 UART model. Reviewed by: corvink, jhb MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D40997
This commit is contained in:
Andrew Turner
Mark Johnston
parent
afc10f8bba
commit
f3003a0dfb
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@ -32,6 +32,7 @@
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#define UART_NS16550_IO_BAR_SIZE 8
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struct uart_ns16550_softc;
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struct uart_pl011_softc;
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struct vm_snapshot_meta;
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typedef void (*uart_intr_func_t)(void *arg);
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@ -49,4 +50,12 @@ int uart_ns16550_tty_open(struct uart_ns16550_softc *sc,
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int uart_ns16550_snapshot(struct uart_ns16550_softc *sc,
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struct vm_snapshot_meta *meta);
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#endif
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#endif
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uint32_t uart_pl011_read(struct uart_pl011_softc *sc, int offset);
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void uart_pl011_write(struct uart_pl011_softc *sc, int offset,
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uint32_t value);
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struct uart_pl011_softc *uart_pl011_init(uart_intr_func_t intr_assert,
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uart_intr_func_t intr_deassert, void *arg);
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int uart_pl011_tty_open(struct uart_pl011_softc *sc, const char *device);
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#endif /* _UART_EMUL_H_ */
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394
usr.sbin/bhyve/uart_pl011.c
Normal file
394
usr.sbin/bhyve/uart_pl011.c
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@ -0,0 +1,394 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2020 Andrew Turner
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*
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* This work was supported by Innovate UK project 105694, "Digital Security
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* by Design (DSbD) Technology Platform Prototype".
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <assert.h>
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#include <pthread.h>
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#include <stdbool.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include "uart_backend.h"
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#include "uart_emul.h"
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#define UART_FIFO_SIZE 16
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#define UARTDR 0x00
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#define UARTDR_RSR_SHIFT 8
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#define UARTRSR 0x01
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#define UARTRSR_OE (1 << 3)
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#define UARTFR 0x06
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#define UARTFR_TXFE (1 << 7)
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#define UARTFR_RXFF (1 << 6)
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#define UARTFR_TXFF (1 << 5)
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#define UARTFR_RXFE (1 << 4)
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#define UARTRTINTR (1 << 6)
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#define UARTTXINTR (1 << 5)
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#define UARTRXINTR (1 << 4)
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#define UARTIBRD 0x09
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#define UARTFBRD 0x0a
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#define UARTFBRD_MASK 0x003f
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#define UARTLCR_H 0x0b
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#define UARTLCR_H_MASK 0x00ff
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#define UARTLCR_H_FEN (1 << 4)
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#define UARTCR 0x0c
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/* TODO: Check the flags in the UARTCR register */
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#define UARTCR_MASK 0xffc7
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#define UARTCR_LBE (1 << 7)
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#define UARTIFLS 0x0d
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#define UARTIFLS_MASK 0x003f
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#define UARTIFLS_RXIFLSEL(x) (((x) >> 3) & 0x7)
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#define UARTIFLS_TXIFLSEL(x) (((x) >> 0) & 0x7)
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#define UARTIMSC 0x0e
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#define UARTIMSC_MASK 0x07ff
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#define UARTRIS 0x0f
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#define UARTMIS 0x10
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#define UARTICR 0x11
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#define UARTPeriphID 0x00241011
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#define UARTPeriphID0 0x3f8
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#define UARTPeriphID0_VAL (((UARTPeriphID) >> 0) & 0xff)
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#define UARTPeriphID1 0x3f9
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#define UARTPeriphID1_VAL (((UARTPeriphID) >> 8) & 0xff)
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#define UARTPeriphID2 0x3fa
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#define UARTPeriphID2_VAL (((UARTPeriphID) >> 16) & 0xff)
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#define UARTPeriphID3 0x3fb
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#define UARTPeriphID3_VAL (((UARTPeriphID) >> 24) & 0xff)
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#define UARTPCellID 0xb105f00d
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#define UARTPCellID0 0x3fc
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#define UARTPCellID0_VAL (((UARTPCellID) >> 0) & 0xff)
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#define UARTPCellID1 0x3fd
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#define UARTPCellID1_VAL (((UARTPCellID) >> 8) & 0xff)
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#define UARTPCellID2 0x3fe
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#define UARTPCellID2_VAL (((UARTPCellID) >> 16) & 0xff)
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#define UARTPCellID3 0x3ff
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#define UARTPCellID3_VAL (((UARTPCellID) >> 24) & 0xff)
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struct uart_pl011_softc {
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struct uart_softc *backend;
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pthread_mutex_t mtx; /* protects all softc elements */
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uint16_t irq_state;
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uint16_t rsr;
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uint16_t cr;
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uint16_t ifls;
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uint16_t imsc;
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uint16_t lcr_h;
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uint16_t ibrd;
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uint16_t fbrd;
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void *arg;
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uart_intr_func_t intr_assert;
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uart_intr_func_t intr_deassert;
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};
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static void
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uart_reset(struct uart_pl011_softc *sc)
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{
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sc->ifls = 0x12;
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/* no fifo until enabled by software */
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uart_rxfifo_reset(sc->backend, 1);
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}
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static int
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uart_rx_trigger_level(struct uart_pl011_softc *sc)
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{
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/* If the FIFO is disabled trigger when we have any data */
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if ((sc->lcr_h & UARTLCR_H_FEN) != 0)
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return (1);
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/* Trigger base on how full the fifo is */
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switch (UARTIFLS_RXIFLSEL(sc->ifls)) {
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case 0:
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return (UART_FIFO_SIZE / 8);
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case 1:
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return (UART_FIFO_SIZE / 4);
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case 2:
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return (UART_FIFO_SIZE / 2);
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case 3:
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return (UART_FIFO_SIZE * 3 / 4);
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case 4:
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return (UART_FIFO_SIZE * 7 / 8);
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default:
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/* TODO: Find out what happens in this case */
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return (UART_FIFO_SIZE);
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}
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}
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static void
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uart_toggle_intr(struct uart_pl011_softc *sc)
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{
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if ((sc->irq_state & sc->imsc) == 0)
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(*sc->intr_deassert)(sc->arg);
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else
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(*sc->intr_assert)(sc->arg);
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}
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static void
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uart_drain(int fd __unused, enum ev_type ev, void *arg)
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{
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struct uart_pl011_softc *sc;
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int old_size, trig_lvl;
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bool loopback;
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sc = arg;
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assert(ev == EVF_READ);
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/*
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* This routine is called in the context of the mevent thread
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* to take out the softc lock to protect against concurrent
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* access from a vCPU i/o exit
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*/
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pthread_mutex_lock(&sc->mtx);
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old_size = uart_rxfifo_numchars(sc->backend);
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loopback = (sc->cr & UARTCR_LBE) != 0;
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uart_rxfifo_drain(sc->backend, loopback);
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/* If we cross the trigger level raise UARTRXINTR */
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trig_lvl = uart_rx_trigger_level(sc);
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if (old_size < trig_lvl &&
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uart_rxfifo_numchars(sc->backend) >= trig_lvl)
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sc->irq_state |= UARTRXINTR;
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if (uart_rxfifo_numchars(sc->backend) > 0)
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sc->irq_state |= UARTRTINTR;
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if (!loopback)
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uart_toggle_intr(sc);
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pthread_mutex_unlock(&sc->mtx);
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}
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void
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uart_pl011_write(struct uart_pl011_softc *sc, int offset, uint32_t value)
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{
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bool loopback;
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pthread_mutex_lock(&sc->mtx);
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switch (offset) {
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case UARTDR:
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loopback = (sc->cr & UARTCR_LBE) != 0;
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if (uart_rxfifo_putchar(sc->backend, value & 0xff, loopback))
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sc->rsr |= UARTRSR_OE;
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/* We don't have a TX fifo, so trigger when we have data */
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sc->irq_state |= UARTTXINTR;
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break;
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case UARTRSR:
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/* Any write clears this register */
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sc->rsr = 0;
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break;
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case UARTFR:
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/* UARTFR is a read-only register */
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break;
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/* TODO: UARTILPR */
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case UARTIBRD:
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sc->ibrd = value;
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break;
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case UARTFBRD:
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sc->fbrd = value & UARTFBRD_MASK;
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break;
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case UARTLCR_H:
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/* Check if the FIFO enable bit changed */
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if (((sc->lcr_h ^ value) & UARTLCR_H_FEN) != 0) {
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if ((value & UARTLCR_H_FEN) != 0) {
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uart_rxfifo_reset(sc->backend, UART_FIFO_SIZE);
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} else {
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uart_rxfifo_reset(sc->backend, 1);
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}
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}
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sc->lcr_h = value & UARTLCR_H_MASK;
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break;
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case UARTCR:
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sc->cr = value & UARTCR_MASK;
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break;
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case UARTIFLS:
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sc->ifls = value & UARTCR_MASK;
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break;
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case UARTIMSC:
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sc->imsc = value & UARTIMSC_MASK;
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break;
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case UARTRIS:
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case UARTMIS:
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/* UARTRIS and UARTMIS are read-only registers */
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break;
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case UARTICR:
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sc->irq_state &= ~value;
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break;
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default:
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/* Ignore writes to unassigned/ID registers */
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break;
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}
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uart_toggle_intr(sc);
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pthread_mutex_unlock(&sc->mtx);
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}
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uint32_t
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uart_pl011_read(struct uart_pl011_softc *sc, int offset)
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{
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uint32_t reg;
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int fifo_sz;
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reg = 0;
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pthread_mutex_lock(&sc->mtx);
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switch (offset) {
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case UARTDR:
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reg = uart_rxfifo_getchar(sc->backend);
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/* Deassert the irq if below the trigger level */
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fifo_sz = uart_rxfifo_numchars(sc->backend);
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if (fifo_sz < uart_rx_trigger_level(sc))
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sc->irq_state &= ~UARTRXINTR;
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if (fifo_sz == 0)
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sc->irq_state &= ~UARTRTINTR;
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reg |= sc->rsr << UARTDR_RSR_SHIFT;
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/* After reading from the fifo there is now space in it */
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sc->rsr &= UARTRSR_OE;
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break;
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case UARTRSR:
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/* Any write clears this register */
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reg = sc->rsr;
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break;
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case UARTFR:
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/* Transmit is intstant, so the fifo is always empty */
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reg = UARTFR_TXFE;
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/* Set the receive fifo full/empty flags */
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fifo_sz = uart_rxfifo_numchars(sc->backend);
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if (fifo_sz == UART_FIFO_SIZE)
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reg |= UARTFR_RXFF;
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else if (fifo_sz == 0)
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reg |= UARTFR_RXFE;
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break;
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/* TODO: UARTILPR */
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case UARTIBRD:
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reg = sc->ibrd;
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break;
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case UARTFBRD:
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reg = sc->fbrd;
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break;
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case UARTLCR_H:
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reg = sc->lcr_h;
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break;
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case UARTCR:
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reg = sc->cr;
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break;
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case UARTIMSC:
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reg = sc->imsc;
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break;
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case UARTRIS:
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reg = sc->irq_state;
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break;
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case UARTMIS:
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reg = sc->irq_state & sc->imsc;
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break;
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case UARTICR:
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reg = 0;
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break;
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case UARTPeriphID0:
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reg = UARTPeriphID0_VAL;
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break;
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case UARTPeriphID1:
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reg =UARTPeriphID1_VAL;
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break;
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case UARTPeriphID2:
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reg = UARTPeriphID2_VAL;
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break;
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case UARTPeriphID3:
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reg = UARTPeriphID3_VAL;
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break;
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case UARTPCellID0:
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reg = UARTPCellID0_VAL;
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break;
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case UARTPCellID1:
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reg = UARTPCellID1_VAL;
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break;
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case UARTPCellID2:
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reg = UARTPCellID2_VAL;
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break;
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case UARTPCellID3:
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reg = UARTPCellID3_VAL;
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break;
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default:
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/* Return 0 in reads from unasigned registers */
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reg = 0;
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break;
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}
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uart_toggle_intr(sc);
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pthread_mutex_unlock(&sc->mtx);
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return (reg);
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}
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struct uart_pl011_softc *
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uart_pl011_init(uart_intr_func_t intr_assert, uart_intr_func_t intr_deassert,
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void *arg)
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{
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struct uart_pl011_softc *sc;
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sc = calloc(1, sizeof(struct uart_pl011_softc));
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sc->arg = arg;
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sc->intr_assert = intr_assert;
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sc->intr_deassert = intr_deassert;
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sc->backend = uart_init();
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pthread_mutex_init(&sc->mtx, NULL);
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uart_reset(sc);
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return (sc);
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}
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int
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uart_pl011_tty_open(struct uart_pl011_softc *sc, const char *device)
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{
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return (uart_tty_open(sc->backend, device, uart_drain, sc));
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}
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