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UART: Remove ingenic xburst (mips) code from ns8250 driver
Since ingenic JZ4780 SOC support has been removed there is no need
to support ingenic quirks in the UART driver.
Invert of commit b192bae67e
Reviewed by: imp, manu
Approved by: imp, manu (mentor)
Differential Revision: https://reviews.freebsd.org/D42497
This commit is contained in:
parent
d6e457328d
commit
f25b0d6dd7
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@ -162,9 +162,6 @@
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#define FIFO_XMT_RST FCR_XMT_RST
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#define FCR_DMA 0x08
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#define FIFO_DMA_MODE FCR_DMA
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#ifdef CPU_XBURST
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#define FCR_UART_ON 0x10
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#endif
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#define FCR_RX_LOW 0x00
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#define FIFO_RX_LOW FCR_RX_LOW
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#define FCR_RX_MEDL 0x40
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@ -233,9 +233,6 @@ ns8250_flush(struct uart_bas *bas, int what)
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int drain = 0;
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fcr = FCR_ENABLE;
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#ifdef CPU_XBURST
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fcr |= FCR_UART_ON;
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#endif
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if (what & UART_FLUSH_TRANSMITTER)
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fcr |= FCR_XMT_RST;
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if (what & UART_FLUSH_RECEIVER)
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@ -327,10 +324,6 @@ ns8250_probe(struct uart_bas *bas)
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{
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u_char val;
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#ifdef CPU_XBURST
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uart_setreg(bas, REG_FCR, FCR_UART_ON);
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#endif
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/* Check known 0 bits that don't depend on DLAB. */
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val = uart_getreg(bas, REG_IIR);
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if (val & 0x30)
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@ -352,7 +345,7 @@ static void
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ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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u_char ier, val;
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u_char ier;
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if (bas->rclk == 0)
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bas->rclk = DEFAULT_RCLK;
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@ -369,11 +362,7 @@ ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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uart_barrier(bas);
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/* Disable the FIFO (if present). */
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val = 0;
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#ifdef CPU_XBURST
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val |= FCR_UART_ON;
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#endif
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uart_setreg(bas, REG_FCR, val);
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uart_setreg(bas, REG_FCR, 0);
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uart_barrier(bas);
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/* Set RTS & DTR. */
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@ -552,9 +541,6 @@ ns8250_bus_attach(struct uart_softc *sc)
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ns8250->busy_detect = bas->busy_detect;
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ns8250->mcr = uart_getreg(bas, REG_MCR);
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ns8250->fcr = FCR_ENABLE;
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#ifdef CPU_XBURST
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ns8250->fcr |= FCR_UART_ON;
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#endif
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if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
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&ivar)) {
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if (UART_FLAGS_FCR_RX_LOW(ivar))
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@ -847,7 +833,6 @@ ns8250_bus_probe(struct uart_softc *sc)
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struct uart_bas *bas;
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int count, delay, error, limit;
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uint8_t lsr, mcr, ier;
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uint8_t val;
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bas = &sc->sc_bas;
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@ -880,11 +865,7 @@ ns8250_bus_probe(struct uart_softc *sc)
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* done. Since this is the first time we enable the FIFOs, we reset
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* them.
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*/
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val = FCR_ENABLE;
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#ifdef CPU_XBURST
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val |= FCR_UART_ON;
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#endif
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uart_setreg(bas, REG_FCR, val);
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uart_setreg(bas, REG_FCR, FCR_ENABLE);
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uart_barrier(bas);
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if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
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/*
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@ -898,11 +879,7 @@ ns8250_bus_probe(struct uart_softc *sc)
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return (0);
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}
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val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST;
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#ifdef CPU_XBURST
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val |= FCR_UART_ON;
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#endif
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uart_setreg(bas, REG_FCR, val);
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uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
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uart_barrier(bas);
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count = 0;
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@ -912,11 +889,7 @@ ns8250_bus_probe(struct uart_softc *sc)
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error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
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if (error) {
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uart_setreg(bas, REG_MCR, mcr);
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val = 0;
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#ifdef CPU_XBURST
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val |= FCR_UART_ON;
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#endif
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uart_setreg(bas, REG_FCR, val);
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uart_setreg(bas, REG_FCR, 0);
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uart_barrier(bas);
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goto describe;
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}
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@ -947,11 +920,7 @@ ns8250_bus_probe(struct uart_softc *sc)
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ier = uart_getreg(bas, REG_IER) & 0xe0;
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uart_setreg(bas, REG_IER, ier);
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uart_setreg(bas, REG_MCR, mcr);
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val = 0;
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#ifdef CPU_XBURST
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val |= FCR_UART_ON;
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#endif
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uart_setreg(bas, REG_FCR, val);
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uart_setreg(bas, REG_FCR, 0);
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uart_barrier(bas);
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count = 0;
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goto describe;
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