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Define more registers in the PHY unit and use them to report back
the result of the media auto negotiation. Reviewed by: David Greenman <dg@freebsd.org>
This commit is contained in:
Julian Elischer
parent
48ee93d6f3
commit
f1bf08c22e
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=43912
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@ -27,7 +27,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_fxp.c,v 1.61 1999/01/28 00:57:53 dillon Exp $
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* $Id: if_fxp.c,v 1.62 1999/01/28 17:32:05 dillon Exp $
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*/
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/*
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@ -1494,9 +1494,26 @@ fxp_mediastatus(ifp, ifmr)
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case FXP_PHY_82555B:
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flags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_BMCR);
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ifmr->ifm_active = IFM_ETHER;
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if (flags & FXP_PHY_BMCR_AUTOEN)
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ifmr->ifm_active |= IFM_AUTO;
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else {
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if (flags & FXP_PHY_BMCR_AUTOEN) {
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ifmr->ifm_active |= IFM_AUTO; /* XXX presently 0 */
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/*
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* XXX Find the correct subset of chips that have
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* the USC register..
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*/
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if ((sc->phy_primary_device == FXP_PHY_82555)
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|| (sc->phy_primary_device == FXP_PHY_82555B)) {
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flags = fxp_mdi_read(sc,
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sc->phy_primary_addr, FXP_PHY_USC);
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if (flags & FXP_PHY_USC_SPEED)
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ifmr->ifm_active |= IFM_100_TX;
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else
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ifmr->ifm_active |= IFM_10_T;
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if (flags & FXP_PHY_USC_DUPLEX)
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ifmr->ifm_active |= IFM_FDX;
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}
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} else {
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if (flags & FXP_PHY_BMCR_SPEED_100M)
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ifmr->ifm_active |= IFM_100_TX;
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else
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@ -24,7 +24,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_fxpreg.h,v 1.12 1998/03/03 14:19:09 dg Exp $
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* $Id: if_fxpreg.h,v 1.13 1998/06/08 09:47:46 bde Exp $
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*/
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#define FXP_VENDORID_INTEL 0x8086
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@ -331,11 +331,67 @@ struct fxp_stats {
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/*
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* PHY BMCR Basic Mode Control Register
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* Should probably be in i82555.h.
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* (Called "Management Data Interface Control Reg" in some Intel data books).
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* (*) indicates bit ignored in auto negotiation mode.
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*/
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#define FXP_PHY_BMCR 0x0
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#define FXP_PHY_BMCR_FULLDUPLEX 0x0100
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#define FXP_PHY_BMCR_AUTOEN 0x1000
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#define FXP_PHY_BMCR_SPEED_100M 0x2000
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#define FXP_PHY_BMCR 0x0
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#define FXP_PHY_BMCR_FULLDUPLEX 0x0100 /* 1 = Fullduplex (*) */
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#define FXP_PHY_BMCR_RESTART_NEG 0x0200 /* ==> 1 to restart autoneg */
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#define FXP_PHY_BMCR_POWERDOWN 0x0800 /* 1 = low power mode */
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#define FXP_PHY_BMCR_AUTOEN 0x1000 /* 1 = for auto mode */
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#define FXP_PHY_BMCR_SPEED_100M 0x2000 /* 1 = for 100Mb/sec (*) */
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#define FXP_PHY_BMCR_LOOPBACK 0x4000 /* 1 = loopback at the PHY */
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#define FXP_PHY_BMCR_RESET 0x8000 /* ==> 1 sets to defaults */
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/*
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* Management Data Interface Status reg.
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*/
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#define FXP_PHY_STS 0x1
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#define FXP_PHY_STS_EXND 0x0001 /* Extended regs enabled */
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#define FXP_PHY_STS_JABR 0x0002 /* Jabber detected */
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#define FXP_PHY_STS_LINK_STS 0x0004 /* Link valid */
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#define FXP_PHY_STS_CAN_AUTO 0x0008 /* Auto detection available */
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#define FXP_PHY_STS_REMT_FAULT 0x0010 /* remote fault detected */
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#define FXP_PHY_STS_AUTO_DONE 0x0020 /* auto negotiation completed */
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#define FXP_PHY_STS_MGMT_PREAMBLE 0x0040 /* real complicated */
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#define FXP_PHY_STS_10HDX_OK 0x1000 /* can do 10Mb HDX */
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#define FXP_PHY_STS_10FDX_OK 0x2000 /* can do 10Mb FDX */
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#define FXP_PHY_STS_100HDX_OK 0x4000 /* can do 100Mb HDX */
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#define FXP_PHY_STS_100FDX_OK 0x8000 /* can do 100Mb FDX */
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/*
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* More Phy regs
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*/
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#define FXP_PHY_ID1 0x2
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#define FXP_PHY_ID2 0x3
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/*
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* MDI Auto negotiation advertisement register.
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* What we advertise we can do..
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* The same bits are used to indicate the response too.
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*/
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#define FXP_PHY_ADVRT 0x4
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#define FXP_PHY_RMT_ADVRT 0x5 /* what the other end said */
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#define FXP_PHY_ADVRT_SELECT 0x001F /* real complicated */
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#define FXP_PHY_ADVRT_TECH_AVAIL 0x1FE0 /* can do 10Mb HDX */
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#define FXP_PHY_ADVRT_RMT_FAULT 0x2000 /* can do 10Mb FDX */
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#define FXP_PHY_ADVRT_ACK 0x4000 /* Acked */
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#define FXP_PHY_ADVRT_NXT_PAGE 0x8000 /* can do 100Mb FDX */
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/*
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* Phy Unit Status and Control Register (another one)
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*/
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#define FXP_PHY_USC 0x10
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#define FXP_PHY_USC_DUPLEX 0x0001 /* in FDX mode */
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#define FXP_PHY_USC_SPEED 0x0002 /* 1 = in 100Mb mode */
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#define FXP_PHY_USC_POLARITY 0x0100 /* 1 = reverse polarity */
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#define FXP_PHY_USC_10_PWRDOWN 0x0200 /* 10Mb PHY powered down */
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#define FXP_PHY_USC_100_PWRDOWN 0x0400 /* 100Mb PHY powered down */
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#define FXP_PHY_USC_INSYNC 0x0800 /* 100Mb PHY is in sync */
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#define FXP_PHY_USC_TX_FLOWCNTRL 0x1000 /* TX FC mode in use */
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#define FXP_PHY_USC_PHY_FLOWCNTRL 0x8000 /* PHY FC mode in use */
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/*
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* DP84830 PHY, PCS Configuration Register
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@ -27,7 +27,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_fxp.c,v 1.61 1999/01/28 00:57:53 dillon Exp $
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* $Id: if_fxp.c,v 1.62 1999/01/28 17:32:05 dillon Exp $
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*/
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/*
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@ -1494,9 +1494,26 @@ fxp_mediastatus(ifp, ifmr)
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case FXP_PHY_82555B:
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flags = fxp_mdi_read(sc, sc->phy_primary_addr, FXP_PHY_BMCR);
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ifmr->ifm_active = IFM_ETHER;
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if (flags & FXP_PHY_BMCR_AUTOEN)
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ifmr->ifm_active |= IFM_AUTO;
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else {
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if (flags & FXP_PHY_BMCR_AUTOEN) {
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ifmr->ifm_active |= IFM_AUTO; /* XXX presently 0 */
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/*
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* XXX Find the correct subset of chips that have
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* the USC register..
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*/
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if ((sc->phy_primary_device == FXP_PHY_82555)
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|| (sc->phy_primary_device == FXP_PHY_82555B)) {
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flags = fxp_mdi_read(sc,
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sc->phy_primary_addr, FXP_PHY_USC);
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if (flags & FXP_PHY_USC_SPEED)
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ifmr->ifm_active |= IFM_100_TX;
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else
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ifmr->ifm_active |= IFM_10_T;
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if (flags & FXP_PHY_USC_DUPLEX)
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ifmr->ifm_active |= IFM_FDX;
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}
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} else {
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if (flags & FXP_PHY_BMCR_SPEED_100M)
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ifmr->ifm_active |= IFM_100_TX;
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else
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@ -24,7 +24,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_fxpreg.h,v 1.12 1998/03/03 14:19:09 dg Exp $
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* $Id: if_fxpreg.h,v 1.13 1998/06/08 09:47:46 bde Exp $
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*/
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#define FXP_VENDORID_INTEL 0x8086
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@ -331,11 +331,67 @@ struct fxp_stats {
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/*
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* PHY BMCR Basic Mode Control Register
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* Should probably be in i82555.h.
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* (Called "Management Data Interface Control Reg" in some Intel data books).
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* (*) indicates bit ignored in auto negotiation mode.
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*/
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#define FXP_PHY_BMCR 0x0
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#define FXP_PHY_BMCR_FULLDUPLEX 0x0100
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#define FXP_PHY_BMCR_AUTOEN 0x1000
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#define FXP_PHY_BMCR_SPEED_100M 0x2000
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#define FXP_PHY_BMCR 0x0
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#define FXP_PHY_BMCR_FULLDUPLEX 0x0100 /* 1 = Fullduplex (*) */
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#define FXP_PHY_BMCR_RESTART_NEG 0x0200 /* ==> 1 to restart autoneg */
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#define FXP_PHY_BMCR_POWERDOWN 0x0800 /* 1 = low power mode */
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#define FXP_PHY_BMCR_AUTOEN 0x1000 /* 1 = for auto mode */
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#define FXP_PHY_BMCR_SPEED_100M 0x2000 /* 1 = for 100Mb/sec (*) */
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#define FXP_PHY_BMCR_LOOPBACK 0x4000 /* 1 = loopback at the PHY */
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#define FXP_PHY_BMCR_RESET 0x8000 /* ==> 1 sets to defaults */
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/*
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* Management Data Interface Status reg.
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*/
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#define FXP_PHY_STS 0x1
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#define FXP_PHY_STS_EXND 0x0001 /* Extended regs enabled */
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#define FXP_PHY_STS_JABR 0x0002 /* Jabber detected */
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#define FXP_PHY_STS_LINK_STS 0x0004 /* Link valid */
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#define FXP_PHY_STS_CAN_AUTO 0x0008 /* Auto detection available */
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#define FXP_PHY_STS_REMT_FAULT 0x0010 /* remote fault detected */
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#define FXP_PHY_STS_AUTO_DONE 0x0020 /* auto negotiation completed */
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#define FXP_PHY_STS_MGMT_PREAMBLE 0x0040 /* real complicated */
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#define FXP_PHY_STS_10HDX_OK 0x1000 /* can do 10Mb HDX */
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#define FXP_PHY_STS_10FDX_OK 0x2000 /* can do 10Mb FDX */
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#define FXP_PHY_STS_100HDX_OK 0x4000 /* can do 100Mb HDX */
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#define FXP_PHY_STS_100FDX_OK 0x8000 /* can do 100Mb FDX */
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/*
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* More Phy regs
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*/
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#define FXP_PHY_ID1 0x2
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#define FXP_PHY_ID2 0x3
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/*
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* MDI Auto negotiation advertisement register.
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* What we advertise we can do..
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* The same bits are used to indicate the response too.
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*/
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#define FXP_PHY_ADVRT 0x4
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#define FXP_PHY_RMT_ADVRT 0x5 /* what the other end said */
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#define FXP_PHY_ADVRT_SELECT 0x001F /* real complicated */
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#define FXP_PHY_ADVRT_TECH_AVAIL 0x1FE0 /* can do 10Mb HDX */
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#define FXP_PHY_ADVRT_RMT_FAULT 0x2000 /* can do 10Mb FDX */
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#define FXP_PHY_ADVRT_ACK 0x4000 /* Acked */
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#define FXP_PHY_ADVRT_NXT_PAGE 0x8000 /* can do 100Mb FDX */
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/*
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* Phy Unit Status and Control Register (another one)
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*/
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#define FXP_PHY_USC 0x10
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#define FXP_PHY_USC_DUPLEX 0x0001 /* in FDX mode */
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#define FXP_PHY_USC_SPEED 0x0002 /* 1 = in 100Mb mode */
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#define FXP_PHY_USC_POLARITY 0x0100 /* 1 = reverse polarity */
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#define FXP_PHY_USC_10_PWRDOWN 0x0200 /* 10Mb PHY powered down */
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#define FXP_PHY_USC_100_PWRDOWN 0x0400 /* 100Mb PHY powered down */
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#define FXP_PHY_USC_INSYNC 0x0800 /* 100Mb PHY is in sync */
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#define FXP_PHY_USC_TX_FLOWCNTRL 0x1000 /* TX FC mode in use */
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#define FXP_PHY_USC_PHY_FLOWCNTRL 0x8000 /* PHY FC mode in use */
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/*
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* DP84830 PHY, PCS Configuration Register
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