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Import device-tree files from Linux 6.5

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Sponsored by:   Beckhoff Automation GmbH & Co. KG
This commit is contained in:
Emmanuel Vadot 2024-03-21 21:10:18 +01:00
parent 139d114acc 309417d444
commit f126890ac5
3676 changed files with 60850 additions and 24253 deletions
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9
sys/contrib/device-tree/Bindings/arm/amlogic.yaml
View file

@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/arm/amlogic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic MesonX
title: Amlogic SoC based Platforms
maintainers:
- Kevin Hilman <khilman@baylibre.com>
@ -205,6 +205,13 @@ properties:
- amlogic,ad401
- const: amlogic,a1
- description: Boards with the Amlogic C3 C302X/C308L SoC
items:
- enum:
- amlogic,aw409
- amlogic,aw419
- const: amlogic,c3
- description: Boards with the Amlogic Meson S4 S805X2 SoC
items:
- enum:

18
sys/contrib/device-tree/Bindings/arm/arm,coresight-cti.yaml
View file

@ -287,7 +287,7 @@ examples:
arm,trig-in-sigs = <0 1>;
arm,trig-in-types = <PE_DBGTRIGGER
PE_PMUIRQ>;
arm,trig-out-sigs=<0 1 2 >;
arm,trig-out-sigs = <0 1 2 >;
arm,trig-out-types = <PE_EDBGREQ
PE_DBGRESTART
PE_CTIIRQ>;
@ -309,24 +309,24 @@ examples:
trig-conns@0 {
reg = <0>;
arm,trig-in-sigs=<0>;
arm,trig-in-types=<GEN_INTREQ>;
arm,trig-out-sigs=<0>;
arm,trig-out-types=<GEN_HALTREQ>;
arm,trig-in-sigs = <0>;
arm,trig-in-types = <GEN_INTREQ>;
arm,trig-out-sigs = <0>;
arm,trig-out-types = <GEN_HALTREQ>;
arm,trig-conn-name = "sys_profiler";
};
trig-conns@1 {
reg = <1>;
arm,trig-out-sigs=<2 3>;
arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
arm,trig-out-sigs = <2 3>;
arm,trig-out-types = <GEN_HALTREQ GEN_RESTARTREQ>;
arm,trig-conn-name = "watchdog";
};
trig-conns@2 {
reg = <2>;
arm,trig-in-sigs=<1 6>;
arm,trig-in-types=<GEN_HALTREQ GEN_RESTARTREQ>;
arm,trig-in-sigs = <1 6>;
arm,trig-in-types = <GEN_HALTREQ GEN_RESTARTREQ>;
arm,trig-conn-name = "g_counter";
};
};

73
sys/contrib/device-tree/Bindings/arm/arm,coresight-dummy-sink.yaml Normal file
View file

@ -0,0 +1,73 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-dummy-sink.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Coresight Dummy sink component
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight dummy sink component is for the specific coresight sink devices
kernel don't have permission to access or configure, e.g., CoreSight EUD on
Qualcomm platforms. It is a mini-USB hub implemented to support the USB-based
debug and trace capabilities. For this device, a dummy driver is needed to
register it as Coresight sink device in kernel side, so that path can be
created in the driver. Then the trace flow would be transferred to EUD via
coresight link of AP processor. It provides Coresight API for operations on
dummy source devices, such as enabling and disabling them. It also provides
the Coresight dummy source paths for debugging.
The primary use case of the coresight dummy sink is to build path in kernel
side for dummy sink component.
maintainers:
- Mike Leach <mike.leach@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
- James Clark <james.clark@arm.com>
- Mao Jinlong <quic_jinlmao@quicinc.com>
- Hao Zhang <quic_hazha@quicinc.com>
properties:
compatible:
enum:
- arm,coresight-dummy-sink
in-ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port:
description: Input connection from the Coresight Trace bus to
dummy sink, such as Embedded USB debugger(EUD).
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- in-ports
additionalProperties: false
examples:
# Minimum dummy sink definition. Dummy sink connect to coresight replicator.
- |
sink {
compatible = "arm,coresight-dummy-sink";
in-ports {
port {
eud_in_replicator_swao: endpoint {
remote-endpoint = <&replicator_swao_out_eud>;
};
};
};
};
...

71
sys/contrib/device-tree/Bindings/arm/arm,coresight-dummy-source.yaml Normal file
View file

@ -0,0 +1,71 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-dummy-source.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Coresight Dummy source component
description: |
CoreSight components are compliant with the ARM CoreSight architecture
specification and can be connected in various topologies to suit a particular
SoCs tracing needs. These trace components can generally be classified as
sinks, links and sources. Trace data produced by one or more sources flows
through the intermediate links connecting the source to the currently selected
sink.
The Coresight dummy source component is for the specific coresight source
devices kernel don't have permission to access or configure. For some SOCs,
there would be Coresight source trace components on sub-processor which
are conneted to AP processor via debug bus. For these devices, a dummy driver
is needed to register them as Coresight source devices, so that paths can be
created in the driver. It provides Coresight API for operations on dummy
source devices, such as enabling and disabling them. It also provides the
Coresight dummy source paths for debugging.
The primary use case of the coresight dummy source is to build path in kernel
side for dummy source component.
maintainers:
- Mike Leach <mike.leach@linaro.org>
- Suzuki K Poulose <suzuki.poulose@arm.com>
- James Clark <james.clark@arm.com>
- Mao Jinlong <quic_jinlmao@quicinc.com>
- Hao Zhang <quic_hazha@quicinc.com>
properties:
compatible:
enum:
- arm,coresight-dummy-source
out-ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port:
description: Output connection from the source to Coresight
Trace bus.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- out-ports
additionalProperties: false
examples:
# Minimum dummy source definition. Dummy source connect to coresight funnel.
- |
source {
compatible = "arm,coresight-dummy-source";
out-ports {
port {
dummy_riscv_out_funnel_swao: endpoint {
remote-endpoint = <&funnel_swao_in_dummy_riscv>;
};
};
};
};
...

10
sys/contrib/device-tree/Bindings/arm/arm,vexpress-juno.yaml
View file

@ -122,14 +122,14 @@ properties:
arm,vexpress,position:
description: When daughterboards are stacked on one site, their position
in the stack be be described this attribute.
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3
arm,vexpress,dcc:
description: When describing tiles consisting of more than one DCC, its
number can be specified with this attribute.
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3
@ -180,13 +180,13 @@ patternProperties:
- const: simple-bus
arm,v2m-memory-map:
description: This describes the memory map type.
$ref: '/schemas/types.yaml#/definitions/string'
$ref: /schemas/types.yaml#/definitions/string
enum:
- rs1
- rs2
arm,hbi:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description: This indicates the ARM HBI (Hardware Board ID), this is
ARM's unique board model ID, visible on the PCB's silkscreen.
@ -197,7 +197,7 @@ patternProperties:
property, describing the physical location of the children nodes.
0 means motherboard site, while 1 and 2 are daughterboard sites, and
0xf means "sisterboard" which is the site containing the main CPU tile.
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 15

94
sys/contrib/device-tree/Bindings/arm/atmel-sysregs.txt
View file

@ -52,100 +52,6 @@ Example:
reg = <0xe3804000 0x1000>;
};
SHDWC Shutdown Controller
required properties:
- compatible: Should be "atmel,<chip>-shdwc".
<chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
- reg: Should contain registers location and length
- clocks: phandle to input clock.
optional properties:
- atmel,wakeup-mode: String, operation mode of the wakeup mode.
Supported values are: "none", "high", "low", "any".
- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf).
optional at91sam9260 properties:
- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
optional at91sam9rl properties:
- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
optional at91sam9x5 properties:
- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up.
Example:
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
clocks = <&clk32k>;
};
SHDWC SAMA5D2-Compatible Shutdown Controller
1) shdwc node
required properties:
- compatible: should be "atmel,sama5d2-shdwc", "microchip,sam9x60-shdwc" or
"microchip,sama7g5-shdwc"
- reg: should contain registers location and length
- clocks: phandle to input clock.
- #address-cells: should be one. The cell is the wake-up input index.
- #size-cells: should be zero.
optional properties:
- debounce-delay-us: minimum wake-up inputs debouncer period in
microseconds. It's usually a board-related property.
- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up.
optional microchip,sam9x60-shdwc or microchip,sama7g5-shdwc properties:
- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up.
The node contains child nodes for each wake-up input that the platform uses.
2) input nodes
Wake-up input nodes are usually described in the "board" part of the Device
Tree. Note also that input 0 is linked to the wake-up pin and is frequently
used.
Required properties:
- reg: should contain the wake-up input index [0 - 15].
Optional properties:
- atmel,wakeup-active-high: boolean, the corresponding wake-up input described
by the child, forces the wake-up of the core power supply on a high level.
The default is to be active low.
Example:
On the SoC side:
shdwc@f8048010 {
compatible = "atmel,sama5d2-shdwc";
reg = <0xf8048010 0x10>;
clocks = <&clk32k>;
#address-cells = <1>;
#size-cells = <0>;
atmel,wakeup-rtc-timer;
};
On the board side:
shdwc@f8048010 {
debounce-delay-us = <976>;
input@0 {
reg = <0>;
};
input@1 {
reg = <1>;
atmel,wakeup-active-high;
};
};
Special Function Registers (SFR)
Special Function Registers (SFR) manage specific aspects of the integrated

14
sys/contrib/device-tree/Bindings/arm/bcm/brcm,bcm4708.yaml
View file

@ -25,13 +25,15 @@ properties:
- enum:
- asus,rt-ac56u
- asus,rt-ac68u
- buffalo,wzr-1166dhp
- buffalo,wzr-1166dhp2
- buffalo,wzr-1750dhp
- linksys,ea6300-v1
- linksys,ea6500-v2
- luxul,xap-1510v1
- luxul,xap-1510-v1
- luxul,xwc-1000
- netgear,r6250v1
- netgear,r6300v2
- netgear,r6250-v1
- netgear,r6300-v2
- smartrg,sr400ac
- brcm,bcm94708
- const: brcm,bcm4708
@ -42,8 +44,8 @@ properties:
- asus,rt-n18u
- buffalo,wzr-600dhp2
- buffalo,wzr-900dhp
- luxul,xap-1410v1
- luxul,xwr-1200v1
- luxul,xap-1410-v1
- luxul,xwr-1200-v1
- tplink,archer-c5-v2
- const: brcm,bcm47081
- const: brcm,bcm4708
@ -72,7 +74,7 @@ properties:
- luxul,xap-1610-v1
- luxul,xbr-4500-v1
- luxul,xwc-2000-v1
- luxul,xwr-3100v1
- luxul,xwr-3100-v1
- luxul,xwr-3150-v1
- netgear,r8500
- phicomm,k3

19
sys/contrib/device-tree/Bindings/arm/cpus.yaml
View file

@ -153,6 +153,7 @@ properties:
- arm,cortex-r4
- arm,cortex-r5
- arm,cortex-r7
- arm,cortex-r52
- arm,cortex-x1
- arm,cortex-x1c
- arm,cortex-x2
@ -196,7 +197,7 @@ properties:
- qcom,scorpion
enable-method:
$ref: '/schemas/types.yaml#/definitions/string'
$ref: /schemas/types.yaml#/definitions/string
oneOf:
# On ARM v8 64-bit this property is required
- enum:
@ -245,8 +246,8 @@ properties:
cpu-release-addr:
oneOf:
- $ref: '/schemas/types.yaml#/definitions/uint32'
- $ref: '/schemas/types.yaml#/definitions/uint64'
- $ref: /schemas/types.yaml#/definitions/uint32
- $ref: /schemas/types.yaml#/definitions/uint64
description:
The DT specification defines this as 64-bit always, but some 32-bit Arm
systems have used a 32-bit value which must be supported.
@ -254,7 +255,7 @@ properties:
property value of "spin-table".
cpu-idle-states:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description: |
@ -270,7 +271,7 @@ properties:
cci-control-port: true
dynamic-power-coefficient:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description:
A u32 value that represents the running time dynamic
power coefficient in units of uW/MHz/V^2. The
@ -307,7 +308,7 @@ properties:
PM domain provider, must be "psci".
qcom,saw:
$ref: '/schemas/types.yaml#/definitions/phandle'
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Specifies the SAW* node associated with this CPU.
@ -317,7 +318,7 @@ properties:
* arm/msm/qcom,saw2.txt
qcom,acc:
$ref: '/schemas/types.yaml#/definitions/phandle'
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Specifies the ACC* node associated with this CPU.
@ -328,7 +329,7 @@ properties:
* arm/msm/qcom,kpss-acc.txt
rockchip,pmu:
$ref: '/schemas/types.yaml#/definitions/phandle'
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Specifies the syscon node controlling the cpu core power domains.
@ -338,7 +339,7 @@ properties:
the cpu-core power-domains.
secondary-boot-reg:
$ref: '/schemas/types.yaml#/definitions/uint32'
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Required for systems that have an "enable-method" property value of
"brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".

14
sys/contrib/device-tree/Bindings/arm/fsl.yaml
View file

@ -726,6 +726,12 @@ properties:
- const: dh,imx6ull-dhcor-som
- const: fsl,imx6ull
- description: i.MX6ULL DHCOR SoM based Boards
items:
- const: marantec,imx6ull-dhcor-maveo-box
- const: dh,imx6ull-dhcor-som
- const: fsl,imx6ull
- description: i.MX6ULL PHYTEC phyBOARD-Segin
items:
- enum:
@ -901,6 +907,7 @@ properties:
- emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
- fsl,imx8mm-evk # i.MX8MM EVK Board
- fsl,imx8mm-evkb # i.MX8MM EVKB Board
- gateworks,imx8mm-gw7904
- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
@ -918,6 +925,12 @@ properties:
- prt,prt8mm # i.MX8MM Protonic PRT8MM Board
- const: fsl,imx8mm
- description: Emtop i.MX8MM based Boards
items:
- const: ees,imx8mm-emtop-baseboard # i.MX8MM Emtop SoM on i.MX8M Mini Baseboard V1
- const: ees,imx8mm-emtop-som # i.MX8MM Emtop SOM-IMX8MMLPD4 module
- const: fsl,imx8mm
- description: Engicam i.Core MX8M Mini SoM based boards
items:
- enum:
@ -1019,6 +1032,7 @@ properties:
- dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
- fsl,imx8mp-evk # i.MX8MP EVK Board
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw7905-2x # i.MX8MP Gateworks Board
- polyhex,imx8mp-debix # Polyhex Debix boards
- polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
- toradex,verdin-imx8mp # Verdin iMX8M Plus Modules

8
sys/contrib/device-tree/Bindings/arm/keystone/ti,sci.yaml
View file

@ -96,8 +96,8 @@ examples:
compatible = "ti,k2g-sci";
ti,system-reboot-controller;
mbox-names = "rx", "tx";
mboxes= <&msgmgr 5 2>,
<&msgmgr 0 0>;
mboxes = <&msgmgr 5 2>,
<&msgmgr 0 0>;
reg-names = "debug_messages";
reg = <0x02921800 0x800>;
};
@ -107,8 +107,8 @@ examples:
compatible = "ti,k2g-sci";
ti,host-id = <12>;
mbox-names = "rx", "tx";
mboxes= <&secure_proxy_main 11>,
<&secure_proxy_main 13>;
mboxes = <&secure_proxy_main 11>,
<&secure_proxy_main 13>;
reg-names = "debug_messages";
reg = <0x44083000 0x1000>;

30
sys/contrib/device-tree/Bindings/arm/nuvoton/nuvoton,ma35d1.yaml Normal file
View file

@ -0,0 +1,30 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/nuvoton/nuvoton,ma35d1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Nuvoton MA35 series SoC based platforms
maintainers:
- Jacky Huang <ychuang3@nuvoton.com>
description: |
Boards with an ARMv8 based Nuvoton MA35 series SoC shall have
the following properties.
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: MA35D1 based boards
items:
- enum:
- nuvoton,ma35d1-iot
- nuvoton,ma35d1-som
- const: nuvoton,ma35d1
additionalProperties: true
...

36
sys/contrib/device-tree/Bindings/arm/nuvoton/nuvoton,npcm.yaml Normal file
View file

@ -0,0 +1,36 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/nuvoton/nuvoton,npcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NPCM Platforms
maintainers:
- Jonathan Neuschäfer <j.neuschaefer@gmx.net>
- Tomer Maimon <tmaimon77@gmail.com>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: WPCM450 based boards
items:
- enum:
- supermicro,x9sci-ln4f-bmc # Supermicro X9SCI-LN4F server's BMC
- const: nuvoton,wpcm450
- description: NPCM750 based boards
items:
- enum:
- nuvoton,npcm750-evb # NPCM750 evaluation board
- const: nuvoton,npcm750
- description: NPCM845 based boards
items:
- enum:
- nuvoton,npcm845-evb # NPCM845 evaluation board
- const: nuvoton,npcm845
additionalProperties: true

2
sys/contrib/device-tree/Bindings/arm/psci.yaml
View file

@ -100,7 +100,7 @@ properties:
patternProperties:
"^power-domain-":
$ref: "../power/power-domain.yaml#"
$ref: /schemas/power/power-domain.yaml#
type: object
description: |

30
sys/contrib/device-tree/Bindings/arm/qcom.yaml
View file

@ -40,6 +40,7 @@ description: |
msm8939
msm8953
msm8956
msm8960
msm8974
msm8976
msm8992
@ -69,6 +70,7 @@ description: |
sdm845
sdx55
sdx65
sdx75
sm4250
sm6115
sm6115p
@ -85,9 +87,15 @@ description: |
The 'board' element must be one of the following strings:
adp
ap-al02-c2
ap-al02-c6
ap-al02-c7
ap-al02-c8
ap-al02-c9
ap-mi01.2
ap-mi01.3
ap-mi01.6
ap-mi01.9
cdp
cp01-c1
dragonboard
@ -191,6 +199,7 @@ properties:
- items:
- enum:
- qcom,msm8960-cdp
- samsung,expressatt
- const: qcom,msm8960
- items:
@ -333,7 +342,9 @@ properties:
- items:
- enum:
- qcom,ipq5332-ap-mi01.2
- qcom,ipq5332-ap-mi01.3
- qcom,ipq5332-ap-mi01.6
- qcom,ipq5332-ap-mi01.9
- const: qcom,ipq5332
- items:
@ -351,7 +362,11 @@ properties:
- items:
- enum:
- qcom,ipq9574-ap-al02-c2
- qcom,ipq9574-ap-al02-c6
- qcom,ipq9574-ap-al02-c7
- qcom,ipq9574-ap-al02-c8
- qcom,ipq9574-ap-al02-c9
- const: qcom,ipq9574
- description: Sierra Wireless MangOH Green with WP8548 Module
@ -380,9 +395,9 @@ properties:
- qcom,qru1000-idp
- const: qcom,qru1000
- description: Qualcomm Technologies, Inc. SC7180 IDP
items:
- items:
- enum:
- acer,aspire1
- qcom,sc7180-idp
- const: qcom,sc7180
@ -819,6 +834,11 @@ properties:
- qcom,sdx65-mtp
- const: qcom,sdx65
- items:
- enum:
- qcom,sdx75-idp
- const: qcom,sdx75
- items:
- enum:
- qcom,ipq6018-cp01
@ -882,6 +902,11 @@ properties:
- const: qcom,qrb4210
- const: qcom,sm4250
- items:
- enum:
- fxtec,pro1x
- const: qcom,sm6115
- items:
- enum:
- lenovo,j606f
@ -1042,6 +1067,7 @@ allOf:
- qcom,sdm845
- qcom,sdx55
- qcom,sdx65
- qcom,sdx75
- qcom,sm4250
- qcom,sm6115
- qcom,sm6125

24
sys/contrib/device-tree/Bindings/arm/rockchip.yaml
View file

@ -40,6 +40,11 @@ properties:
- const: anbernic,rg353p
- const: rockchip,rk3566
- description: Anbernic RG353PS
items:
- const: anbernic,rg353ps
- const: rockchip,rk3566
- description: Anbernic RG353V
items:
- const: anbernic,rg353v
@ -102,6 +107,12 @@ properties:
- const: edgeble,neural-compute-module-6a # Edgeble Neural Compute Module 6A SoM
- const: rockchip,rk3588
- description: Edgeble Neural Compute Module 6(Neu6) Model B SoM based boards
items:
- const: edgeble,neural-compute-module-6b-io # Edgeble Neural Compute Module 6B IO Board
- const: edgeble,neural-compute-module-6b # Edgeble Neural Compute Module 6B SoM
- const: rockchip,rk3588
- description: Elgin RV1108 R1
items:
- const: elgin,rv1108-r1
@ -189,6 +200,7 @@ properties:
items:
- enum:
- friendlyarm,nanopi-r2c
- friendlyarm,nanopi-r2c-plus
- friendlyarm,nanopi-r2s
- const: rockchip,rk3328
@ -534,6 +546,11 @@ properties:
- const: hugsun,x99
- const: rockchip,rk3399
- description: Indiedroid Nova SBC
items:
- const: indiedroid,nova
- const: rockchip,rk3588s
- description: Khadas Edge series boards
items:
- enum:
@ -562,6 +579,13 @@ properties:
- const: leez,p710
- const: rockchip,rk3399
- description: Lunzn FastRhino R66S / R68S
items:
- enum:
- lunzn,fastrhino-r66s
- lunzn,fastrhino-r68s
- const: rockchip,rk3568
- description: mqmaker MiQi
items:
- const: mqmaker,miqi

10
sys/contrib/device-tree/Bindings/arm/samsung/samsung-boards.yaml
View file

@ -72,6 +72,16 @@ properties:
- const: samsung,exynos4210
- const: samsung,exynos4
- description: Samsung Galaxy Tab3 family boards
items:
- enum:
- samsung,t310 # Samsung Galaxy Tab 3 8.0 WiFi (SM-T310)
- samsung,t311 # Samsung Galaxy Tab 3 8.0 3G (SM-T311)
- samsung,t315 # Samsung Galaxy Tab 3 8.0 LTE (SM-T315)
- const: samsung,tab3
- const: samsung,exynos4212
- const: samsung,exynos4
- description: Exynos4412 based boards
items:
- enum:

28
sys/contrib/device-tree/Bindings/arm/socionext/synquacer.yaml Normal file
View file

@ -0,0 +1,28 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/socionext/synquacer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Socionext Synquacer platform
maintainers:
- Masahisa Kojima <masahisa.kojima@linaro.org>
- Jassi Brar <jaswinder.singh@linaro.org>
description:
Socionext SC2A11B (Synquacer) SoC based boards
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- enum:
- socionext,developer-box
- const: socionext,synquacer
additionalProperties: true
...

7
sys/contrib/device-tree/Bindings/arm/stm32/st,stm32-syscon.yaml
View file

@ -15,12 +15,13 @@ properties:
oneOf:
- items:
- enum:
- st,stm32mp157-syscfg
- st,stm32mp151-pwr-mcu
- st,stm32-syscfg
- st,stm32-power-config
- st,stm32-syscfg
- st,stm32-tamp
- st,stm32f4-gcan
- st,stm32mp151-pwr-mcu
- st,stm32mp157-syscfg
- st,stm32mp25-syscfg
- const: syscon
- items:
- const: st,stm32-tamp

12
sys/contrib/device-tree/Bindings/arm/stm32/stm32.yaml
View file

@ -155,6 +155,18 @@ properties:
- const: seeed,stm32mp157c-odyssey-som
- const: st,stm32mp157
- description: Phytec STM32MP1 SoM based Boards
items:
- const: phytec,phycore-stm32mp1-3
- const: phytec,phycore-stm32mp157c-som
- const: st,stm32mp157
- description: ST STM32MP257 based Boards
items:
- enum:
- st,stm32mp257f-ev1
- const: st,stm32mp257
additionalProperties: true
...

6
sys/contrib/device-tree/Bindings/arm/sunxi.yaml
View file

@ -305,6 +305,12 @@ properties:
- const: allwinner,i12-tvbox
- const: allwinner,sun7i-a20
- description: ICnova A20 ADB4006
items:
- const: incircuit,icnova-a20-adb4006
- const: incircuit,icnova-a20
- const: allwinner,sun7i-a20
- description: ICNova A20 SWAC
items:
- const: incircuit,icnova-a20-swac

14
sys/contrib/device-tree/Bindings/arm/tegra.yaml
View file

@ -167,6 +167,11 @@ properties:
- const: nvidia,p3737-0000+p3701-0000
- const: nvidia,p3701-0000
- const: nvidia,tegra234
- description: NVIDIA IGX Orin Development Kit
items:
- const: nvidia,p3740-0002+p3701-0008
- const: nvidia,p3701-0008
- const: nvidia,tegra234
- description: Jetson Orin NX
items:
- const: nvidia,p3767-0000
@ -176,5 +181,14 @@ properties:
- const: nvidia,p3768-0000+p3767-0000
- const: nvidia,p3767-0000
- const: nvidia,tegra234
- description: Jetson Orin Nano
items:
- const: nvidia,p3767-0005
- const: nvidia,tegra234
- description: Jetson Orin Nano Developer Kit
items:
- const: nvidia,p3768-0000+p3767-0005
- const: nvidia,p3767-0005
- const: nvidia,tegra234
additionalProperties: true

26
sys/contrib/device-tree/Bindings/arm/ti/k3.yaml
View file

@ -25,6 +25,12 @@ properties:
- ti,am62a7-sk
- const: ti,am62a7
- description: K3 AM625 SoC PHYTEC phyBOARD-Lyra
items:
- const: phytec,am625-phyboard-lyra-rdk
- const: phytec,am62-phycore-som
- const: ti,am625
- description: K3 AM625 SoC
items:
- enum:
@ -33,6 +39,26 @@ properties:
- ti,am62-lp-sk
- const: ti,am625
- description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards
items:
- enum:
- toradex,verdin-am62-nonwifi-dahlia # Verdin AM62 Module on Dahlia
- toradex,verdin-am62-nonwifi-dev # Verdin AM62 Module on Verdin Development Board
- toradex,verdin-am62-nonwifi-yavia # Verdin AM62 Module on Yavia
- const: toradex,verdin-am62-nonwifi # Verdin AM62 Module without Wi-Fi / BT
- const: toradex,verdin-am62 # Verdin AM62 Module
- const: ti,am625
- description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards with Wi-Fi / BT
items:
- enum:
- toradex,verdin-am62-wifi-dahlia # Verdin AM62 Wi-Fi / BT Module on Dahlia
- toradex,verdin-am62-wifi-dev # Verdin AM62 Wi-Fi / BT M. on Verdin Development B.
- toradex,verdin-am62-wifi-yavia # Verdin AM62 Wi-Fi / BT Module on Yavia
- const: toradex,verdin-am62-wifi # Verdin AM62 Wi-Fi / BT Module
- const: toradex,verdin-am62 # Verdin AM62 Module
- const: ti,am625
- description: K3 AM642 SoC
items:
- enum:

2
sys/contrib/device-tree/Bindings/arm/xen.txt
View file

@ -56,7 +56,7 @@ hypervisor {
};
The format and meaning of the "xen,uefi-*" parameters are similar to those in
Documentation/arm/uefi.rst, which are provided by the regular UEFI stub. However
Documentation/arch/arm/uefi.rst, which are provided by the regular UEFI stub. However
they differ because they are provided by the Xen hypervisor, together with a set
of UEFI runtime services implemented via hypercalls, see
http://xenbits.xen.org/docs/unstable/hypercall/x86_64/include,public,platform.h.html.

8
sys/contrib/device-tree/Bindings/arm/xilinx.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Platforms
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
description: |
Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
@ -61,10 +61,10 @@ properties:
- const: xlnx,zynqmp-zc1254
- const: xlnx,zynqmp
- description: Xilinx internal board zc1275
- description: Xilinx evaluation board zcu1275
items:
- const: xlnx,zynqmp-zc1275-revA
- const: xlnx,zynqmp-zc1275
- const: xlnx,zynqmp-zcu1275-revA
- const: xlnx,zynqmp-zcu1275
- const: xlnx,zynqmp
- description: Xilinx 96boards compatible board zcu100

2
sys/contrib/device-tree/Bindings/ata/ceva,ahci-1v84.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ceva AHCI SATA Controller
maintainers:
- Piyush Mehta <piyush.mehta@xilinx.com>
- Piyush Mehta <piyush.mehta@amd.com>
description: |
The Ceva SATA controller mostly conforms to the AHCI interface with some

124
sys/contrib/device-tree/Bindings/ata/rockchip,dwc-ahci.yaml Normal file
View file

@ -0,0 +1,124 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synopsys DWC AHCI SATA controller for Rockchip devices
maintainers:
- Serge Semin <fancer.lancer@gmail.com>
description:
This document defines device tree bindings for the Synopsys DWC
implementation of the AHCI SATA controller found in Rockchip
devices.
select:
properties:
compatible:
contains:
enum:
- rockchip,rk3568-dwc-ahci
- rockchip,rk3588-dwc-ahci
required:
- compatible
properties:
compatible:
items:
- enum:
- rockchip,rk3568-dwc-ahci
- rockchip,rk3588-dwc-ahci
- const: snps,dwc-ahci
ports-implemented:
const: 1
sata-port@0:
$ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
properties:
reg:
const: 0
unevaluatedProperties: false
patternProperties:
"^sata-port@[1-9a-e]$": false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- ports-implemented
allOf:
- $ref: snps,dwc-ahci-common.yaml#
- if:
properties:
compatible:
contains:
enum:
- rockchip,rk3588-dwc-ahci
then:
properties:
clocks:
maxItems: 5
clock-names:
items:
- const: sata
- const: pmalive
- const: rxoob
- const: ref
- const: asic
- if:
properties:
compatible:
contains:
enum:
- rockchip,rk3568-dwc-ahci
then:
properties:
clocks:
maxItems: 3
clock-names:
items:
- const: sata
- const: pmalive
- const: rxoob
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/rockchip,rk3588-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/ata/ahci.h>
#include <dt-bindings/phy/phy.h>
sata@fe210000 {
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
reg = <0xfe210000 0x1000>;
clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
<&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
<&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
ports-implemented = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
sata-port@0 {
reg = <0>;
hba-port-cap = <HBA_PORT_FBSCP>;
phys = <&combphy0_ps PHY_TYPE_SATA>;
phy-names = "sata-phy";
snps,rx-ts-max = <32>;
snps,tx-ts-max = <32>;
};
};
...

8
sys/contrib/device-tree/Bindings/ata/snps,dwc-ahci-common.yaml
View file

@ -31,11 +31,11 @@ properties:
PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
clock, etc.
minItems: 1
maxItems: 4
maxItems: 6
clock-names:
minItems: 1
maxItems: 4
maxItems: 6
items:
oneOf:
- description: Application APB/AHB/AXI BIU clock
@ -48,6 +48,10 @@ properties:
const: pmalive
- description: RxOOB detection clock
const: rxoob
- description: PHY Transmit Clock
const: asic
- description: PHY Receive Clock
const: rbc
- description: SATA Ports reference clock
const: ref

13
sys/contrib/device-tree/Bindings/ata/snps,dwc-ahci.yaml
View file

@ -13,6 +13,15 @@ description:
This document defines device tree bindings for the generic Synopsys DWC
implementation of the AHCI SATA controller.
select:
properties:
compatible:
enum:
- snps,dwc-ahci
- snps,spear-ahci
required:
- compatible
allOf:
- $ref: snps,dwc-ahci-common.yaml#
@ -23,10 +32,6 @@ properties:
const: snps,dwc-ahci
- description: SPEAr1340 AHCI SATA device
const: snps,spear-ahci
- description: Rockhip RK3568 AHCI controller
items:
- const: rockchip,rk3568-dwc-ahci
- const: snps,dwc-ahci
patternProperties:
"^sata-port@[0-9a-e]$":

1
sys/contrib/device-tree/Bindings/auxdisplay/holtek,ht16k33.yaml
View file

@ -40,6 +40,7 @@ properties:
linux,keymap: true
linux,no-autorepeat:
type: boolean
description: Disable keyrepeat
default-brightness-level:

2
sys/contrib/device-tree/Bindings/bus/ti-sysc.yaml
View file

@ -97,7 +97,7 @@ properties:
- enum: [ ick, fck, sys_clk ]
- items:
- const: fck
- enum: [ ick. dbclk, osc, sys_clk, dss_clk, ahclkx ]
- enum: [ ick, dbclk, osc, sys_clk, dss_clk, ahclkx ]
- items:
- const: fck
- const: phy-clk

73
sys/contrib/device-tree/Bindings/clock/amlogic,a1-peripherals-clkc.yaml Normal file
View file

@ -0,0 +1,73 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,a1-peripherals-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic A1 Peripherals Clock Control Unit
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Jerome Brunet <jbrunet@baylibre.com>
- Jian Hu <jian.hu@jian.hu.com>
- Dmitry Rokosov <ddrokosov@sberdevices.ru>
properties:
compatible:
const: amlogic,a1-peripherals-clkc
'#clock-cells':
const: 1
reg:
maxItems: 1
clocks:
items:
- description: input fixed pll div2
- description: input fixed pll div3
- description: input fixed pll div5
- description: input fixed pll div7
- description: input hifi pll
- description: input oscillator (usually at 24MHz)
clock-names:
items:
- const: fclk_div2
- const: fclk_div3
- const: fclk_div5
- const: fclk_div7
- const: hifi_pll
- const: xtal
required:
- compatible
- '#clock-cells'
- reg
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
apb {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@800 {
compatible = "amlogic,a1-peripherals-clkc";
reg = <0 0x800 0 0x104>;
#clock-cells = <1>;
clocks = <&clkc_pll CLKID_FCLK_DIV2>,
<&clkc_pll CLKID_FCLK_DIV3>,
<&clkc_pll CLKID_FCLK_DIV5>,
<&clkc_pll CLKID_FCLK_DIV7>,
<&clkc_pll CLKID_HIFI_PLL>,
<&xtal>;
clock-names = "fclk_div2", "fclk_div3",
"fclk_div5", "fclk_div7",
"hifi_pll", "xtal";
};
};

59
sys/contrib/device-tree/Bindings/clock/amlogic,a1-pll-clkc.yaml Normal file
View file

@ -0,0 +1,59 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,a1-pll-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic A1 PLL Clock Control Unit
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Jerome Brunet <jbrunet@baylibre.com>
- Jian Hu <jian.hu@jian.hu.com>
- Dmitry Rokosov <ddrokosov@sberdevices.ru>
properties:
compatible:
const: amlogic,a1-pll-clkc
'#clock-cells':
const: 1
reg:
maxItems: 1
clocks:
items:
- description: input fixpll_in
- description: input hifipll_in
clock-names:
items:
- const: fixpll_in
- const: hifipll_in
required:
- compatible
- '#clock-cells'
- reg
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
apb {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@7c80 {
compatible = "amlogic,a1-pll-clkc";
reg = <0 0x7c80 0 0x18c>;
#clock-cells = <1>;
clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
<&clkc_periphs CLKID_HIFIPLL_IN>;
clock-names = "fixpll_in", "hifipll_in";
};
};

154
sys/contrib/device-tree/Bindings/clock/atmel,at91rm9200-pmc.yaml Normal file
View file

@ -0,0 +1,154 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/atmel,at91rm9200-pmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel Power Management Controller (PMC)
maintainers:
- Claudiu Beznea <claudiu.beznea@microchip.com>
description:
The power management controller optimizes power consumption by controlling all
system and user peripheral clocks. The PMC enables/disables the clock inputs
to many of the peripherals and to the processor.
properties:
compatible:
oneOf:
- items:
- const: atmel,at91sam9g20-pmc
- const: atmel,at91sam9260-pmc
- const: syscon
- items:
- enum:
- atmel,at91sam9g15-pmc
- atmel,at91sam9g25-pmc
- atmel,at91sam9g35-pmc
- atmel,at91sam9x25-pmc
- atmel,at91sam9x35-pmc
- const: atmel,at91sam9x5-pmc
- const: syscon
- items:
- enum:
- atmel,at91rm9200-pmc
- atmel,at91sam9260-pmc
- atmel,at91sam9g45-pmc
- atmel,at91sam9n12-pmc
- atmel,at91sam9rl-pmc
- atmel,at91sam9x5-pmc
- atmel,sama5d2-pmc
- atmel,sama5d3-pmc
- atmel,sama5d4-pmc
- microchip,sam9x60-pmc
- microchip,sama7g5-pmc
- const: syscon
reg:
maxItems: 1
interrupts:
maxItems: 1
"#clock-cells":
description: |
- 1st cell is the clock type, one of PMC_TYPE_CORE, PMC_TYPE_SYSTEM,
PMC_TYPE_PERIPHERAL, PMC_TYPE_GCK, PMC_TYPE_PROGRAMMABLE (as defined
in <dt-bindings/clock/at91.h>)
- 2nd cell is the clock identifier as defined in <dt-bindings/clock/at91.h
(for core clocks) or as defined in datasheet (for system, peripheral,
gck and programmable clocks).
const: 2
clocks:
minItems: 2
maxItems: 3
clock-names:
minItems: 2
maxItems: 3
atmel,osc-bypass:
description: set when a clock signal is directly provided on XIN
type: boolean
required:
- compatible
- reg
- interrupts
- "#clock-cells"
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
enum:
- microchip,sam9x60-pmc
- microchip,sama7g5-pmc
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: td_slck
- const: md_slck
- const: main_xtal
- if:
properties:
compatible:
contains:
enum:
- atmel,at91rm9200-pmc
- atmel,at91sam9260-pmc
- atmel,at91sam9g20-pmc
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: slow_xtal
- const: main_xtal
- if:
properties:
compatible:
contains:
enum:
- atmel,sama5d2-pmc
- atmel,sama5d3-pmc
- atmel,sama5d4-pmc
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: slow_clk
- const: main_xtal
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
pmc: clock-controller@f0018000 {
compatible = "atmel,sama5d4-pmc", "syscon";
reg = <0xf0018000 0x120>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
#clock-cells = <2>;
clocks = <&clk32k>, <&main_xtal>;
clock-names = "slow_clk", "main_xtal";
};
...

70
sys/contrib/device-tree/Bindings/clock/atmel,at91sam9x5-sckc.yaml Normal file
View file

@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/atmel,at91sam9x5-sckc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel Slow Clock Controller (SCKC)
maintainers:
- Claudiu Beznea <claudiu.beznea@microchip.com>
properties:
compatible:
oneOf:
- enum:
- atmel,at91sam9x5-sckc
- atmel,sama5d3-sckc
- atmel,sama5d4-sckc
- microchip,sam9x60-sckc
- items:
- const: microchip,sama7g5-sckc
- const: microchip,sam9x60-sckc
reg:
maxItems: 1
clocks:
maxItems: 1
"#clock-cells":
enum: [0, 1]
atmel,osc-bypass:
type: boolean
description: set when a clock signal is directly provided on XIN
required:
- compatible
- reg
- clocks
- "#clock-cells"
allOf:
- if:
properties:
compatible:
contains:
enum:
- microchip,sam9x60-sckc
then:
properties:
"#clock-cells":
const: 1
else:
properties:
"#clock-cells":
const: 0
additionalProperties: false
examples:
- |
clk32k: clock-controller@fffffe50 {
compatible = "microchip,sam9x60-sckc";
reg = <0xfffffe50 0x4>;
clocks = <&slow_xtal>;
#clock-cells = <1>;
};
...

2
sys/contrib/device-tree/Bindings/clock/brcm,bcm63268-timer-clocks.yaml
View file

@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/brcm,bcm63268-timer-clocks.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM63268 Timer Clock and Reset Device Tree Bindings
title: Broadcom BCM63268 Timer Clock and Reset
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>

3
sys/contrib/device-tree/Bindings/clock/imx8m-clock.yaml
View file

@ -24,6 +24,9 @@ properties:
reg:
maxItems: 1
interrupts:
maxItems: 2
clocks:
minItems: 6
maxItems: 7

2
sys/contrib/device-tree/Bindings/clock/imx8mp-audiomix.yaml
View file

@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/imx8mp-audiomix.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8MP AudioMIX Block Control Binding
title: NXP i.MX8MP AudioMIX Block Control
maintainers:
- Marek Vasut <marex@denx.de>

4
sys/contrib/device-tree/Bindings/clock/ingenic,cgu.yaml
View file

@ -98,9 +98,9 @@ required:
patternProperties:
"^usb-phy@[a-f0-9]+$":
allOf: [ $ref: "../phy/ingenic,phy-usb.yaml#" ]
$ref: /schemas/phy/ingenic,phy-usb.yaml#
"^mac-phy-ctrl@[a-f0-9]+$":
allOf: [ $ref: "../net/ingenic,mac.yaml#" ]
$ref: /schemas/net/ingenic,mac.yaml#
additionalProperties: false

64
sys/contrib/device-tree/Bindings/clock/mediatek,mtmips-sysc.yaml Normal file
View file

@ -0,0 +1,64 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MTMIPS SoCs System Controller
maintainers:
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
description: |
MediaTek MIPS and Ralink SoCs provides a system controller to allow
to access to system control registers. These registers include clock
and reset related ones so this node is both clock and reset provider
for the rest of the world.
These SoCs have an XTAL from where the cpu clock is
provided as well as derived clocks for the bus and the peripherals.
properties:
compatible:
items:
- enum:
- ralink,mt7620-sysc
- ralink,mt7628-sysc
- ralink,mt7688-sysc
- ralink,rt2880-sysc
- ralink,rt3050-sysc
- ralink,rt3052-sysc
- ralink,rt3352-sysc
- ralink,rt3883-sysc
- ralink,rt5350-sysc
- const: syscon
reg:
maxItems: 1
'#clock-cells':
description:
The first cell indicates the clock number.
const: 1
'#reset-cells':
description:
The first cell indicates the reset bit within the register.
const: 1
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
syscon@0 {
compatible = "ralink,rt5350-sysc", "syscon";
reg = <0x0 0x100>;
#clock-cells = <1>;
#reset-cells = <1>;
};

63
sys/contrib/device-tree/Bindings/clock/nuvoton,ma35d1-clk.yaml Normal file
View file

@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Nuvoton MA35D1 Clock Controller Module
maintainers:
- Chi-Fang Li <cfli0@nuvoton.com>
- Jacky Huang <ychuang3@nuvoton.com>
description: |
The MA35D1 clock controller generates clocks for the whole chip,
including system clocks and all peripheral clocks.
See also:
include/dt-bindings/clock/ma35d1-clk.h
properties:
compatible:
items:
- const: nuvoton,ma35d1-clk
reg:
maxItems: 1
"#clock-cells":
const: 1
clocks:
maxItems: 1
nuvoton,pll-mode:
description:
A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
EPLL, and VPLL in sequential.
maxItems: 5
items:
enum:
- integer
- fractional
- spread-spectrum
$ref: /schemas/types.yaml#/definitions/non-unique-string-array
required:
- compatible
- reg
- "#clock-cells"
- clocks
additionalProperties: false
examples:
- |
clock-controller@40460200 {
compatible = "nuvoton,ma35d1-clk";
reg = <0x40460200 0x100>;
#clock-cells = <1>;
clocks = <&clk_hxt>;
};
...

1
sys/contrib/device-tree/Bindings/clock/qcom,a53pll.yaml
View file

@ -19,6 +19,7 @@ properties:
- qcom,ipq5332-a53pll
- qcom,ipq6018-a53pll
- qcom,ipq8074-a53pll
- qcom,ipq9574-a73pll
- qcom,msm8916-a53pll
- qcom,msm8939-a53pll

73
sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8953.yaml Normal file
View file

@ -0,0 +1,73 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on MSM8953
maintainers:
- Adam Skladowski <a_skl39@protonmail.com>
- Sireesh Kodali <sireeshkodali@protonmail.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8953.
See also: include/dt-bindings/clock/qcom,gcc-msm8953.h
properties:
compatible:
const: qcom,gcc-msm8953
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Byte clock from DSI PHY1
- description: Pixel clock from DSI PHY1
clock-names:
items:
- const: xo
- const: sleep
- const: dsi0pll
- const: dsi0pllbyte
- const: dsi1pll
- const: dsi1pllbyte
required:
- compatible
- clocks
- clock-names
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
clock-controller@1800000 {
compatible = "qcom,gcc-msm8953";
reg = <0x01800000 0x80000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>,
<&dsi0_phy 1>,
<&dsi0_phy 0>,
<&dsi1_phy 1>,
<&dsi1_phy 0>;
clock-names = "xo",
"sleep",
"dsi0pll",
"dsi0pllbyte",
"dsi1pll",
"dsi1pllbyte";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};

1
sys/contrib/device-tree/Bindings/clock/qcom,gcc-other.yaml
View file

@ -30,7 +30,6 @@ properties:
enum:
- qcom,gcc-ipq6018
- qcom,gcc-mdm9607
- qcom,gcc-msm8953
- qcom,gcc-mdm9615
required:

7
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc7180.yaml
View file

@ -32,6 +32,10 @@ properties:
- const: bi_tcxo_ao
- const: sleep_clk
power-domains:
items:
- description: CX domain
required:
- compatible
- clocks
@ -45,6 +49,8 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@100000 {
compatible = "qcom,gcc-sc7180";
reg = <0x00100000 0x1f0000>;
@ -52,6 +58,7 @@ examples:
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
power-domains = <&rpmhpd SC7180_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

7
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc7280.yaml
View file

@ -43,6 +43,10 @@ properties:
- const: ufs_phy_tx_symbol_0_clk
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk
power-domains:
items:
- description: CX domain
required:
- compatible
- clocks
@ -56,6 +60,8 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@100000 {
compatible = "qcom,gcc-sc7280";
reg = <0x00100000 0x1f0000>;
@ -71,6 +77,7 @@ examples:
"pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk",
"ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
power-domains = <&rpmhpd SC7280_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

5
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8250.yaml
View file

@ -23,11 +23,13 @@ properties:
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
required:
@ -47,8 +49,9 @@ examples:
compatible = "qcom,gcc-sm8250";
reg = <0x00100000 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "bi_tcxo", "sleep_clk";
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

3
sys/contrib/device-tree/Bindings/clock/qcom,gpucc.yaml
View file

@ -50,6 +50,9 @@ properties:
- const: gcc_gpu_gpll0_clk_src
- const: gcc_gpu_gpll0_div_clk_src
power-domains:
maxItems: 1
'#clock-cells':
const: 1

1
sys/contrib/device-tree/Bindings/clock/qcom,ipq9574-gcc.yaml
View file

@ -7,6 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ9574
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Anusha Rao <quic_anusha@quicinc.com>
description: |

32
sys/contrib/device-tree/Bindings/clock/qcom,mmcc.yaml
View file

@ -31,11 +31,11 @@ properties:
- qcom,mmcc-sdm660
clocks:
minItems: 8
minItems: 7
maxItems: 13
clock-names:
minItems: 8
minItems: 7
maxItems: 13
'#clock-cells':
@ -99,6 +99,34 @@ allOf:
- const: dsi2pllbyte
- const: hdmipll
- if:
properties:
compatible:
contains:
enum:
- qcom,mmcc-msm8226
then:
properties:
clocks:
items:
- description: Board XO source
- description: MMSS GPLL0 voted clock
- description: GPLL0 voted clock
- description: GPLL1 voted clock
- description: GFX3D clock source
- description: DSI phy instance 0 dsi clock
- description: DSI phy instance 0 byte clock
clock-names:
items:
- const: xo
- const: mmss_gpll0_vote
- const: gpll0_vote
- const: gpll1_vote
- const: gfx3d_clk_src
- const: dsi0pll
- const: dsi0pllbyte
- if:
properties:
compatible:

1
sys/contrib/device-tree/Bindings/clock/qcom,rpmhcc.yaml
View file

@ -27,6 +27,7 @@ properties:
- qcom,sdm845-rpmh-clk
- qcom,sdx55-rpmh-clk
- qcom,sdx65-rpmh-clk
- qcom,sdx75-rpmh-clk
- qcom,sm6350-rpmh-clk
- qcom,sm8150-rpmh-clk
- qcom,sm8250-rpmh-clk

60
sys/contrib/device-tree/Bindings/clock/qcom,sc8280xp-lpasscc.yaml Normal file
View file

@ -0,0 +1,60 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sc8280xp-lpasscc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Core & Audio Clock Controller on SC8280XP
maintainers:
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
description: |
Qualcomm LPASS core and audio clock control module provides the clocks,
and reset on SC8280XP.
See also::
include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h
properties:
compatible:
enum:
- qcom,sc8280xp-lpassaudiocc
- qcom,sc8280xp-lpasscc
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
lpass_audiocc: clock-controller@32a9000 {
compatible = "qcom,sc8280xp-lpassaudiocc";
reg = <0x032a9000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
- |
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
lpasscc: clock-controller@33e0000 {
compatible = "qcom,sc8280xp-lpasscc";
reg = <0x033e0000 0x12000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
...

65
sys/contrib/device-tree/Bindings/clock/qcom,sdx75-gcc.yaml Normal file
View file

@ -0,0 +1,65 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sdx75-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SDX75
maintainers:
- Imran Shaik <quic_imrashai@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SDX75
See also:: include/dt-bindings/clock/qcom,sdx75-gcc.h
properties:
compatible:
const: qcom,sdx75-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: EMAC0 sgmiiphy mac rclk source
- description: EMAC0 sgmiiphy mac tclk source
- description: EMAC0 sgmiiphy rclk source
- description: EMAC0 sgmiiphy tclk source
- description: EMAC1 sgmiiphy mac rclk source
- description: EMAC1 sgmiiphy mac tclk source
- description: EMAC1 sgmiiphy rclk source
- description: EMAC1 sgmiiphy tclk source
- description: PCIE20 phy aux clock source
- description: PCIE_1 Pipe clock source
- description: PCIE_2 Pipe clock source
- description: PCIE Pipe clock source
- description: USB3 phy wrapper pipe clock source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@80000 {
compatible = "qcom,sdx75-gcc";
reg = <0x80000 0x1f7400>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&emac0_sgmiiphy_mac_rclk>,
<&emac0_sgmiiphy_mac_tclk>, <&emac0_sgmiiphy_rclk>, <&emac0_sgmiiphy_tclk>,
<&emac1_sgmiiphy_mac_rclk>, <&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>,
<&emac1_sgmiiphy_tclk>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>,
<&pcie_2_pipe_clk>, <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

15
sys/contrib/device-tree/Bindings/clock/qcom,sm6375-gpucc.yaml
View file

@ -27,9 +27,21 @@ properties:
- description: GPLL0 div branch source
- description: SNoC DVM GFX source
power-domains:
description:
A phandle and PM domain specifier for the VDD_GX power rail
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required VDD_GX performance point.
maxItems: 1
required:
- compatible
- clocks
- power-domains
- required-opps
allOf:
- $ref: qcom,gcc.yaml#
@ -40,6 +52,7 @@ examples:
- |
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
soc {
#address-cells = <2>;
@ -52,6 +65,8 @@ examples:
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
power-domains = <&rpmpd SM6375_VDDGX>;
required-opps = <&rpmpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

68
sys/contrib/device-tree/Bindings/clock/qcom,sm8350-videocc.yaml Normal file
View file

@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8350-videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8350 Video Clock & Reset Controller
maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
Qualcomm video clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also::
include/dt-bindings/clock/qcom,videocc-sm8350.h
include/dt-bindings/reset/qcom,videocc-sm8350.h
properties:
compatible:
const: qcom,sm8350-videocc
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Board sleep clock
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
required:
- compatible
- clocks
- power-domains
- required-opps
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@abf0000 {
compatible = "qcom,sm8350-videocc";
reg = <0x0abf0000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd SM8350_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

75
sys/contrib/device-tree/Bindings/clock/qcom,sm8450-gpucc.yaml Normal file
View file

@ -0,0 +1,75 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SM8450
maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
Qualcomm graphics clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also::
include/dt-bindings/clock/qcom,sm8450-gpucc.h
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h
properties:
compatible:
enum:
- qcom,sm8450-gpucc
- qcom,sm8550-gpucc
clocks:
items:
- description: Board XO source
- description: GPLL0 main branch source
- description: GPLL0 div branch source
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@3d90000 {
compatible = "qcom,sm8450-gpucc";
reg = <0 0x03d90000 0 0xa000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
};
...

79
sys/contrib/device-tree/Bindings/clock/qcom,sm8450-videocc.yaml Normal file
View file

@ -0,0 +1,79 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Video Clock & Reset Controller on SM8450
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm video clock control module provides the clocks, resets and power
domains on SM8450.
See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h
properties:
compatible:
enum:
- qcom,sm8450-videocc
- qcom,sm8550-videocc
reg:
maxItems: 1
clocks:
items:
- description: Board XO source
- description: Video AHB clock from GCC
power-domains:
maxItems: 1
description:
MMCX power domain.
required-opps:
maxItems: 1
description:
A phandle to an OPP node describing required MMCX performance point.
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- power-domains
- required-opps
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
videocc: clock-controller@aaf0000 {
compatible = "qcom,sm8450-videocc";
reg = <0x0aaf0000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_VIDEO_AHB_CLK>;
power-domains = <&rpmhpd SM8450_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

2
sys/contrib/device-tree/Bindings/clock/renesas,r9a06g032-sysctrl.yaml
View file

@ -48,7 +48,7 @@ properties:
patternProperties:
"^dma-router@[a-f0-9]+$":
type: object
$ref: "../dma/renesas,rzn1-dmamux.yaml#"
$ref: /schemas/dma/renesas,rzn1-dmamux.yaml#
required:
- compatible

1
sys/contrib/device-tree/Bindings/clock/samsung,exynos-clock.yaml
View file

@ -24,6 +24,7 @@ properties:
- samsung,exynos3250-cmu-dmc
- samsung,exynos3250-cmu-isp
- samsung,exynos4210-clock
- samsung,exynos4212-clock
- samsung,exynos4412-clock
- samsung,exynos5250-clock
- items:

43
sys/contrib/device-tree/Bindings/clock/ti,am62-audio-refclk.yaml Normal file
View file

@ -0,0 +1,43 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/ti,am62-audio-refclk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI Audio Reference Clock
maintainers:
- Jai Luthra <j-luthra@ti.com>
properties:
compatible:
items:
- const: ti,am62-audio-refclk
reg:
maxItems: 1
"#clock-cells":
const: 0
clocks:
maxItems: 1
required:
- compatible
- reg
- "#clock-cells"
- clocks
additionalProperties: false
examples:
- |
audio_refclk0: clock@82e0 {
compatible = "ti,am62-audio-refclk";
reg = <0x82e0 0x4>;
clocks = <&k3_clks 157 0>;
assigned-clocks = <&k3_clks 157 0>;
assigned-clock-parents = <&k3_clks 157 8>;
#clock-cells = <0>;
};

5
sys/contrib/device-tree/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml
View file

@ -16,7 +16,6 @@ properties:
- ti,am654-ehrpwm-tbclk
- ti,am64-epwm-tbclk
- ti,am62-epwm-tbclk
- const: syscon
"#clock-cells":
const: 1
@ -33,8 +32,8 @@ additionalProperties: false
examples:
- |
ehrpwm_tbclk: syscon@4140 {
compatible = "ti,am654-ehrpwm-tbclk", "syscon";
ehrpwm_tbclk: clock@4140 {
compatible = "ti,am654-ehrpwm-tbclk";
reg = <0x4140 0x18>;
#clock-cells = <1>;
};

2
sys/contrib/device-tree/Bindings/clock/xlnx,clocking-wizard.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx clocking wizard
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
description:
The clocking wizard is a soft ip clocking block of Xilinx versal. It

4
sys/contrib/device-tree/Bindings/clock/xlnx,versal-clk.yaml
View file

@ -7,9 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Versal clock controller
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Jolly Shah <jolly.shah@xilinx.com>
- Rajan Vaja <rajan.vaja@xilinx.com>
- Michal Simek <michal.simek@amd.com>
description: |
The clock controller is a hardware block of Xilinx versal clock tree. It

20
sys/contrib/device-tree/Bindings/connector/usb-connector.yaml
View file

@ -168,6 +168,13 @@ properties:
offer the power, Capability Mismatch is set. Required for power sink and
power dual role.
port:
$ref: /schemas/graph.yaml#/properties/port
description: OF graph bindings modeling a data bus to the connector, e.g.
there is a single High Speed (HS) port present in this connector. If there
is more than one bus (several port, with 'reg' property), they can be grouped
under 'ports'.
ports:
$ref: /schemas/graph.yaml#/properties/ports
description: OF graph bindings modeling any data bus to the connector
@ -322,6 +329,19 @@ examples:
};
};
# USB-C connector attached to SoC with a single High-Speed controller
- |
connector {
compatible = "usb-c-connector";
label = "USB-C";
port {
high_speed_ep: endpoint {
remote-endpoint = <&usb_hs_ep>;
};
};
};
# USB-C connector attached to SoC and USB3 typec port controller(hd3ss3220)
# with SS 2:1 MUX. HS lines routed to SoC, SS lines routed to the MUX and
# the output of MUX is connected to the SoC.

2
sys/contrib/device-tree/Bindings/cpu/idle-states.yaml
View file

@ -259,7 +259,7 @@ description: |+
http://infocenter.arm.com/help/index.jsp
[5] ARM Linux Kernel documentation - Booting AArch64 Linux
Documentation/arm64/booting.rst
Documentation/arch/arm64/booting.rst
[6] RISC-V Linux Kernel documentation - CPUs bindings
Documentation/devicetree/bindings/riscv/cpus.yaml

1
sys/contrib/device-tree/Bindings/cpufreq/qcom-cpufreq-nvmem.yaml
View file

@ -28,6 +28,7 @@ select:
- qcom,apq8064
- qcom,apq8096
- qcom,ipq8064
- qcom,ipq8074
- qcom,msm8939
- qcom,msm8960
- qcom,msm8974

4
sys/contrib/device-tree/Bindings/crypto/amlogic,gxl-crypto.yaml
View file

@ -19,8 +19,8 @@ properties:
interrupts:
items:
- description: "Interrupt for flow 0"
- description: "Interrupt for flow 1"
- description: Interrupt for flow 0
- description: Interrupt for flow 1
clocks:
maxItems: 1

6
sys/contrib/device-tree/Bindings/crypto/fsl,sec-v4.0-mon.yaml
View file

@ -103,6 +103,12 @@ properties:
wakeup-source: true
linux,keycode:
$ref: /schemas/types.yaml#/definitions/uint32
default: 116
deprecated: true
linux,keycodes:
maxItems: 1
default: 116
required:

12
sys/contrib/device-tree/Bindings/crypto/fsl-dcp.yaml
View file

@ -11,9 +11,15 @@ maintainers:
properties:
compatible:
enum:
- fsl,imx23-dcp
- fsl,imx28-dcp
oneOf:
- enum:
- fsl,imx23-dcp
- fsl,imx28-dcp
- items:
- enum:
- fsl,imx6sl-dcp
- fsl,imx6ull-dcp
- const: fsl,imx28-dcp
reg:
maxItems: 1

6
sys/contrib/device-tree/Bindings/crypto/intel,ixp4xx-crypto.yaml
View file

@ -2,8 +2,8 @@
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel IXP4xx cryptographic engine
@ -21,7 +21,7 @@ properties:
const: intel,ixp4xx-crypto
intel,npe-handle:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to the NPE this crypto engine

52
sys/contrib/device-tree/Bindings/crypto/qcom-qce.yaml
View file

@ -24,12 +24,20 @@ properties:
deprecated: true
description: Kept only for ABI backward compatibility
- items:
- enum:
- qcom,ipq4019-qce
- qcom,sm8150-qce
- const: qcom,qce
- items:
- enum:
- qcom,ipq6018-qce
- qcom,ipq8074-qce
- qcom,msm8996-qce
- qcom,qcm2290-qce
- qcom,sdm845-qce
- qcom,sm6115-qce
- const: qcom,ipq4019-qce
- const: qcom,qce
@ -46,16 +54,12 @@ properties:
maxItems: 1
clocks:
items:
- description: iface clocks register interface.
- description: bus clocks data transfer interface.
- description: core clocks rest of the crypto block.
minItems: 1
maxItems: 3
clock-names:
items:
- const: iface
- const: bus
- const: core
minItems: 1
maxItems: 3
iommus:
minItems: 1
@ -89,9 +93,37 @@ allOf:
enum:
- qcom,crypto-v5.1
- qcom,crypto-v5.4
- qcom,ipq4019-qce
- qcom,ipq6018-qce
- qcom,ipq8074-qce
- qcom,msm8996-qce
- qcom,sdm845-qce
then:
properties:
clocks:
maxItems: 3
clock-names:
items:
- const: iface
- const: bus
- const: core
required:
- clocks
- clock-names
- if:
properties:
compatible:
contains:
enum:
- qcom,qcm2290-qce
- qcom,sm6115-qce
then:
properties:
clocks:
maxItems: 1
clock-names:
items:
- const: core
required:
- clocks
- clock-names

70
sys/contrib/device-tree/Bindings/crypto/starfive,jh7110-crypto.yaml Normal file
View file

@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/starfive,jh7110-crypto.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: StarFive Cryptographic Module
maintainers:
- Jia Jie Ho <jiajie.ho@starfivetech.com>
- William Qiu <william.qiu@starfivetech.com>
properties:
compatible:
const: starfive,jh7110-crypto
reg:
maxItems: 1
clocks:
items:
- description: Hardware reference clock
- description: AHB reference clock
clock-names:
items:
- const: hclk
- const: ahb
interrupts:
maxItems: 1
resets:
maxItems: 1
dmas:
items:
- description: TX DMA channel
- description: RX DMA channel
dma-names:
items:
- const: tx
- const: rx
required:
- compatible
- reg
- clocks
- clock-names
- resets
- dmas
- dma-names
additionalProperties: false
examples:
- |
crypto: crypto@16000000 {
compatible = "starfive,jh7110-crypto";
reg = <0x16000000 0x4000>;
clocks = <&clk 15>, <&clk 16>;
clock-names = "hclk", "ahb";
interrupts = <28>;
resets = <&reset 3>;
dmas = <&dma 1 2>,
<&dma 0 2>;
dma-names = "tx", "rx";
};
...

4
sys/contrib/device-tree/Bindings/crypto/xlnx,zynqmp-aes.yaml
View file

@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP AES-GCM Hardware Accelerator
maintainers:
- Kalyani Akula <kalyani.akula@xilinx.com>
- Michal Simek <michal.simek@xilinx.com>
- Kalyani Akula <kalyani.akula@amd.com>
- Michal Simek <michal.simek@amd.com>
description: |
The ZynqMP AES-GCM hardened cryptographic accelerator is used to

118
sys/contrib/device-tree/Bindings/display/amlogic,meson-g12a-dw-mipi-dsi.yaml Normal file
View file

@ -0,0 +1,118 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright 2020 BayLibre, SAS
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/amlogic,meson-g12a-dw-mipi-dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
The Amlogic Meson Synopsys Designware Integration is composed of
- A Synopsys DesignWare MIPI DSI Host Controller IP
- A TOP control block controlling the Clocks & Resets of the IP
allOf:
- $ref: dsi-controller.yaml#
properties:
compatible:
enum:
- amlogic,meson-g12a-dw-mipi-dsi
reg:
maxItems: 1
clocks:
minItems: 3
maxItems: 4
clock-names:
minItems: 3
items:
- const: pclk
- const: bit
- const: px
- const: meas
resets:
maxItems: 1
reset-names:
items:
- const: top
phys:
maxItems: 1
phy-names:
items:
- const: dphy
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Input node to receive pixel data.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: DSI output node to panel.
required:
- port@0
- port@1
required:
- compatible
- reg
- clocks
- clock-names
- resets
- reset-names
- phys
- phy-names
- ports
unevaluatedProperties: false
examples:
- |
dsi@6000 {
compatible = "amlogic,meson-g12a-dw-mipi-dsi";
reg = <0x6000 0x400>;
resets = <&reset_top>;
reset-names = "top";
clocks = <&clk_pclk>, <&bit_clk>, <&clk_px>;
clock-names = "pclk", "bit", "px";
phys = <&mipi_dphy>;
phy-names = "dphy";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* VPU VENC Input */
mipi_dsi_venc_port: port@0 {
reg = <0>;
mipi_dsi_in: endpoint {
remote-endpoint = <&dpi_out>;
};
};
/* DSI Output */
mipi_dsi_panel_port: port@1 {
reg = <1>;
mipi_out_panel: endpoint {
remote-endpoint = <&mipi_in_panel>;
};
};
};
};

5
sys/contrib/device-tree/Bindings/display/amlogic,meson-vpu.yaml
View file

@ -96,6 +96,11 @@ properties:
description:
A port node pointing to the HDMI-TX port node.
port@2:
$ref: /schemas/graph.yaml#/properties/port
description:
A port node pointing to the DPI port node (e.g. DSI or LVDS transceiver).
"#address-cells":
const: 1

1
sys/contrib/device-tree/Bindings/display/bridge/analogix,dp.yaml
View file

@ -26,6 +26,7 @@ properties:
const: dp
force-hpd:
type: boolean
description:
Indicate driver need force hpd when hpd detect failed, this
is used for some eDP screen which don not have a hpd signal.

5
sys/contrib/device-tree/Bindings/display/bridge/fsl,ldb.yaml
View file

@ -17,6 +17,7 @@ description: |
properties:
compatible:
enum:
- fsl,imx6sx-ldb
- fsl,imx8mp-ldb
- fsl,imx93-ldb
@ -64,7 +65,9 @@ allOf:
properties:
compatible:
contains:
const: fsl,imx93-ldb
enum:
- fsl,imx6sx-ldb
- fsl,imx93-ldb
then:
properties:
ports:

1
sys/contrib/device-tree/Bindings/display/bridge/nxp,tda998x.yaml
View file

@ -20,6 +20,7 @@ properties:
maxItems: 1
video-ports:
$ref: /schemas/types.yaml#/definitions/uint32
default: 0x230145
maximum: 0xffffff
description:

35
sys/contrib/device-tree/Bindings/display/bridge/samsung,mipi-dsim.yaml
View file

@ -70,7 +70,9 @@ properties:
samsung,burst-clock-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description:
DSIM high speed burst mode frequency.
DSIM high speed burst mode frequency. If absent,
the pixel clock from the attached device or bridge
will be used instead.
samsung,esc-clock-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
@ -80,7 +82,8 @@ properties:
samsung,pll-clock-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description:
DSIM oscillator clock frequency.
DSIM oscillator clock frequency. If absent, the clock frequency
of sclk_mipi will be used instead.
phys:
maxItems: 1
@ -100,20 +103,42 @@ properties:
specified.
port@1:
$ref: /schemas/graph.yaml#/properties/port
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
DSI output port node to the panel or the next bridge
in the chain.
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
uniqueItems: true
items:
enum: [ 1, 2, 3, 4 ]
lane-polarities:
minItems: 1
maxItems: 5
description:
The Samsung MIPI DSI IP requires that all the data lanes have
the same polarity.
dependencies:
lane-polarities: [data-lanes]
required:
- clock-names
- clocks
- compatible
- interrupts
- reg
- samsung,burst-clock-frequency
- samsung,esc-clock-frequency
- samsung,pll-clock-frequency
allOf:
- $ref: ../dsi-controller.yaml#

3
sys/contrib/device-tree/Bindings/display/bridge/toshiba,tc358762.yaml
View file

@ -21,6 +21,9 @@ properties:
maxItems: 1
description: virtual channel number of a DSI peripheral
reset-gpios:
maxItems: 1
vddc-supply:
description: Regulator for 1.2V internal core power.

14
sys/contrib/device-tree/Bindings/display/bridge/toshiba,tc358767.yaml
View file

@ -4,16 +4,24 @@
$id: http://devicetree.org/schemas/display/bridge/toshiba,tc358767.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Toshiba TC358767 eDP bridge
title: Toshiba TC358767/TC358867/TC9595 DSI/DPI/eDP bridge
maintainers:
- Andrey Gusakov <andrey.gusakov@cogentembedded.com>
description: The TC358767 is bridge device which converts DSI/DPI to eDP/DP
description: |
The TC358767/TC358867/TC9595 is bridge device which
converts DSI/DPI to eDP/DP .
properties:
compatible:
const: toshiba,tc358767
oneOf:
- items:
- enum:
- toshiba,tc358867
- toshiba,tc9595
- const: toshiba,tc358767
- const: toshiba,tc358767
reg:
enum:

3
sys/contrib/device-tree/Bindings/display/connector/hdmi-connector.yaml
View file

@ -36,6 +36,9 @@ properties:
description: GPIO signal to enable DDC bus
maxItems: 1
hdmi-pwr-supply:
description: Power supply for the HDMI +5V Power pin
port:
$ref: /schemas/graph.yaml#/properties/port
description: Connection to controller providing HDMI signals

7
sys/contrib/device-tree/Bindings/display/fsl,lcdif.yaml
View file

@ -21,6 +21,7 @@ properties:
- fsl,imx28-lcdif
- fsl,imx6sx-lcdif
- fsl,imx8mp-lcdif
- fsl,imx93-lcdif
- items:
- enum:
- fsl,imx6sl-lcdif
@ -88,7 +89,9 @@ allOf:
properties:
compatible:
contains:
const: fsl,imx8mp-lcdif
enum:
- fsl,imx8mp-lcdif
- fsl,imx93-lcdif
then:
properties:
clocks:
@ -107,6 +110,7 @@ allOf:
enum:
- fsl,imx6sx-lcdif
- fsl,imx8mp-lcdif
- fsl,imx93-lcdif
then:
properties:
clocks:
@ -123,6 +127,7 @@ allOf:
- fsl,imx8mm-lcdif
- fsl,imx8mn-lcdif
- fsl,imx8mp-lcdif
- fsl,imx93-lcdif
then:
required:
- power-domains

1
sys/contrib/device-tree/Bindings/display/mediatek/mediatek,aal.yaml
View file

@ -27,6 +27,7 @@ properties:
- items:
- enum:
- mediatek,mt2712-disp-aal
- mediatek,mt6795-disp-aal
- const: mediatek,mt8173-disp-aal
- items:
- enum:

1
sys/contrib/device-tree/Bindings/display/mediatek/mediatek,color.yaml
View file

@ -33,6 +33,7 @@ properties:
- const: mediatek,mt2701-disp-color
- items:
- enum:
- mediatek,mt6795-disp-color
- mediatek,mt8183-disp-color
- mediatek,mt8186-disp-color
- mediatek,mt8188-disp-color

23
sys/contrib/device-tree/Bindings/display/mediatek/mediatek,dpi.yaml
View file

@ -17,15 +17,20 @@ description: |
properties:
compatible:
enum:
- mediatek,mt2701-dpi
- mediatek,mt7623-dpi
- mediatek,mt8173-dpi
- mediatek,mt8183-dpi
- mediatek,mt8186-dpi
- mediatek,mt8188-dp-intf
- mediatek,mt8192-dpi
- mediatek,mt8195-dp-intf
oneOf:
- enum:
- mediatek,mt2701-dpi
- mediatek,mt7623-dpi
- mediatek,mt8173-dpi
- mediatek,mt8183-dpi
- mediatek,mt8186-dpi
- mediatek,mt8188-dp-intf
- mediatek,mt8192-dpi
- mediatek,mt8195-dp-intf
- items:
- enum:
- mediatek,mt6795-dpi
- const: mediatek,mt8183-dpi
reg:
maxItems: 1

19
sys/contrib/device-tree/Bindings/display/mediatek/mediatek,dsi.yaml
View file

@ -22,13 +22,18 @@ allOf:
properties:
compatible:
enum:
- mediatek,mt2701-dsi
- mediatek,mt7623-dsi
- mediatek,mt8167-dsi
- mediatek,mt8173-dsi
- mediatek,mt8183-dsi
- mediatek,mt8186-dsi
oneOf:
- enum:
- mediatek,mt2701-dsi
- mediatek,mt7623-dsi
- mediatek,mt8167-dsi
- mediatek,mt8173-dsi
- mediatek,mt8183-dsi
- mediatek,mt8186-dsi
- items:
- enum:
- mediatek,mt6795-dsi
- const: mediatek,mt8173-dsi
reg:
maxItems: 1

4
sys/contrib/device-tree/Bindings/display/mediatek/mediatek,gamma.yaml
View file

@ -24,6 +24,10 @@ properties:
- enum:
- mediatek,mt8173-disp-gamma
- mediatek,mt8183-disp-gamma
- items:
- enum:
- mediatek,mt6795-disp-gamma
- const: mediatek,mt8173-disp-gamma
- items:
- enum:
- mediatek,mt8186-disp-gamma

3
sys/contrib/device-tree/Bindings/display/mediatek/mediatek,merge.yaml
View file

@ -24,6 +24,9 @@ properties:
- enum:
- mediatek,mt8173-disp-merge
- mediatek,mt8195-disp-merge
- items:
- const: mediatek,mt6795-disp-merge
- const: mediatek,mt8173-disp-merge
reg:
maxItems: 1

3
sys/contrib/device-tree/Bindings/display/mediatek/mediatek,od.yaml
View file

@ -24,6 +24,9 @@ properties:
- enum:
- mediatek,mt2712-disp-od
- mediatek,mt8173-disp-od
- items:
- const: mediatek,mt6795-disp-od
- const: mediatek,mt8173-disp-od
reg:
maxItems: 1

4
sys/contrib/device-tree/Bindings/display/mediatek/mediatek,ovl.yaml
View file

@ -31,6 +31,10 @@ properties:
- mediatek,mt7623-disp-ovl
- mediatek,mt2712-disp-ovl
- const: mediatek,mt2701-disp-ovl
- items:
- enum:
- mediatek,mt6795-disp-ovl
- const: mediatek,mt8173-disp-ovl
- items:
- enum:
- mediatek,mt8188-disp-ovl

4
sys/contrib/device-tree/Bindings/display/mediatek/mediatek,rdma.yaml
View file

@ -37,6 +37,10 @@ properties:
- mediatek,mt7623-disp-rdma
- mediatek,mt2712-disp-rdma
- const: mediatek,mt2701-disp-rdma
- items:
- enum:
- mediatek,mt6795-disp-rdma
- const: mediatek,mt8173-disp-rdma
- items:
- enum:
- mediatek,mt8186-disp-rdma

3
sys/contrib/device-tree/Bindings/display/mediatek/mediatek,split.yaml
View file

@ -23,6 +23,9 @@ properties:
oneOf:
- enum:
- mediatek,mt8173-disp-split
- items:
- const: mediatek,mt6795-disp-split
- const: mediatek,mt8173-disp-split
reg:
maxItems: 1

3
sys/contrib/device-tree/Bindings/display/mediatek/mediatek,ufoe.yaml
View file

@ -24,6 +24,9 @@ properties:
oneOf:
- enum:
- mediatek,mt8173-disp-ufoe
- items:
- const: mediatek,mt6795-disp-ufoe
- const: mediatek,mt8173-disp-ufoe
reg:
maxItems: 1

3
sys/contrib/device-tree/Bindings/display/mediatek/mediatek,wdma.yaml
View file

@ -23,6 +23,9 @@ properties:
oneOf:
- enum:
- mediatek,mt8173-disp-wdma
- items:
- const: mediatek,mt6795-disp-wdma
- const: mediatek,mt8173-disp-wdma
reg:
maxItems: 1

1
sys/contrib/device-tree/Bindings/display/msm/dp-controller.yaml
View file

@ -29,6 +29,7 @@ properties:
- items:
- enum:
- qcom,sm8450-dp
- qcom,sm8550-dp
- const: qcom,sm8350-dp
reg:

6
sys/contrib/device-tree/Bindings/display/msm/dsi-controller-main.yaml
View file

@ -15,6 +15,7 @@ properties:
- items:
- enum:
- qcom,apq8064-dsi-ctrl
- qcom,msm8226-dsi-ctrl
- qcom,msm8916-dsi-ctrl
- qcom,msm8953-dsi-ctrl
- qcom,msm8974-dsi-ctrl
@ -26,6 +27,8 @@ properties:
- qcom,sdm660-dsi-ctrl
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
- qcom,sm6350-dsi-ctrl
- qcom,sm6375-dsi-ctrl
- qcom,sm8150-dsi-ctrl
- qcom,sm8250-dsi-ctrl
- qcom,sm8350-dsi-ctrl
@ -256,6 +259,7 @@ allOf:
compatible:
contains:
enum:
- qcom,msm8226-dsi-ctrl
- qcom,msm8974-dsi-ctrl
then:
properties:
@ -297,6 +301,7 @@ allOf:
contains:
enum:
- qcom,msm8998-dsi-ctrl
- qcom,sm6350-dsi-ctrl
then:
properties:
clocks:
@ -364,6 +369,7 @@ allOf:
enum:
- qcom,sdm845-dsi-ctrl
- qcom,sm6115-dsi-ctrl
- qcom,sm6375-dsi-ctrl
then:
properties:
clocks:

3
sys/contrib/device-tree/Bindings/display/msm/dsi-phy-28nm.yaml
View file

@ -15,10 +15,11 @@ allOf:
properties:
compatible:
enum:
- qcom,dsi-phy-28nm-8226
- qcom,dsi-phy-28nm-8960
- qcom,dsi-phy-28nm-hpm
- qcom,dsi-phy-28nm-hpm-fam-b
- qcom,dsi-phy-28nm-lp
- qcom,dsi-phy-28nm-8960
reg:
items:

53
sys/contrib/device-tree/Bindings/display/msm/gmu.yaml
View file

@ -19,16 +19,18 @@ description: |
properties:
compatible:
items:
- pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
- const: qcom,adreno-gmu
oneOf:
- items:
- pattern: '^qcom,adreno-gmu-6[0-9][0-9]\.[0-9]$'
- const: qcom,adreno-gmu
- const: qcom,adreno-gmu-wrapper
reg:
minItems: 3
minItems: 1
maxItems: 4
reg-names:
minItems: 3
minItems: 1
maxItems: 4
clocks:
@ -44,7 +46,6 @@ properties:
- description: GMU HFI interrupt
- description: GMU interrupt
interrupt-names:
items:
- const: hfi
@ -72,14 +73,8 @@ required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- interrupts
- interrupt-names
- power-domains
- power-domain-names
- iommus
- operating-points-v2
additionalProperties: false
@ -122,6 +117,7 @@ allOf:
contains:
enum:
- qcom,adreno-gmu-635.0
- qcom,adreno-gmu-660.1
then:
properties:
reg:
@ -217,6 +213,28 @@ allOf:
- const: axi
- const: memnoc
- if:
properties:
compatible:
contains:
const: qcom,adreno-gmu-wrapper
then:
properties:
reg:
items:
- description: GMU wrapper register space
reg-names:
items:
- const: gmu
else:
required:
- clocks
- clock-names
- interrupts
- interrupt-names
- iommus
- operating-points-v2
examples:
- |
#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
@ -225,7 +243,7 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
gmu: gmu@506a000 {
compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
reg = <0x506a000 0x30000>,
<0xb280000 0x10000>,
@ -249,3 +267,12 @@ examples:
iommus = <&adreno_smmu 5>;
operating-points-v2 = <&gmu_opp_table>;
};
gmu_wrapper: gmu@596a000 {
compatible = "qcom,adreno-gmu-wrapper";
reg = <0x0596a000 0x30000>;
reg-names = "gmu";
power-domains = <&gpucc GPU_CX_GDSC>,
<&gpucc GPU_GX_GDSC>;
power-domain-names = "cx", "gx";
};

61
sys/contrib/device-tree/Bindings/display/msm/gpu.yaml
View file

@ -36,10 +36,7 @@ properties:
reg-names:
minItems: 1
items:
- const: kgsl_3d0_reg_memory
- const: cx_mem
- const: cx_dbgc
maxItems: 3
interrupts:
maxItems: 1
@ -157,16 +154,62 @@ allOf:
required:
- clocks
- clock-names
- if:
properties:
compatible:
contains:
pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
then: # Since Adreno 6xx series clocks should be defined in GMU
enum:
- qcom,adreno-610.0
- qcom,adreno-619.1
then:
properties:
clocks: false
clock-names: false
clocks:
minItems: 6
maxItems: 6
clock-names:
items:
- const: core
description: GPU Core clock
- const: iface
description: GPU Interface clock
- const: mem_iface
description: GPU Memory Interface clock
- const: alt_mem_iface
description: GPU Alternative Memory Interface clock
- const: gmu
description: CX GMU clock
- const: xo
description: GPUCC clocksource clock
reg-names:
minItems: 1
items:
- const: kgsl_3d0_reg_memory
- const: cx_dbgc
required:
- clocks
- clock-names
else:
if:
properties:
compatible:
contains:
pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
then: # Starting with A6xx, the clocks are usually defined in the GMU node
properties:
clocks: false
clock-names: false
reg-names:
minItems: 1
items:
- const: kgsl_3d0_reg_memory
- const: cx_mem
- const: cx_dbgc
examples:
- |

1
sys/contrib/device-tree/Bindings/display/msm/qcom,mdp5.yaml
View file

@ -22,6 +22,7 @@ properties:
- items:
- enum:
- qcom,apq8084-mdp5
- qcom,msm8226-mdp5
- qcom,msm8916-mdp5
- qcom,msm8917-mdp5
- qcom,msm8953-mdp5

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