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Implement real read/write barriers for the i386. Despite the comment in

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previous versions of this file, some barrier functionality is required.
This commit is contained in:
Mike Smith 2000-05-18 00:06:10 +00:00
parent b75cda591f
commit f0ba8e211c
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=60672
6 changed files with 90 additions and 24 deletions
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19
sys/amd64/include/bus_amd64.h
View file

@ -1134,14 +1134,25 @@ bus_space_copy_region_4(bus_space_tag_t tag, bus_space_handle_t bsh1,
* void bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, bus_size_t len, int flags);
*
* Note: the i386 does not currently require barriers, but we must
* provide the flags to MI code.
*
* Note that BUS_SPACE_BARRIER_WRITE doesn't do anything other than
* prevent reordering by the compiler; all Intel x86 processors currently
* retire operations outside the CPU in program order.
*/
#define bus_space_barrier(t, h, o, l, f) \
((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
static __inline void
bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh,
bus_size_t offset, bus_size_t len, int flags)
{
if (flags & BUS_SPACE_BARRIER_READ)
__asm __volatile ("lock; addl $0,0(%esp)" : : : "memory");
else
__asm __volatile ("" : : : "memory");
}
/*
* Flags used in various bus DMA methods.
*/

19
sys/amd64/include/bus_at386.h
View file

@ -1134,14 +1134,25 @@ bus_space_copy_region_4(bus_space_tag_t tag, bus_space_handle_t bsh1,
* void bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, bus_size_t len, int flags);
*
* Note: the i386 does not currently require barriers, but we must
* provide the flags to MI code.
*
* Note that BUS_SPACE_BARRIER_WRITE doesn't do anything other than
* prevent reordering by the compiler; all Intel x86 processors currently
* retire operations outside the CPU in program order.
*/
#define bus_space_barrier(t, h, o, l, f) \
((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
static __inline void
bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh,
bus_size_t offset, bus_size_t len, int flags)
{
if (flags & BUS_SPACE_BARRIER_READ)
__asm __volatile ("lock; addl $0,0(%esp)" : : : "memory");
else
__asm __volatile ("" : : : "memory");
}
/*
* Flags used in various bus DMA methods.
*/

19
sys/amd64/include/bus_dma.h
View file

@ -1134,14 +1134,25 @@ bus_space_copy_region_4(bus_space_tag_t tag, bus_space_handle_t bsh1,
* void bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, bus_size_t len, int flags);
*
* Note: the i386 does not currently require barriers, but we must
* provide the flags to MI code.
*
* Note that BUS_SPACE_BARRIER_WRITE doesn't do anything other than
* prevent reordering by the compiler; all Intel x86 processors currently
* retire operations outside the CPU in program order.
*/
#define bus_space_barrier(t, h, o, l, f) \
((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
static __inline void
bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh,
bus_size_t offset, bus_size_t len, int flags)
{
if (flags & BUS_SPACE_BARRIER_READ)
__asm __volatile ("lock; addl $0,0(%esp)" : : : "memory");
else
__asm __volatile ("" : : : "memory");
}
/*
* Flags used in various bus DMA methods.
*/

19
sys/i386/include/bus_at386.h
View file

@ -1134,14 +1134,25 @@ bus_space_copy_region_4(bus_space_tag_t tag, bus_space_handle_t bsh1,
* void bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, bus_size_t len, int flags);
*
* Note: the i386 does not currently require barriers, but we must
* provide the flags to MI code.
*
* Note that BUS_SPACE_BARRIER_WRITE doesn't do anything other than
* prevent reordering by the compiler; all Intel x86 processors currently
* retire operations outside the CPU in program order.
*/
#define bus_space_barrier(t, h, o, l, f) \
((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
static __inline void
bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh,
bus_size_t offset, bus_size_t len, int flags)
{
if (flags & BUS_SPACE_BARRIER_READ)
__asm __volatile ("lock; addl $0,0(%esp)" : : : "memory");
else
__asm __volatile ("" : : : "memory");
}
/*
* Flags used in various bus DMA methods.
*/

19
sys/i386/include/bus_dma.h
View file

@ -1134,14 +1134,25 @@ bus_space_copy_region_4(bus_space_tag_t tag, bus_space_handle_t bsh1,
* void bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, bus_size_t len, int flags);
*
* Note: the i386 does not currently require barriers, but we must
* provide the flags to MI code.
*
* Note that BUS_SPACE_BARRIER_WRITE doesn't do anything other than
* prevent reordering by the compiler; all Intel x86 processors currently
* retire operations outside the CPU in program order.
*/
#define bus_space_barrier(t, h, o, l, f) \
((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
static __inline void
bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh,
bus_size_t offset, bus_size_t len, int flags)
{
if (flags & BUS_SPACE_BARRIER_READ)
__asm __volatile ("lock; addl $0,0(%esp)" : : : "memory");
else
__asm __volatile ("" : : : "memory");
}
/*
* Flags used in various bus DMA methods.
*/

19
sys/sys/bus_dma.h
View file

@ -1134,14 +1134,25 @@ bus_space_copy_region_4(bus_space_tag_t tag, bus_space_handle_t bsh1,
* void bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh,
* bus_size_t offset, bus_size_t len, int flags);
*
* Note: the i386 does not currently require barriers, but we must
* provide the flags to MI code.
*
* Note that BUS_SPACE_BARRIER_WRITE doesn't do anything other than
* prevent reordering by the compiler; all Intel x86 processors currently
* retire operations outside the CPU in program order.
*/
#define bus_space_barrier(t, h, o, l, f) \
((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
static __inline void
bus_space_barrier(bus_space_tag_t tag, bus_space_handle_t bsh,
bus_size_t offset, bus_size_t len, int flags)
{
if (flags & BUS_SPACE_BARRIER_READ)
__asm __volatile ("lock; addl $0,0(%esp)" : : : "memory");
else
__asm __volatile ("" : : : "memory");
}
/*
* Flags used in various bus DMA methods.
*/