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riscv: Introduce support for APLIC interrupt controller
This patch introduces support for the RISC-V APLIC interrupt controller [1]. Currently, it is only supports direct mode, i.e. without an IMSIC and functionally replacing the legacy RISC-V PLIC. Work on IMSIC support is in progress. [1] https://github.com/riscv/riscv-aia/releases/tag/1.0 Reviewed by: mhorne Discussed with: jrtc27 MFC after: 1 month Differential Revision: https://reviews.freebsd.org/D43293
This commit is contained in:
Himanshu Chauhan
Mitchell Horne
parent
3fb8f1272b
commit
ee91dae43d
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@ -27,6 +27,7 @@ libkern/memset.c standard
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libkern/strcmp.c standard
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libkern/strlen.c standard
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libkern/strncmp.c standard
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riscv/riscv/aplic.c standard
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riscv/riscv/autoconf.c standard
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riscv/riscv/bus_machdep.c standard
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riscv/riscv/bus_space_asm.S standard
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554
sys/riscv/riscv/aplic.c
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554
sys/riscv/riscv/aplic.c
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@ -0,0 +1,554 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2024 Himanshu Chauhan <hchauhan@thechauhan.dev>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/module.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <sys/smp.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/riscvreg.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "pic_if.h"
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#define APLIC_MAX_IRQS 1023
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/* Smaller priority number means higher priority */
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#define APLIC_INTR_DEF_PRIO 1
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static pic_disable_intr_t aplic_disable_intr;
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static pic_enable_intr_t aplic_enable_intr;
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static pic_map_intr_t aplic_map_intr;
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static pic_setup_intr_t aplic_setup_intr;
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static pic_post_ithread_t aplic_post_ithread;
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static pic_pre_ithread_t aplic_pre_ithread;
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static pic_bind_intr_t aplic_bind_intr;
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struct aplic_irqsrc {
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struct intr_irqsrc isrc;
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u_int irq;
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};
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struct aplic_softc {
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device_t dev;
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struct resource *mem_res;
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struct resource *irq_res;
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void *ih;
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struct aplic_irqsrc isrcs[APLIC_MAX_IRQS + 1];
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unsigned int hart_indices[MAXCPU];
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int ndev;
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};
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#define APLIC_DOMAIN_CFG_IE (1UL << 8) /* Enable domain IRQs */
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#define APLIC_DOMAIN_CFG_DM (1UL << 2) /* IRQ delivery mode */
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#define APLIC_DOMAIN_CFG_BE (1UL << 0) /* Endianess */
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#define APLIC_MODE_DIRECT 0 /* Direct delivery mode */
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#define APLIC_MODE_MSI 1 /* MSI delivery mode */
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#define APLIC_SRC_CFG_DLGT (1UL << 10) /* Source delegation */
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#define APLIC_SRC_CFG_SM_SHIFT 0
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#define APLIC_SRC_CFG_SM_MASK (0x7UL << APLIC_SRC_CFG_SM_SHIFT)
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#define APLIC_SRC_CFG_SM_INACTIVE 0 /* APLIC inactive in domain */
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#define APLIC_SRC_CFG_SM_DETACHED 1 /* Detached from source wire */
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#define APLIC_SRC_CFG_SM_EDGE_RSE 4 /* Asserted on rising edge */
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#define APLIC_SRC_CFG_SM_EDGE_FLL 5 /* Asserted on falling edge */
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#define APLIC_SRC_CFG_SM_LVL_HI 6 /* Asserted when high */
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#define APLIC_SRC_CFG_SM_LVL_LO 7 /* Asserted when low */
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/* Register offsets in APLIC configuration space */
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#define APLIC_DOMAIN_CFG 0x0000
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#define APLIC_SRC_CFG(_idx) (0x0004 + (((_idx) - 1) * 4))
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#define APLIC_TARGET(_idx) (0x3004 + (((_idx) - 1) * 4))
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#define APLIC_MMSIADDRCFG 0x1BC0
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#define APLIC_MMSIADDRCFGH 0x1BC4
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#define APLIC_SMSIADDRCFG 0x1BC8
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#define APLIC_SMSIADDRCFGH 0x1BCC
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#define APLIC_SETIPNUM 0x1CDC
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#define APLIC_CLRIPNUM 0x1DDC
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#define APLIC_SETIENUM 0x1EDC
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#define APLIC_CLRIENUM 0x1FDC
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#define APLIC_SETIPNUM_LE 0x2000
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#define APLIC_SETIPNUM_BE 0x2004
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#define APLIC_GENMSI 0x3000
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#define APLIC_IDC_BASE 0x4000
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#define APLIC_SETIE_BASE 0x1E00
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#define APLIC_CLRIE_BASE 0x1F00
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/* Interrupt delivery control structure */
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#define APLIC_IDC_IDELIVERY_OFFS 0x0000
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#define APLIC_IDC_IFORCE_OFFS 0x0004
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#define APLIC_IDC_ITHRESHOLD_OFFS 0x0008
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#define APLIC_IDC_TOPI_OFFS 0x0018
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#define APLIC_IDC_CLAIMI_OFFS 0x001C
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#define APLIC_IDC_SZ 0x20
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#define APLIC_IDC_IDELIVERY_DISABLE 0
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#define APLIC_IDC_IDELIVERY_ENABLE 1
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#define APLIC_IDC_ITHRESHOLD_DISABLE 0
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#define APLIC_IDC_CLAIMI_PRIO_MASK 0xff
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#define APLIC_IDC_CLAIMI_IRQ_SHIFT 16
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#define APLIC_IDC_CLAIMI_IRQ_MASK 0x3ff
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#define APLIC_IDC_CLAIMI_IRQ(_claimi) \
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(((_claimi) >> APLIC_IDC_CLAIMI_IRQ_SHIFT) \
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& APLIC_IDC_CLAIMI_IRQ_MASK)
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#define APLIC_IDC_CLAIMI_PRIO(_claimi) ((_claimi) & APLIC_IDC_CLAIMI_PRIO_MASK)
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#define APLIC_IDC_REG(_sc, _cpu, _field) \
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(APLIC_IDC_BASE + APLIC_IDC_##_field##_OFFS + \
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((_sc->hart_indices[_cpu]) * APLIC_IDC_SZ))
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#define APLIC_IDC_IDELIVERY(_sc, _cpu) \
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APLIC_IDC_REG(_sc, _cpu, IDELIVERY)
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#define APLIC_IDC_IFORCE(_sc, _cpu) \
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APLIC_IDC_REG(_sc, _cpu, IFORCE)
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#define APLIC_IDC_ITHRESHOLD(_sc, _cpu) \
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APLIC_IDC_REG(_sc, _cpu, ITHRESHOLD)
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#define APLIC_IDC_TOPI(_sc, _cpu) \
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APLIC_IDC_REG(_sc, _cpu, TOPI)
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#define APLIC_IDC_CLAIMI(_sc, _cpu) \
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APLIC_IDC_REG(_sc, _cpu, CLAIMI)
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#define APLIC_MK_IRQ_TARGET(_sc, _cpu, _prio) \
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(_sc->hart_indices[_cpu] << 18 | ((_prio) & 0xff))
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#define aplic_read(sc, reg) bus_read_4(sc->mem_res, (reg))
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#define aplic_write(sc, reg, val) bus_write_4(sc->mem_res, (reg), (val))
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static u_int aplic_irq_cpu;
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static inline int
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riscv_cpu_to_hartid(int cpu)
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{
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return pcpu_find(cpu)->pc_hart;
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}
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static inline int
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riscv_hartid_to_cpu(int hartid)
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{
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int cpu;
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CPU_FOREACH(cpu) {
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if (riscv_cpu_to_hartid(cpu) == hartid)
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return cpu;
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}
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return (-1);
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}
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static int
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fdt_get_hartid(device_t dev, phandle_t aplic)
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{
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int hartid;
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/* Check the interrupt controller layout. */
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if (OF_searchencprop(aplic, "#interrupt-cells", &hartid,
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sizeof(hartid)) == -1) {
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device_printf(dev,
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"Could not find #interrupt-cells for phandle %u\n", aplic);
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return (-1);
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}
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/*
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* The parent of the interrupt-controller is the CPU we are
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* interested in, so search for its hart ID.
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*/
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if (OF_searchencprop(OF_parent(aplic), "reg", (pcell_t *)&hartid,
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sizeof(hartid)) == -1) {
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device_printf(dev, "Could not find hartid\n");
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return (-1);
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}
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return (hartid);
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}
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static inline void
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aplic_irq_dispatch(struct aplic_softc *sc, u_int irq, u_int prio,
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struct trapframe *tf)
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{
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struct aplic_irqsrc *src;
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src = &sc->isrcs[irq];
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if (intr_isrc_dispatch(&src->isrc, tf) != 0)
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if (bootverbose)
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device_printf(sc->dev, "Stray irq %u detected\n", irq);
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}
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static int
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aplic_intr(void *arg)
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{
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struct aplic_softc *sc;
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struct trapframe *tf;
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u_int claimi, prio, irq;
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int cpu;
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sc = arg;
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cpu = PCPU_GET(cpuid);
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/* Claim any pending interrupt. */
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claimi = aplic_read(sc, APLIC_IDC_CLAIMI(sc, cpu));
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prio = APLIC_IDC_CLAIMI_PRIO(claimi);
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irq = APLIC_IDC_CLAIMI_IRQ(claimi);
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KASSERT((irq != 0), ("Invalid IRQ 0"));
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tf = curthread->td_intr_frame;
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aplic_irq_dispatch(sc, irq, prio, tf);
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return (FILTER_HANDLED);
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}
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static void
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aplic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct aplic_softc *sc;
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struct aplic_irqsrc *src;
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sc = device_get_softc(dev);
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src = (struct aplic_irqsrc *)isrc;
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/* Disable the interrupt source */
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aplic_write(sc, APLIC_CLRIENUM, src->irq);
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}
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static void
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aplic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct aplic_softc *sc;
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struct aplic_irqsrc *src;
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sc = device_get_softc(dev);
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src = (struct aplic_irqsrc *)isrc;
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/* Enable the interrupt source */
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aplic_write(sc, APLIC_SETIENUM, src->irq);
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}
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static int
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aplic_map_intr(device_t dev, struct intr_map_data *data,
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struct intr_irqsrc **isrcp)
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{
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struct intr_map_data_fdt *daf;
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struct aplic_softc *sc;
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sc = device_get_softc(dev);
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if (data->type != INTR_MAP_DATA_FDT)
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return (ENOTSUP);
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daf = (struct intr_map_data_fdt *)data;
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if (daf->ncells != 2 || daf->cells[0] > sc->ndev) {
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device_printf(dev, "Invalid cell data\n");
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return (EINVAL);
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}
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*isrcp = &sc->isrcs[daf->cells[0]].isrc;
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return (0);
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}
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static int
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aplic_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "riscv,aplic"))
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return (ENXIO);
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device_set_desc(dev, "Advanced Platform-Level Interrupt Controller");
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return (BUS_PROBE_DEFAULT);
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}
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/*
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* Setup APLIC in direct mode.
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*/
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static int
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aplic_setup_direct_mode(device_t dev)
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{
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struct aplic_irqsrc *isrcs;
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struct aplic_softc *sc;
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struct intr_pic *pic;
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const char *name;
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phandle_t node, xref, iparent;
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pcell_t *cells, cell;
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int error = ENXIO;
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u_int irq;
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int cpu, hartid, rid, i, nintr, idc;
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sc = device_get_softc(dev);
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node = ofw_bus_get_node(dev);
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sc->dev = dev;
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if ((OF_getencprop(node, "riscv,num-sources", &sc->ndev,
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sizeof(sc->ndev))) < 0) {
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device_printf(dev, "Error: could not get number of devices\n");
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return (error);
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}
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if (sc->ndev > APLIC_MAX_IRQS) {
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device_printf(dev, "Error: invalid ndev (%d)\n", sc->ndev);
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return (error);
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}
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/* Request memory resources */
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev,
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"Error: could not allocate memory resources\n");
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return (error);
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}
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/* Set APLIC in direct mode and enable all interrupts */
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aplic_write(sc, APLIC_DOMAIN_CFG,
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APLIC_MODE_DIRECT | APLIC_DOMAIN_CFG_IE);
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/* Register the interrupt sources */
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isrcs = sc->isrcs;
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name = device_get_nameunit(sc->dev);
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for (irq = 1; irq <= sc->ndev; irq++) {
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isrcs[irq].irq = irq;
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error = intr_isrc_register(&isrcs[irq].isrc, sc->dev,
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0, "%s,%u", name, irq);
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if (error != 0)
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goto fail;
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aplic_write(sc, APLIC_SRC_CFG(irq),
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APLIC_SRC_CFG_SM_DETACHED);
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}
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nintr = OF_getencprop_alloc_multi(node, "interrupts-extended",
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sizeof(uint32_t), (void **)&cells);
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if (nintr <= 0) {
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device_printf(dev, "Could not read interrupts-extended\n");
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goto fail;
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}
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/* interrupts-extended is a list of phandles and interrupt types. */
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for (i = 0, idc = 0; i < nintr; i += 2, idc++) {
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/* Skip M-mode external interrupts */
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if (cells[i + 1] != IRQ_EXTERNAL_SUPERVISOR)
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continue;
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/* Get the hart ID from the CLIC's phandle. */
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hartid = fdt_get_hartid(dev, OF_node_from_xref(cells[i]));
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if (hartid < 0) {
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OF_prop_free(cells);
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goto fail;
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}
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/* Get the corresponding cpuid. */
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cpu = riscv_hartid_to_cpu(hartid);
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if (cpu < 0) {
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device_printf(dev, "Invalid cpu for hart %d\n", hartid);
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OF_prop_free(cells);
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goto fail;
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}
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sc->hart_indices[cpu] = idc;
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}
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OF_prop_free(cells);
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/* Turn off the interrupt delivery for all CPUs within or out domain */
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CPU_FOREACH(cpu) {
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aplic_write(sc, APLIC_IDC_IDELIVERY(sc, cpu),
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APLIC_IDC_IDELIVERY_DISABLE);
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aplic_write(sc, APLIC_IDC_ITHRESHOLD(sc, cpu),
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APLIC_IDC_ITHRESHOLD_DISABLE);
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}
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iparent = OF_xref_from_node(ofw_bus_get_node(intr_irq_root_dev));
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cell = IRQ_EXTERNAL_SUPERVISOR;
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irq = ofw_bus_map_intr(dev, iparent, 1, &cell);
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error = bus_set_resource(dev, SYS_RES_IRQ, 0, irq, 1);
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if (error != 0) {
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device_printf(dev, "Unable to register IRQ resource\n");
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return (ENXIO);
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}
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rid = 0;
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sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE);
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if (sc->irq_res == NULL) {
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device_printf(dev,
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"Error: could not allocate IRQ resources\n");
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return (ENXIO);
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}
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||||
|
||||
xref = OF_xref_from_node(node);
|
||||
pic = intr_pic_register(sc->dev, xref);
|
||||
if (pic == NULL) {
|
||||
error = ENXIO;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_CLK,
|
||||
aplic_intr, NULL, sc, &sc->ih);
|
||||
if (error != 0) {
|
||||
device_printf(dev, "Unable to setup IRQ resource\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
fail:
|
||||
return (error);
|
||||
}
|
||||
|
||||
static int
|
||||
aplic_attach(device_t dev)
|
||||
{
|
||||
int rc;
|
||||
|
||||
/* APLIC with IMSIC on hart is not supported */
|
||||
if (ofw_bus_has_prop(dev, "msi-parent")) {
|
||||
device_printf(dev, "APLIC with IMSIC is unsupported\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
rc = aplic_setup_direct_mode(dev);
|
||||
|
||||
return (rc);
|
||||
}
|
||||
|
||||
static void
|
||||
aplic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
aplic_disable_intr(dev, isrc);
|
||||
}
|
||||
|
||||
static void
|
||||
aplic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
aplic_enable_intr(dev, isrc);
|
||||
}
|
||||
|
||||
static int
|
||||
aplic_setup_intr(device_t dev, struct intr_irqsrc *isrc, struct resource *res,
|
||||
struct intr_map_data *data)
|
||||
{
|
||||
struct aplic_irqsrc *src;
|
||||
struct aplic_softc *sc;
|
||||
|
||||
CPU_ZERO(&isrc->isrc_cpu);
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
src = (struct aplic_irqsrc *)isrc;
|
||||
|
||||
aplic_write(sc, APLIC_SRC_CFG(src->irq), APLIC_SRC_CFG_SM_EDGE_RSE);
|
||||
|
||||
/*
|
||||
* In uniprocessor system, bind_intr will not be called.
|
||||
* So bind the interrupt on this CPU. If secondary CPUs
|
||||
* are present, then bind_intr will be called again and
|
||||
* interrupts will rebind to those CPUs.
|
||||
*/
|
||||
aplic_bind_intr(dev, isrc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
aplic_bind_intr(device_t dev, struct intr_irqsrc *isrc)
|
||||
{
|
||||
struct aplic_softc *sc;
|
||||
struct aplic_irqsrc *src;
|
||||
uint32_t cpu, hartid;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
src = (struct aplic_irqsrc *)isrc;
|
||||
|
||||
/* Disable the interrupt source */
|
||||
aplic_write(sc, APLIC_CLRIENUM, src->irq);
|
||||
|
||||
if (CPU_EMPTY(&isrc->isrc_cpu)) {
|
||||
cpu = aplic_irq_cpu = intr_irq_next_cpu(aplic_irq_cpu,
|
||||
&all_cpus);
|
||||
CPU_SETOF(cpu, &isrc->isrc_cpu);
|
||||
} else {
|
||||
cpu = CPU_FFS(&isrc->isrc_cpu) - 1;
|
||||
}
|
||||
|
||||
hartid = riscv_cpu_to_hartid(cpu);
|
||||
|
||||
if (bootverbose)
|
||||
device_printf(dev, "Bind irq %d to cpu%d (hart %d)\n", src->irq,
|
||||
cpu, hartid);
|
||||
|
||||
aplic_write(sc, APLIC_TARGET(src->irq),
|
||||
APLIC_MK_IRQ_TARGET(sc, cpu, APLIC_INTR_DEF_PRIO));
|
||||
aplic_write(sc, APLIC_IDC_IDELIVERY(sc, cpu),
|
||||
APLIC_IDC_IDELIVERY_ENABLE);
|
||||
aplic_enable_intr(dev, isrc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static device_method_t aplic_methods[] = {
|
||||
DEVMETHOD(device_probe, aplic_probe),
|
||||
DEVMETHOD(device_attach, aplic_attach),
|
||||
|
||||
DEVMETHOD(pic_disable_intr, aplic_disable_intr),
|
||||
DEVMETHOD(pic_enable_intr, aplic_enable_intr),
|
||||
DEVMETHOD(pic_map_intr, aplic_map_intr),
|
||||
DEVMETHOD(pic_pre_ithread, aplic_pre_ithread),
|
||||
DEVMETHOD(pic_post_ithread, aplic_post_ithread),
|
||||
DEVMETHOD(pic_post_filter, aplic_post_ithread),
|
||||
DEVMETHOD(pic_setup_intr, aplic_setup_intr),
|
||||
DEVMETHOD(pic_bind_intr, aplic_bind_intr),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
DEFINE_CLASS_0(aplic, aplic_driver, aplic_methods, sizeof(struct aplic_softc));
|
||||
|
||||
EARLY_DRIVER_MODULE(aplic, simplebus, aplic_driver, 0, 0,
|
||||
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
|
||||
Loading…
Reference in a new issue