diff --git a/sys/powerpc/aim/mp_cpudep.c b/sys/powerpc/aim/mp_cpudep.c
index 50f64d79441a..8741463d02b9 100644
--- a/sys/powerpc/aim/mp_cpudep.c
+++ b/sys/powerpc/aim/mp_cpudep.c
@@ -75,9 +75,21 @@ cpudep_ap_bootstrap(void)
 }
 
 static register_t
-mpc745x_l2_enable(register_t l2cr_config)
+mpc74xx_l2_enable(register_t l2cr_config)
 {
-	register_t ccr;
+	register_t ccr, bit;
+	uint16_t	vers;
+
+	vers = mfpvr() >> 16;
+	switch (vers) {
+	case MPC7400:
+	case MPC7410:
+		bit = L2CR_L2IP;
+		break;
+	default:
+		bit = L2CR_L2I;
+		break;
+	}
 
 	ccr = mfspr(SPR_L2CR);
 	if (ccr & L2CR_L2E)
@@ -88,7 +100,7 @@ mpc745x_l2_enable(register_t l2cr_config)
 	mtspr(SPR_L2CR, ccr | L2CR_L2I);
 	do {
 		ccr = mfspr(SPR_L2CR);
-	} while (ccr & L2CR_L2I);
+	} while (ccr & bit);
 	powerpc_sync();
 	mtspr(SPR_L2CR, l2cr_config);
 	powerpc_sync();
@@ -129,7 +141,7 @@ mpc745x_l3_enable(register_t l3cr_config)
 }
 
 static register_t
-mpc745x_l1d_enable(void)
+mpc74xx_l1d_enable(void)
 {
 	register_t hid;
 
@@ -147,7 +159,7 @@ mpc745x_l1d_enable(void)
 }
 
 static register_t
-mpc745x_l1i_enable(void)
+mpc74xx_l1i_enable(void)
 {
 	register_t hid;
 
@@ -267,9 +279,9 @@ cpudep_ap_setup()
 		mtspr(SPR_HID0, bsp_state[0]); isync();
 		mtspr(SPR_HID1, bsp_state[1]); isync();
 
-		reg = mpc745x_l2_enable(bsp_state[2]);
-		reg = mpc745x_l1d_enable();
-		reg = mpc745x_l1i_enable();
+		reg = mpc74xx_l2_enable(bsp_state[2]);
+		reg = mpc74xx_l1d_enable();
+		reg = mpc74xx_l1i_enable();
 
 		break;
 	default:
diff --git a/sys/powerpc/aim/platform_chrp.c b/sys/powerpc/aim/platform_chrp.c
index 2258c126e720..5a528be93001 100644
--- a/sys/powerpc/aim/platform_chrp.c
+++ b/sys/powerpc/aim/platform_chrp.c
@@ -228,8 +228,26 @@ chrp_smp_start_cpu(platform_t plat, struct pcpu *pc)
 
 	cpu = pc->pc_hwref;
 	res = OF_getprop(cpu, "soft-reset", &reset, sizeof(reset));
-	if (res < 0)
-		return (ENXIO);
+	if (res < 0) {
+		reset = 0x58;
+
+		switch (pc->pc_cpuid) {
+		case 0:
+			reset += 0x03;
+			break;
+		case 1:
+			reset += 0x04;
+			break;
+		case 2:
+			reset += 0x0f;
+			break;
+		case 4:
+			reset += 0x10;
+			break;
+		default:
+			return (ENXIO);
+		}
+	}
 
 	ap_pcpu = pc;
 
@@ -239,10 +257,12 @@ chrp_smp_start_cpu(platform_t plat, struct pcpu *pc)
 	rstvec = rstvec_virtbase + reset;
 
 	*rstvec = 4;
+	powerpc_sync();
 	(void)(*rstvec);
 	powerpc_sync();
 	DELAY(1);
 	*rstvec = 0;
+	powerpc_sync();
 	(void)(*rstvec);
 	powerpc_sync();