diff --git a/sys/gnu/dts/arm/meson.dtsi b/sys/gnu/dts/arm/meson.dtsi
index b67ede515bcd..5260cb02c1b1 100644
--- a/sys/gnu/dts/arm/meson.dtsi
+++ b/sys/gnu/dts/arm/meson.dtsi
@@ -67,7 +67,7 @@
 
 	timer@c1109940 {
 		compatible = "amlogic,meson6-timer";
-		reg = <0xc1109940 0x14>;
+		reg = <0xc1109940 0x18>;
 		interrupts = <0 10 1>;
 	};
 
@@ -80,36 +80,37 @@
 		wdt: watchdog@c1109900 {
 			compatible = "amlogic,meson6-wdt";
 			reg = <0xc1109900 0x8>;
+			interrupts = <0 0 1>;
 		};
 
 		uart_AO: serial@c81004c0 {
 			compatible = "amlogic,meson-uart";
-			reg = <0xc81004c0 0x14>;
+			reg = <0xc81004c0 0x18>;
 			interrupts = <0 90 1>;
 			clocks = <&clk81>;
 			status = "disabled";
 		};
 
-		uart_A: serial@c81084c0 {
+		uart_A: serial@c11084c0 {
 			compatible = "amlogic,meson-uart";
-			reg = <0xc81084c0 0x14>;
-			interrupts = <0 90 1>;
+			reg = <0xc11084c0 0x18>;
+			interrupts = <0 26 1>;
 			clocks = <&clk81>;
 			status = "disabled";
 		};
 
-		uart_B: serial@c81084dc {
+		uart_B: serial@c11084dc {
 			compatible = "amlogic,meson-uart";
-			reg = <0xc81084dc 0x14>;
-			interrupts = <0 90 1>;
+			reg = <0xc11084dc 0x18>;
+			interrupts = <0 75 1>;
 			clocks = <&clk81>;
 			status = "disabled";
 		};
 
-		uart_C: serial@c8108700 {
+		uart_C: serial@c1108700 {
 			compatible = "amlogic,meson-uart";
-			reg = <0xc8108700 0x14>;
-			interrupts = <0 90 1>;
+			reg = <0xc1108700 0x18>;
+			interrupts = <0 93 1>;
 			clocks = <&clk81>;
 			status = "disabled";
 		};
diff --git a/sys/gnu/dts/arm/meson6.dtsi b/sys/gnu/dts/arm/meson6.dtsi
index 8b33be15af94..7bfbb35f9c26 100644
--- a/sys/gnu/dts/arm/meson6.dtsi
+++ b/sys/gnu/dts/arm/meson6.dtsi
@@ -78,3 +78,7 @@
 		clock-frequency = <200000000>;
 	};
 }; /* end of / */
+
+&L2 {
+	interrupts = <0 61 1>;
+};
diff --git a/sys/gnu/dts/arm/meson8.dtsi b/sys/gnu/dts/arm/meson8.dtsi
index 1f442a7fe03b..819a97938147 100644
--- a/sys/gnu/dts/arm/meson8.dtsi
+++ b/sys/gnu/dts/arm/meson8.dtsi
@@ -90,3 +90,7 @@
 		clock-frequency = <141666666>;
 	};
 }; /* end of / */
+
+&L2 {
+	interrupts = <0 143 1>;
+};