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add driver for CMedia CMI8338/CMI8738 sound chips
Submitted by: Orion Hodson <O.Hodson@cs.ucl.ac.uk>
This commit is contained in:
Cameron Grant
parent
51ab799576
commit
ebbb717721
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=72016
4 changed files with 1092 additions and 1 deletions
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@ -465,6 +465,7 @@ dev/sound/midi/midibuf.c optional midi
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dev/sound/midi/midisynth.c optional midi
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dev/sound/midi/sequencer.c optional seq midi
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#dev/sound/pci/aureal.c optional pcm pci
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dev/sound/pci/cmi.c optional pcm pci
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dev/sound/pci/csa.c optional csa pci
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dev/sound/pci/csa.c optional pcm pci
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dev/sound/pci/csamidi.c optional midi csa
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887
sys/dev/sound/pci/cmi.c
Normal file
887
sys/dev/sound/pci/cmi.c
Normal file
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@ -0,0 +1,887 @@
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/*
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* Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
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* SUCH DAMAGE.
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*
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* This driver exists largely as a result of other people's efforts.
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* Much of register handling is based on NetBSD CMI8x38 audio driver
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* by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien
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* <cltien@cmedia.com.tw> clarified points regarding the DMA related
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* registers and the 8738 mixer devices. His Linux was driver a also
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* useful reference point.
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*
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* TODO: MIDI / suspend / resume
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*
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* SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>.
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*
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* $FreeBSD$
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*/
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#include <dev/sound/pcm/sound.h>
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#include <dev/sound/pci/cmireg.h>
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#include <dev/sound/isa/sb.h>
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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#include "mixer_if.h"
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/* Supported chip ID's */
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#define CMI8338A_PCI_ID 0x010013f6
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#define CMI8338B_PCI_ID 0x010113f6
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#define CMI8738_PCI_ID 0x011113f6
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#define CMI8738B_PCI_ID 0x011213f6
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/* Buffer size max is 64k for permitted DMA boundaries */
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#define CMI_BUFFER_SIZE 16384
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/* Interrupts per length of buffer */
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#define CMI_INTR_PER_BUFFER 2
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/* Clarify meaning of named defines in cmireg.h */
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#define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES
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#define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES
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#define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES
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#define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES
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/* Our indication of custom mixer control */
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#define CMPCI_NON_SB16_CONTROL 0xff
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/* Debugging macro's */
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#ifndef DEB
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#define DEB(x) /* x */
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#endif /* DEB */
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#ifndef DEBMIX
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#define DEBMIX(x) /* x */
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#endif /* DEBMIX */
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/* ------------------------------------------------------------------------- */
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/* Structures */
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struct cmi_info;
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struct cmi_chinfo {
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struct cmi_info *parent;
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pcm_channel *channel;
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snd_dbuf *buffer;
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int dir;
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int bps; /* bytes per sample */
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u_int32_t fmt, spd, phys_buf;
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u_int32_t dma_configured;
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};
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struct cmi_info {
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device_t dev;
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u_int32_t type, rev;
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bus_space_tag_t st;
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bus_space_handle_t sh;
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bus_dma_tag_t parent_dmat;
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struct resource *reg, *irq;
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int regid, irqid;
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void *ih;
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struct cmi_chinfo pch, rch;
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};
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/* Channel caps */
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static u_int32_t cmi_fmt[] = {
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AFMT_U8,
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AFMT_STEREO | AFMT_U8,
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AFMT_S16_LE,
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AFMT_STEREO | AFMT_S16_LE,
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0
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};
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static pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0};
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/* ------------------------------------------------------------------------- */
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/* Register Utilities */
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static u_int32_t
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cmi_rd(struct cmi_info *cmi, int regno, int size)
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{
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switch (size) {
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case 1:
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return bus_space_read_1(cmi->st, cmi->sh, regno);
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case 2:
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return bus_space_read_2(cmi->st, cmi->sh, regno);
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case 4:
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return bus_space_read_4(cmi->st, cmi->sh, regno);
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default:
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DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size));
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return 0xFFFFFFFF;
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}
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}
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static void
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cmi_wr(struct cmi_info *cmi, int regno, u_int32_t data, int size)
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{
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switch (size) {
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case 1:
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bus_space_write_1(cmi->st, cmi->sh, regno, data);
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break;
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case 2:
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bus_space_write_2(cmi->st, cmi->sh, regno, data);
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break;
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case 4:
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bus_space_write_4(cmi->st, cmi->sh, regno, data);
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break;
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}
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DELAY(10);
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}
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static void
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cmi_partial_wr4(struct cmi_info *cmi,
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int reg, int shift, u_int32_t mask, u_int32_t val)
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{
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u_int32_t r;
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r = cmi_rd(cmi, reg, 4);
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r &= ~(mask << shift);
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r |= val << shift;
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cmi_wr(cmi, reg, r, 4);
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}
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static void
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cmi_clr4(struct cmi_info *cmi, int reg, u_int32_t mask)
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{
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u_int32_t r;
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r = cmi_rd(cmi, reg, 4);
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r &= ~mask;
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cmi_wr(cmi, reg, r, 4);
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}
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static void
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cmi_set4(struct cmi_info *cmi, int reg, u_int32_t mask)
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{
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u_int32_t r;
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r = cmi_rd(cmi, reg, 4);
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r |= mask;
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cmi_wr(cmi, reg, r, 4);
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}
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/* ------------------------------------------------------------------------- */
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/* Rate Mapping */
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static int cmi_rates[] = {5512, 8000, 11025, 16000,
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22050, 32000, 44100, 48000};
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#define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0]))
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/* cmpci_rate_to_regvalue returns sampling freq selector for FCR1
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* register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */
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static u_int32_t
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cmpci_rate_to_regvalue(int rate)
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{
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int i, r;
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for(i = 0; i < NUM_CMI_RATES - 1; i++) {
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if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) {
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break;
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}
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}
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DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i]));
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r = ((i >> 1) | (i << 2)) & 0x07;
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return r;
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}
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static int
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cmpci_regvalue_to_rate(u_int32_t r)
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{
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int i;
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i = ((r << 1) | (r >> 2)) & 0x07;
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DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i));
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return cmi_rates[i];
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}
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/* ------------------------------------------------------------------------- */
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/* ADC/DAC control */
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static void
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cmi_dac_start(struct cmi_info *cmi, struct cmi_chinfo *ch)
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{
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if (ch->dma_configured == 0) {
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u_int32_t s, i, sz;
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ch->phys_buf = vtophys(sndbuf_getbuf(ch->buffer));
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sz = (u_int32_t)sndbuf_getsize(ch->buffer);
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s = (sz + 1) / ch->bps - 1;
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i = (sz + 1) / (ch->bps * CMI_INTR_PER_BUFFER) - 1;
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cmi_wr(cmi, CMPCI_REG_DMA0_BASE, ch->phys_buf, 4);
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cmi_wr(cmi, CMPCI_REG_DMA0_MAX_SAMPLES, s, 2);
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cmi_wr(cmi, CMPCI_REG_DMA0_INTR_SAMPLES, i, 2);
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ch->dma_configured = 1;
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DEB(printf("cmi_dac_start: dma prog\n"));
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}
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cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR);
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cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_PAUSE);
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cmi_set4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
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cmi_set4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
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}
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static void
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cmi_dac_stop(struct cmi_info *cmi)
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{
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cmi_clr4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
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cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
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}
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static void
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cmi_dac_reset(struct cmi_info *cmi, struct cmi_chinfo *ch)
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{
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cmi_dac_stop(cmi);
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cmi_set4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
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cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
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ch->dma_configured = 0;
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DEB(printf("cmi_dac_reset\n"));
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}
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static void
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cmi_adc_start(struct cmi_info *cmi, struct cmi_chinfo *ch)
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{
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if (ch->dma_configured == 0) {
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u_int32_t s, i, sz;
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ch->phys_buf = vtophys(sndbuf_getbuf(ch->buffer));
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sz = (u_int32_t)sndbuf_getsize(ch->buffer);
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s = (sz + 1) / ch->bps - 1;
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i = (sz + 1) / (ch->bps * CMI_INTR_PER_BUFFER) - 1;
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cmi_wr(cmi, CMPCI_REG_DMA1_BASE, ch->phys_buf, 4);
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cmi_wr(cmi, CMPCI_REG_DMA1_MAX_SAMPLES, s, 2);
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cmi_wr(cmi, CMPCI_REG_DMA1_INTR_SAMPLES, i, 2);
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ch->dma_configured = 1;
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DEB(printf("cmi_adc_start: dma prog\n"));
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}
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cmi_set4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR);
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cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_PAUSE);
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cmi_set4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
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cmi_set4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
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}
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static void
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cmi_adc_stop(struct cmi_info *cmi)
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{
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cmi_clr4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
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cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
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}
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static void
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cmi_adc_reset(struct cmi_info *cmi, struct cmi_chinfo *ch)
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{
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cmi_adc_stop(cmi);
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cmi_set4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
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cmi_clr4(cmi, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
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ch->dma_configured = 0;
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DEB(printf("cmi_adc_reset\n"));
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}
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static void
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cmi_spdif_speed(struct cmi_info *cmi, int speed) {
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u_int32_t fcr1, lcr, mcr;
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mcr = 0;
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if (speed >= 44100) {
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fcr1 = CMPCI_REG_SPDIF0_ENABLE;
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lcr = CMPCI_REG_XSPDIF_ENABLE;
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mcr = (speed == 48000) ?
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CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0;
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} else {
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fcr1 = mcr = lcr = 0;
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}
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cmi_partial_wr4(cmi, CMPCI_REG_FUNC_1, 0,
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CMPCI_REG_SPDIF0_ENABLE, fcr1);
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cmi_partial_wr4(cmi, CMPCI_REG_MISC, 0,
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CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr);
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cmi_partial_wr4(cmi, CMPCI_REG_LEGACY_CTRL, 0,
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CMPCI_REG_XSPDIF_ENABLE, lcr);
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}
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/* ------------------------------------------------------------------------- */
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/* Channel Interface implementation */
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static void *
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cmichan_init(kobj_t obj, void *devinfo, snd_dbuf *b, pcm_channel *c, int dir)
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{
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struct cmi_info *cmi = devinfo;
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struct cmi_chinfo *ch = (dir == PCMDIR_PLAY) ? &cmi->pch : &cmi->rch;
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ch->parent = cmi;
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ch->channel = c;
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ch->bps = 1;
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ch->fmt = AFMT_U8;
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ch->spd = DSP_DEFAULT_SPEED;
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ch->dma_configured = 0;
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ch->buffer = b;
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if (sndbuf_alloc(ch->buffer, cmi->parent_dmat, CMI_BUFFER_SIZE) != 0) {
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DEB(printf("cmichan_init failed\n"));
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return NULL;
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}
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ch->dir = dir;
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if (dir == PCMDIR_PLAY) {
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cmi_clr4(ch->parent, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR);
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} else {
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cmi_set4(ch->parent, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR);
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}
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return ch;
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}
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static int
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cmichan_setformat(kobj_t obj, void *data, u_int32_t format)
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{
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struct cmi_chinfo *ch = data;
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u_int32_t f;
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if (format & AFMT_S16_LE) {
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f = CMPCI_REG_FORMAT_16BIT;
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ch->bps = 2;
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} else {
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f = CMPCI_REG_FORMAT_8BIT;
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ch->bps = 1;
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}
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if (format & AFMT_STEREO) {
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f |= CMPCI_REG_FORMAT_STEREO;
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ch->bps *= 2;
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} else {
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f |= CMPCI_REG_FORMAT_MONO;
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}
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if (ch->dir == PCMDIR_PLAY) {
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cmi_partial_wr4(ch->parent,
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CMPCI_REG_CHANNEL_FORMAT,
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CMPCI_REG_CH0_FORMAT_SHIFT,
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CMPCI_REG_CH0_FORMAT_MASK,
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f);
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} else {
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cmi_partial_wr4(ch->parent,
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CMPCI_REG_CHANNEL_FORMAT,
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CMPCI_REG_CH1_FORMAT_SHIFT,
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CMPCI_REG_CH1_FORMAT_MASK,
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f);
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}
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ch->fmt = format;
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ch->dma_configured = 0;
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return 0;
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}
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static int
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cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed)
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{
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struct cmi_chinfo *ch = data;
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u_int32_t r, rsp;
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r = cmpci_rate_to_regvalue(speed);
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if (ch->dir == PCMDIR_PLAY) {
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if (speed < 44100) /* disable if req before rate change */
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cmi_spdif_speed(ch->parent, speed);
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cmi_partial_wr4(ch->parent,
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CMPCI_REG_FUNC_1,
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CMPCI_REG_DAC_FS_SHIFT,
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CMPCI_REG_DAC_FS_MASK,
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r);
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if (speed >= 44100) /* enable if req after rate change */
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cmi_spdif_speed(ch->parent, speed);
|
||||
rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
|
||||
rsp >>= CMPCI_REG_DAC_FS_SHIFT;
|
||||
rsp &= CMPCI_REG_DAC_FS_MASK;
|
||||
} else {
|
||||
cmi_partial_wr4(ch->parent,
|
||||
CMPCI_REG_FUNC_1,
|
||||
CMPCI_REG_ADC_FS_SHIFT,
|
||||
CMPCI_REG_ADC_FS_MASK,
|
||||
r);
|
||||
rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
|
||||
rsp >>= CMPCI_REG_ADC_FS_SHIFT;
|
||||
rsp &= CMPCI_REG_ADC_FS_MASK;
|
||||
}
|
||||
ch->spd = cmpci_regvalue_to_rate(r);
|
||||
|
||||
DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n",
|
||||
(ch->dir == PCMDIR_PLAY) ? "play" : "rec",
|
||||
speed, ch->spd, cmpci_regvalue_to_rate(rsp)));
|
||||
|
||||
return ch->spd;
|
||||
}
|
||||
|
||||
static int
|
||||
cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
|
||||
{
|
||||
struct cmi_chinfo *ch = data;
|
||||
|
||||
/* user has requested interrupts every blocksize bytes */
|
||||
if (blocksize > CMI_BUFFER_SIZE / CMI_INTR_PER_BUFFER) {
|
||||
blocksize = CMI_BUFFER_SIZE / CMI_INTR_PER_BUFFER;
|
||||
}
|
||||
sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize);
|
||||
|
||||
ch->dma_configured = 0;
|
||||
return sndbuf_getsize(ch->buffer);
|
||||
}
|
||||
|
||||
static int
|
||||
cmichan_trigger(kobj_t obj, void *data, int go)
|
||||
{
|
||||
struct cmi_chinfo *ch = data;
|
||||
struct cmi_info *cmi = ch->parent;
|
||||
|
||||
if (ch->dir == PCMDIR_PLAY) {
|
||||
switch(go) {
|
||||
case PCMTRIG_START:
|
||||
cmi_dac_start(cmi, ch);
|
||||
break;
|
||||
case PCMTRIG_ABORT:
|
||||
cmi_dac_reset(cmi, ch);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch(go) {
|
||||
case PCMTRIG_START:
|
||||
cmi_adc_start(cmi, ch);
|
||||
break;
|
||||
case PCMTRIG_ABORT:
|
||||
cmi_adc_reset(cmi, ch);
|
||||
break;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
cmichan_getptr(kobj_t obj, void *data)
|
||||
{
|
||||
struct cmi_chinfo *ch = data;
|
||||
struct cmi_info *cmi = ch->parent;
|
||||
u_int32_t physptr, bufptr, sz;
|
||||
|
||||
if (ch->dir == PCMDIR_PLAY) {
|
||||
physptr = cmi_rd(cmi, CMPCI_REG_DMA0_BASE, 4);
|
||||
} else {
|
||||
physptr = cmi_rd(cmi, CMPCI_REG_DMA1_BASE, 4);
|
||||
}
|
||||
|
||||
sz = sndbuf_getsize(ch->buffer);
|
||||
bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz;
|
||||
|
||||
return bufptr;
|
||||
}
|
||||
|
||||
static void
|
||||
cmi_intr(void *data)
|
||||
{
|
||||
struct cmi_info *cmi = data;
|
||||
u_int32_t intrstat;
|
||||
|
||||
intrstat = cmi_rd(cmi, CMPCI_REG_INTR_STATUS, 4);
|
||||
if ((intrstat & CMPCI_REG_ANY_INTR) == 0) {
|
||||
return;
|
||||
}
|
||||
|
||||
/* Disable interrupts */
|
||||
if (intrstat & CMPCI_REG_CH0_INTR) {
|
||||
cmi_clr4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
|
||||
}
|
||||
|
||||
if (intrstat & CMPCI_REG_CH1_INTR) {
|
||||
cmi_clr4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
|
||||
}
|
||||
|
||||
DEB(printf("cmi_intr - play %d rec %d\n",
|
||||
intrstat & CMPCI_REG_CH0_INTR,
|
||||
(intrstat & CMPCI_REG_CH1_INTR)>>1));
|
||||
|
||||
/* Signal interrupts to channel */
|
||||
if (intrstat & CMPCI_REG_CH0_INTR) {
|
||||
chn_intr(cmi->pch.channel);
|
||||
}
|
||||
|
||||
if (intrstat & CMPCI_REG_CH1_INTR) {
|
||||
chn_intr(cmi->rch.channel);
|
||||
}
|
||||
|
||||
/* Enable interrupts */
|
||||
if (intrstat & CMPCI_REG_CH0_INTR) {
|
||||
cmi_set4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
|
||||
}
|
||||
|
||||
if (intrstat & CMPCI_REG_CH1_INTR) {
|
||||
cmi_set4(cmi, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static pcmchan_caps *
|
||||
cmichan_getcaps(kobj_t obj, void *data)
|
||||
{
|
||||
return &cmi_caps;
|
||||
}
|
||||
|
||||
static kobj_method_t cmichan_methods[] = {
|
||||
KOBJMETHOD(channel_init, cmichan_init),
|
||||
KOBJMETHOD(channel_setformat, cmichan_setformat),
|
||||
KOBJMETHOD(channel_setspeed, cmichan_setspeed),
|
||||
KOBJMETHOD(channel_setblocksize, cmichan_setblocksize),
|
||||
KOBJMETHOD(channel_trigger, cmichan_trigger),
|
||||
KOBJMETHOD(channel_getptr, cmichan_getptr),
|
||||
KOBJMETHOD(channel_getcaps, cmichan_getcaps),
|
||||
{ 0, 0 }
|
||||
};
|
||||
CHANNEL_DECLARE(cmichan);
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* Mixer - sb16 with kinks */
|
||||
|
||||
static void
|
||||
cmimix_wr(struct cmi_info *cmi, u_int8_t port, u_int8_t val)
|
||||
{
|
||||
cmi_wr(cmi, CMPCI_REG_SBADDR, port, 1);
|
||||
cmi_wr(cmi, CMPCI_REG_SBDATA, val, 1);
|
||||
}
|
||||
|
||||
static u_int8_t
|
||||
cmimix_rd(struct cmi_info *cmi, u_int8_t port)
|
||||
{
|
||||
cmi_wr(cmi, CMPCI_REG_SBADDR, port, 1);
|
||||
return (u_int8_t)cmi_rd(cmi, CMPCI_REG_SBDATA, 1);
|
||||
}
|
||||
|
||||
struct sb16props {
|
||||
u_int8_t rreg; /* right reg chan register */
|
||||
u_int8_t stereo:1; /* (no explanation needed, honest) */
|
||||
u_int8_t rec:1; /* recording source */
|
||||
u_int8_t bits:3; /* num bits to represent maximum gain rep */
|
||||
u_int8_t oselect; /* output select mask */
|
||||
u_int8_t iselect; /* right input select mask */
|
||||
} static const cmt[SOUND_MIXER_NRDEVICES] = {
|
||||
[SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5,
|
||||
CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R},
|
||||
[SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5,
|
||||
CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R},
|
||||
[SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5,
|
||||
CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R},
|
||||
[SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5,
|
||||
CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC},
|
||||
[SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0},
|
||||
[SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0},
|
||||
[SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0},
|
||||
/* These controls are not implemented in CMI8738, but maybe at a
|
||||
future date. They are not documented in C-Media documentation,
|
||||
though appear in other drivers for future h/w (ALSA, Linux, NetBSD).
|
||||
*/
|
||||
[SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0},
|
||||
[SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0},
|
||||
[SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0},
|
||||
[SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0},
|
||||
/* The mic pre-amp is implemented with non-SB16 compatible registers. */
|
||||
[SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0},
|
||||
};
|
||||
|
||||
#define MIXER_GAIN_REG_RTOL(r) (r - 1)
|
||||
|
||||
static int
|
||||
cmimix_init(snd_mixer *m)
|
||||
{
|
||||
struct cmi_info *cmi = mix_getdevinfo(m);
|
||||
u_int32_t i,v;
|
||||
|
||||
v = 0;
|
||||
for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
|
||||
if (cmt[i].bits) v |= 1 << i;
|
||||
}
|
||||
mix_setdevs(m, v);
|
||||
v = 0;
|
||||
for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
|
||||
if (cmt[i].rec) v |= 1 << i;
|
||||
}
|
||||
mix_setrecdevs(m, v);
|
||||
|
||||
cmimix_wr(cmi, CMPCI_SB16_MIXER_RESET, 0);
|
||||
cmimix_wr(cmi, CMPCI_SB16_MIXER_ADCMIX_L, 0);
|
||||
cmimix_wr(cmi, CMPCI_SB16_MIXER_ADCMIX_R, 0);
|
||||
cmimix_wr(cmi, CMPCI_SB16_MIXER_OUTMIX,
|
||||
CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
cmimix_set(snd_mixer *m, unsigned dev, unsigned left, unsigned right)
|
||||
{
|
||||
struct cmi_info *cmi = mix_getdevinfo(m);
|
||||
u_int32_t r, l, max;
|
||||
u_int8_t v;
|
||||
|
||||
max = (1 << cmt[dev].bits) - 1;
|
||||
|
||||
if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) {
|
||||
/* For time being this can only be one thing (mic in mic/aux reg) */
|
||||
u_int8_t v;
|
||||
v = cmi_rd(cmi, CMPCI_REG_AUX_MIC, 1) & 0xf0;
|
||||
l = left * max / 100;
|
||||
/* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value*/
|
||||
v |= ((l << 1) | (~l >> 3)) & 0x0f;
|
||||
cmi_wr(cmi, CMPCI_REG_AUX_MIC, v, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
l = (left * max / 100) << (8 - cmt[dev].bits);
|
||||
if (cmt[dev].stereo) {
|
||||
r = (right * max / 100) << (8 - cmt[dev].bits);
|
||||
cmimix_wr(cmi, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l);
|
||||
cmimix_wr(cmi, cmt[dev].rreg, r);
|
||||
DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\
|
||||
"value 0x%02x:0x%02x\n",
|
||||
dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r));
|
||||
} else {
|
||||
r = l;
|
||||
cmimix_wr(cmi, cmt[dev].rreg, l);
|
||||
DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \
|
||||
"value 0x%02x:0x%02x\n",
|
||||
dev, cmt[dev].rreg, l, l));
|
||||
}
|
||||
|
||||
/* Zero gain does not mute channel from output, but this does... */
|
||||
v = cmimix_rd(cmi, CMPCI_SB16_MIXER_OUTMIX);
|
||||
if (l == 0 && r == 0) {
|
||||
v &= ~cmt[dev].oselect;
|
||||
} else {
|
||||
v |= cmt[dev].oselect;
|
||||
}
|
||||
cmimix_wr(cmi, CMPCI_SB16_MIXER_OUTMIX, v);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
cmimix_setrecsrc(snd_mixer *m, u_int32_t src)
|
||||
{
|
||||
struct cmi_info *cmi = mix_getdevinfo(m);
|
||||
u_int32_t i, ml, sl;
|
||||
|
||||
ml = sl = 0;
|
||||
for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
|
||||
if ((1<<i) & src) {
|
||||
if (cmt[i].stereo) {
|
||||
sl |= cmt[i].iselect;
|
||||
} else {
|
||||
ml |= cmt[i].iselect;
|
||||
}
|
||||
}
|
||||
}
|
||||
cmimix_wr(cmi, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml);
|
||||
DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
|
||||
CMPCI_SB16_MIXER_ADCMIX_R, sl|ml));
|
||||
ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml);
|
||||
cmimix_wr(cmi, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml);
|
||||
DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
|
||||
CMPCI_SB16_MIXER_ADCMIX_L, sl|ml));
|
||||
|
||||
return src;
|
||||
}
|
||||
|
||||
static kobj_method_t cmi_mixer_methods[] = {
|
||||
KOBJMETHOD(mixer_init, cmimix_init),
|
||||
KOBJMETHOD(mixer_set, cmimix_set),
|
||||
KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc),
|
||||
{ 0, 0 }
|
||||
};
|
||||
MIXER_DECLARE(cmi_mixer);
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* Power and reset */
|
||||
|
||||
static void
|
||||
cmi_power(struct cmi_info *cmi, int state)
|
||||
{
|
||||
switch (state) {
|
||||
case 0: /* full power */
|
||||
cmi_clr4(cmi, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
|
||||
break;
|
||||
default:
|
||||
/* power off */
|
||||
cmi_set4(cmi, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* Bus and device registration */
|
||||
static int
|
||||
cmi_probe(device_t dev)
|
||||
{
|
||||
switch(pci_get_devid(dev)) {
|
||||
case CMI8338A_PCI_ID:
|
||||
device_set_desc(dev, "CMedia CMI8338A");
|
||||
return 0;
|
||||
case CMI8338B_PCI_ID:
|
||||
device_set_desc(dev, "CMedia CMI8338B");
|
||||
return 0;
|
||||
case CMI8738_PCI_ID:
|
||||
device_set_desc(dev, "CMedia CMI8738");
|
||||
return 0;
|
||||
case CMI8738B_PCI_ID:
|
||||
device_set_desc(dev, "CMedia CMI8738B");
|
||||
return 0;
|
||||
default:
|
||||
return ENXIO;
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
cmi_attach(device_t dev)
|
||||
{
|
||||
snddev_info *d;
|
||||
struct cmi_info *cmi;
|
||||
u_int32_t data;
|
||||
char status[SND_STATUSLEN];
|
||||
|
||||
d = device_get_softc(dev);
|
||||
|
||||
if ((cmi = malloc(sizeof(struct cmi_info), M_DEVBUF, M_NOWAIT)) == NULL) {
|
||||
device_printf(dev, "cannot allocate softc\n");
|
||||
return ENXIO;
|
||||
}
|
||||
|
||||
bzero(cmi, sizeof(*cmi));
|
||||
|
||||
data = pci_read_config(dev, PCIR_COMMAND, 2);
|
||||
data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN);
|
||||
pci_write_config(dev, PCIR_COMMAND, data, 2);
|
||||
data = pci_read_config(dev, PCIR_COMMAND, 2);
|
||||
|
||||
cmi->regid = PCIR_MAPS;
|
||||
cmi->reg = bus_alloc_resource(dev, SYS_RES_IOPORT, &cmi->regid,
|
||||
0, BUS_SPACE_UNRESTRICTED, 1, RF_ACTIVE);
|
||||
if (!cmi->reg) {
|
||||
device_printf(dev, "cmi_attach: Cannot allocate bus resource\n");
|
||||
goto bad;
|
||||
}
|
||||
cmi->st = rman_get_bustag(cmi->reg);
|
||||
cmi->sh = rman_get_bushandle(cmi->reg);
|
||||
|
||||
cmi->irqid = 0;
|
||||
cmi->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &cmi->irqid,
|
||||
0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
|
||||
if (!cmi->irq ||
|
||||
bus_setup_intr(dev, cmi->irq, INTR_TYPE_TTY, cmi_intr, cmi, &cmi->ih)){
|
||||
device_printf(dev, "cmi_attach: Unable to map interrupt\n");
|
||||
goto bad;
|
||||
}
|
||||
|
||||
if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
|
||||
/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
|
||||
/*highaddr*/BUS_SPACE_MAXADDR,
|
||||
/*filter*/NULL, /*filterarg*/NULL,
|
||||
/*maxsize*/CMI_BUFFER_SIZE, /*nsegments*/1,
|
||||
/*maxsegz*/0x3ffff, /*flags*/0,
|
||||
&cmi->parent_dmat) != 0) {
|
||||
device_printf(dev, "cmi_attach: Unable to create dma tag\n");
|
||||
goto bad;
|
||||
}
|
||||
|
||||
cmi_power(cmi, 0);
|
||||
/* Disable interrupts and channels */
|
||||
cmi_clr4(cmi, CMPCI_REG_INTR_CTRL,
|
||||
CMPCI_REG_CH0_INTR_ENABLE |
|
||||
CMPCI_REG_CH1_INTR_ENABLE |
|
||||
CMPCI_REG_TDMA_INTR_ENABLE);
|
||||
cmi_clr4(cmi, CMPCI_REG_FUNC_0,
|
||||
CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
|
||||
|
||||
mixer_init(dev, &cmi_mixer_class, cmi);
|
||||
|
||||
if (pcm_register(dev, cmi, 1, 1))
|
||||
goto bad;
|
||||
|
||||
pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, cmi);
|
||||
pcm_addchan(dev, PCMDIR_REC, &cmichan_class, cmi);
|
||||
|
||||
snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld",
|
||||
rman_get_start(cmi->reg), rman_get_start(cmi->irq));
|
||||
pcm_setstatus(dev, status);
|
||||
|
||||
DEB(printf("cmi_attach: succeeded\n"));
|
||||
return 0;
|
||||
|
||||
bad:
|
||||
if (cmi->parent_dmat) bus_dma_tag_destroy(cmi->parent_dmat);
|
||||
if (cmi->ih) bus_teardown_intr(dev, cmi->irq, cmi->ih);
|
||||
if (cmi->irq) bus_release_resource(dev, SYS_RES_IRQ, cmi->irqid, cmi->irq);
|
||||
if (cmi->reg) bus_release_resource(dev, SYS_RES_IOPORT,
|
||||
cmi->regid, cmi->reg);
|
||||
if (cmi) free(cmi, M_DEVBUF);
|
||||
|
||||
return ENXIO;
|
||||
}
|
||||
|
||||
static int
|
||||
cmi_detach(device_t dev)
|
||||
{
|
||||
struct cmi_info *cmi;
|
||||
int r;
|
||||
|
||||
r = pcm_unregister(dev);
|
||||
if (r) return r;
|
||||
|
||||
cmi = pcm_getdevinfo(dev);
|
||||
cmi_power(cmi, 3);
|
||||
bus_dma_tag_destroy(cmi->parent_dmat);
|
||||
bus_teardown_intr(dev, cmi->irq, cmi->ih);
|
||||
bus_release_resource(dev, SYS_RES_IRQ, cmi->irqid, cmi->irq);
|
||||
bus_release_resource(dev, SYS_RES_IOPORT, cmi->regid, cmi->reg);
|
||||
free(cmi, M_DEVBUF);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static device_method_t cmi_methods[] = {
|
||||
DEVMETHOD(device_probe, cmi_probe),
|
||||
DEVMETHOD(device_attach, cmi_attach),
|
||||
DEVMETHOD(device_detach, cmi_detach),
|
||||
DEVMETHOD(device_resume, bus_generic_resume),
|
||||
DEVMETHOD(device_suspend, bus_generic_suspend),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static driver_t cmi_driver = {
|
||||
"pcm",
|
||||
cmi_methods,
|
||||
sizeof(snddev_info)
|
||||
};
|
||||
|
||||
static devclass_t pcm_devclass;
|
||||
DRIVER_MODULE(snd_cmipci, pci, cmi_driver, pcm_devclass, 0, 0);
|
||||
MODULE_DEPEND(snd_cmipci, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
|
||||
MODULE_VERSION(snd_cmipci, 1);
|
||||
203
sys/dev/sound/pci/cmireg.h
Normal file
203
sys/dev/sound/pci/cmireg.h
Normal file
|
|
@ -0,0 +1,203 @@
|
|||
/*
|
||||
* Copyright (c) 2000 The NetBSD Foundation, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This code is derived from software contributed to The NetBSD Foundation
|
||||
* by Takuya SHIOZAKI <AoiMoe@imou.to> .
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/* C-Media CMI8x38 Audio Chip Support */
|
||||
|
||||
#ifndef _DEV_PCI_CMPCIREG_H_
|
||||
#define _DEV_PCI_CMPCIREG_H_ (1)
|
||||
|
||||
/*
|
||||
* PCI Configuration Registers
|
||||
*/
|
||||
|
||||
#define CMPCI_PCI_IOBASEREG (PCI_MAPREG_START)
|
||||
|
||||
/*
|
||||
* I/O Space
|
||||
*/
|
||||
|
||||
#define CMPCI_REG_FUNC_0 0x00
|
||||
# define CMPCI_REG_CH0_DIR 0x00000001
|
||||
# define CMPCI_REG_CH1_DIR 0x00000002
|
||||
# define CMPCI_REG_CH0_PAUSE 0x00000004
|
||||
# define CMPCI_REG_CH1_PAUSE 0x00000008
|
||||
# define CMPCI_REG_CH0_ENABLE 0x00010000
|
||||
# define CMPCI_REG_CH1_ENABLE 0x00020000
|
||||
# define CMPCI_REG_CH0_RESET 0x00040000
|
||||
# define CMPCI_REG_CH1_RESET 0x00080000
|
||||
|
||||
#define CMPCI_REG_FUNC_1 0x04
|
||||
# define CMPCI_REG_JOY_ENABLE 0x00000002
|
||||
# define CMPCI_REG_UART_ENABLE 0x00000004
|
||||
# define CMPCI_REG_LEGACY_ENABLE 0x00000008
|
||||
# define CMPCI_REG_BREQ 0x00000010
|
||||
# define CMPCI_REG_MCBINTR_ENABLE 0x00000020
|
||||
# define CMPCI_REG_SPDIFOUT_DAC 0x00000040
|
||||
# define CMPCI_REG_SPDIF_LOOP 0x00000080
|
||||
# define CMPCI_REG_SPDIF0_ENABLE 0x00000100
|
||||
# define CMPCI_REG_SPDIF1_ENABLE 0x00000200
|
||||
# define CMPCI_REG_DAC_FS_SHIFT 10
|
||||
# define CMPCI_REG_DAC_FS_MASK 0x00000007
|
||||
# define CMPCI_REG_ADC_FS_SHIFT 13
|
||||
# define CMPCI_REG_ADC_FS_MASK 0x00000007
|
||||
|
||||
#define CMPCI_REG_CHANNEL_FORMAT 0x08
|
||||
# define CMPCI_REG_CH0_FORMAT_SHIFT 0
|
||||
# define CMPCI_REG_CH0_FORMAT_MASK 0x00000003
|
||||
# define CMPCI_REG_CH1_FORMAT_SHIFT 2
|
||||
# define CMPCI_REG_CH1_FORMAT_MASK 0x00000003
|
||||
# define CMPCI_REG_FORMAT_MONO 0x00000000
|
||||
# define CMPCI_REG_FORMAT_STEREO 0x00000001
|
||||
# define CMPCI_REG_FORMAT_8BIT 0x00000000
|
||||
# define CMPCI_REG_FORMAT_16BIT 0x00000002
|
||||
|
||||
#define CMPCI_REG_INTR_CTRL 0x0c
|
||||
# define CMPCI_REG_CH0_INTR_ENABLE 0x00010000
|
||||
# define CMPCI_REG_CH1_INTR_ENABLE 0x00020000
|
||||
# define CMPCI_REG_TDMA_INTR_ENABLE 0x00040000
|
||||
|
||||
#define CMPCI_REG_INTR_STATUS 0x10
|
||||
# define CMPCI_REG_CH0_INTR 0x00000001
|
||||
# define CMPCI_REG_CH1_INTR 0x00000002
|
||||
# define CMPCI_REG_CH0_BUSY 0x00000004
|
||||
# define CMPCI_REG_CH1_BUSY 0x00000008
|
||||
# define CMPCI_REG_LEGACY_STEREO 0x00000010
|
||||
# define CMPCI_REG_LEGACY_HDMA 0x00000020
|
||||
# define CMPCI_REG_DMASTAT 0x00000040
|
||||
# define CMPCI_REG_XDO46 0x00000080
|
||||
# define CMPCI_REG_HTDMA_INTR 0x00004000
|
||||
# define CMPCI_REG_LTDMA_INTR 0x00008000
|
||||
# define CMPCI_REG_UART_INTR 0x00010000
|
||||
# define CMPCI_REG_MCB_INTR 0x04000000
|
||||
# define CMPCI_REG_VCO 0x08000000
|
||||
# define CMPCI_REG_ANY_INTR 0x80000000
|
||||
|
||||
#define CMPCI_REG_LEGACY_CTRL 0x14
|
||||
# define CMPCI_REG_LEGACY_SPDIF_ENABLE 0x00200000
|
||||
# define CMPCI_REG_SPDIF_COPYRIGHT 0x00400000
|
||||
# define CMPCI_REG_XSPDIF_ENABLE 0x00800000
|
||||
# define CMPCI_REG_FMSEL_SHIFT 24
|
||||
# define CMPCI_REG_FMSEL_MASK 0x00000003
|
||||
# define CMPCI_REG_VSBSEL_SHIFT 26
|
||||
# define CMPCI_REG_VSBSEL_MASK 0x00000003
|
||||
# define CMPCI_REG_VMPUSEL_SHIFT 29
|
||||
# define CMPCI_REG_VMPUSEL_MASK 0x00000003
|
||||
|
||||
#define CMPCI_REG_MISC 0x18
|
||||
# define CMPCI_REG_POWER_DOWN 0x80000000
|
||||
# define CMPCI_REG_BUS_AND_DSP_RESET 0x40000000
|
||||
# define CMPCI_REG_W_SPDIF_48L 0x01000000
|
||||
# define CMPCI_REG_SPDIF_48K 0x00008000
|
||||
# define CMPCI_REG_FM_ENABLE 0x00080000
|
||||
|
||||
#define CMPCI_REG_SBDATA 0x22
|
||||
#define CMPCI_REG_SBADDR 0x23
|
||||
# define CMPCI_SB16_MIXER_RESET 0x00
|
||||
# define CMPCI_SB16_MIXER_MASTER_L 0x30
|
||||
# define CMPCI_SB16_MIXER_MASTER_R 0x31
|
||||
# define CMPCI_SB16_MIXER_VOICE_L 0x32
|
||||
# define CMPCI_SB16_MIXER_VOICE_R 0x33
|
||||
# define CMPCI_SB16_MIXER_FM_L 0x34
|
||||
# define CMPCI_SB16_MIXER_FM_R 0x35
|
||||
# define CMPCI_SB16_MIXER_CDDA_L 0x36
|
||||
# define CMPCI_SB16_MIXER_CDDA_R 0x37
|
||||
# define CMPCI_SB16_MIXER_LINE_L 0x38
|
||||
# define CMPCI_SB16_MIXER_LINE_R 0x39
|
||||
# define CMPCI_SB16_MIXER_MIC 0x3A
|
||||
# define CMPCI_SB16_MIXER_SPEAKER 0x3B
|
||||
# define CMPCI_SB16_MIXER_OUTMIX 0x3C
|
||||
# define CMPCI_SB16_SW_MIC 0x01
|
||||
# define CMPCI_SB16_SW_CD_R 0x02
|
||||
# define CMPCI_SB16_SW_CD_L 0x04
|
||||
# define CMPCI_SB16_SW_CD (CMPCI_SB16_SW_CD_L|CMPCI_SB16_SW_CD_R)
|
||||
# define CMPCI_SB16_SW_LINE_R 0x08
|
||||
# define CMPCI_SB16_SW_LINE_L 0x10
|
||||
# define CMPCI_SB16_SW_LINE (CMPCI_SB16_SW_LINE_L|CMPCI_SB16_SW_LINE_R)
|
||||
# define CMPCI_SB16_SW_FM_R 0x20
|
||||
# define CMPCI_SB16_SW_FM_L 0x40
|
||||
# define CMPCI_SB16_SW_FM (CMPCI_SB16_SW_FM_L|CMPCI_SB16_SW_FM_R)
|
||||
# define CMPCI_SB16_MIXER_ADCMIX_L 0x3D
|
||||
# define CMPCI_SB16_MIXER_ADCMIX_R 0x3E
|
||||
# define CMPCI_SB16_MIXER_FM_SRC_R 0x20
|
||||
# define CMPCI_SB16_MIXER_LINE_SRC_R 0x08
|
||||
# define CMPCI_SB16_MIXER_CD_SRC_R 0x02
|
||||
# define CMPCI_SB16_MIXER_MIC_SRC 0x01
|
||||
# define CMPCI_SB16_MIXER_SRC_R_TO_L(v) ((v) << 1)
|
||||
|
||||
# define CMPCI_SB16_MIXER_INGAIN_L 0x3F
|
||||
# define CMPCI_SB16_MIXER_INGAIN_R 0x40
|
||||
# define CMPCI_SB16_MIXER_OUTGAIN_L 0x41
|
||||
# define CMPCI_SB16_MIXER_OUTGAIN_R 0x42
|
||||
# define CMPCI_SB16_MIXER_AGC 0x43
|
||||
# define CMPCI_SB16_MIXER_TREBLE_L 0x44
|
||||
# define CMPCI_SB16_MIXER_TREBLE_R 0x45
|
||||
# define CMPCI_SB16_MIXER_BASS_L 0x46
|
||||
# define CMPCI_SB16_MIXER_BASS_R 0x47
|
||||
# define CMPCI_SB16_MIXER_L_TO_R(addr) ((addr)+1)
|
||||
|
||||
# define CMPCI_ADJUST_MIC_GAIN(sc, x) cmpci_adjust((x), 0xf8)
|
||||
# define CMPCI_ADJUST_GAIN(sc, x) cmpci_adjust((x), 0xf8)
|
||||
# define CMPCI_ADJUST_2_GAIN(sc, x) cmpci_adjust((x), 0xc0)
|
||||
|
||||
#define CMPCI_REG_MPU_BASE 0x40
|
||||
#define CMPCI_REG_MPU_SIZE 0x10
|
||||
#define CMPCI_REG_FM_BASE 0x50
|
||||
#define CMPCI_REG_FM_SIZE 0x10
|
||||
|
||||
#define CMPCI_REG_AUX_MIC 0x25
|
||||
# define CMPCI_AUX_SELECT_R 0x80
|
||||
# define CMPCI_AUX_SELECT_L 0x40
|
||||
# define CMPCI_AUX_MUTE_R 0x20
|
||||
# define CMPCI_AUX_MUTE_L 0x10
|
||||
# define CMPCI_VAD_MIC 0x0e
|
||||
# define CMPCI_MIC_QUIET 0x01
|
||||
|
||||
#define CMPCI_REG_DMA0_BASE 0x80
|
||||
#define CMPCI_REG_DMA0_BYTES 0x84
|
||||
#define CMPCI_REG_DMA0_SAMPLES 0x86
|
||||
#define CMPCI_REG_DMA1_BASE 0x88
|
||||
#define CMPCI_REG_DMA1_BYTES 0x8C
|
||||
#define CMPCI_REG_DMA1_SAMPLES 0x8E
|
||||
|
||||
/* sample rate */
|
||||
#define CMPCI_REG_RATE_5512 0
|
||||
#define CMPCI_REG_RATE_11025 1
|
||||
#define CMPCI_REG_RATE_22050 2
|
||||
#define CMPCI_REG_RATE_44100 3
|
||||
#define CMPCI_REG_RATE_8000 4
|
||||
#define CMPCI_REG_RATE_16000 5
|
||||
#define CMPCI_REG_RATE_32000 6
|
||||
#define CMPCI_REG_RATE_48000 7
|
||||
#define CMPCI_REG_NUMRATE 8
|
||||
|
||||
#endif /* _DEV_PCI_CMPCIREG_H_ */
|
||||
|
||||
/* end of file */
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
# $FreeBSD$
|
||||
|
||||
SUBDIR = ad1816 csa csapcm ds1 emu10k1 es137x es1888 ess fm801 gusc
|
||||
SUBDIR = ad1816 cmi csa csapcm ds1 emu10k1 es137x es1888 ess fm801 gusc
|
||||
SUBDIR += maestro maestro3 mss neomagic sb16 sb8 sbc solo t4dwave via82c686
|
||||
SUBDIR += driver
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue