mirror of
https://github.com/freebsd/freebsd-src
synced 2024-10-17 05:43:59 +00:00
Fix style(9).
This commit is contained in:
Jung-uk Kim
parent
9ae328fc8f
commit
ea9b97d2bd
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=165811
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@ -50,8 +50,6 @@ __FBSDID("$FreeBSD$");
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#define MAX_APSIZE 0x3f /* 256 MB */
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static void agp_intel_commit_gatt(device_t dev);
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struct agp_intel_softc {
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struct agp_softc agp;
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u_int32_t initial_aperture; /* aperture size at startup */
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@ -64,70 +62,53 @@ agp_intel_match(device_t dev)
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{
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if (pci_get_class(dev) != PCIC_BRIDGE
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|| pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
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return NULL;
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return (NULL);
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if (agp_find_caps(dev) == 0)
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return NULL;
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return (NULL);
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switch (pci_get_devid(dev)) {
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/* Intel -- vendor 0x8086 */
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case 0x71808086:
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return ("Intel 82443LX (440 LX) host to PCI bridge");
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case 0x71908086:
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return ("Intel 82443BX (440 BX) host to PCI bridge");
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case 0x71a08086:
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return ("Intel 82443GX host to PCI bridge");
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case 0x71a18086:
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return ("Intel 82443GX host to AGP bridge");
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case 0x11308086:
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return ("Intel 82815 (i815 GMCH) host to PCI bridge");
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case 0x25008086:
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case 0x25018086:
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return ("Intel 82820 host to AGP bridge");
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case 0x35758086:
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return ("Intel 82830 host to AGP bridge");
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case 0x1a218086:
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return ("Intel 82840 host to AGP bridge");
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case 0x1a308086:
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return ("Intel 82845 host to AGP bridge");
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case 0x25308086:
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return ("Intel 82850 host to AGP bridge");
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case 0x33408086:
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return ("Intel 82855 host to AGP bridge");
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case 0x25318086:
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return ("Intel 82860 host to AGP bridge");
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case 0x25708086:
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return ("Intel 82865 host to AGP bridge");
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case 0x255d8086:
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return ("Intel E7205 host to AGP bridge");
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case 0x25508086:
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return ("Intel E7505 host to AGP bridge");
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case 0x25788086:
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return ("Intel 82875P host to AGP bridge");
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case 0x25608086:
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return ("Intel 82845G host to AGP bridge");
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case 0x35808086:
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return ("Intel 82855GM host to AGP bridge");
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};
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return NULL;
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return (NULL);
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}
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static int
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@ -140,21 +121,24 @@ agp_intel_probe(device_t dev)
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desc = agp_intel_match(dev);
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if (desc) {
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device_set_desc(dev, desc);
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return BUS_PROBE_DEFAULT;
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return (BUS_PROBE_DEFAULT);
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}
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return ENXIO;
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return (ENXIO);
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}
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static void agp_intel_commit_gatt(device_t dev)
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static void
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agp_intel_commit_gatt(device_t dev)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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struct agp_gatt *gatt = sc->gatt;
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u_int32_t type = pci_get_devid(dev);
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struct agp_intel_softc *sc;
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u_int32_t type;
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u_int32_t value;
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sc = device_get_softc(dev);
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type = pci_get_devid(dev);
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/* Install the gatt. */
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pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);
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pci_write_config(dev, AGP_INTEL_ATTBASE, sc->gatt->ag_physical, 4);
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/* Enable the GLTB and setup the control register. */
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switch (type) {
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@ -182,14 +166,12 @@ static void agp_intel_commit_gatt(device_t dev)
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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| (1 << 9)), 2);
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break;
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case 0x25008086: /* i820 */
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case 0x25018086: /* i820 */
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pci_write_config(dev, AGP_INTEL_I820_RDCR,
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(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
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| (1 << 1)), 1);
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break;
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case 0x1a308086: /* i845 */
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case 0x33408086: /* i855 */
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case 0x35808086: /* i855GM */
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@ -202,7 +184,6 @@ static void agp_intel_commit_gatt(device_t dev)
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(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
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| (1 << 1)), 1);
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break;
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default: /* Intel Generic (maybe) */
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pci_write_config(dev, AGP_INTEL_NBXCFG,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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@ -213,7 +194,6 @@ static void agp_intel_commit_gatt(device_t dev)
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case 0x1a218086: /* i840 */
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pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
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break;
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case 0x25008086: /* i820 */
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case 0x25018086: /* i820 */
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case 0x1a308086: /* i845 */
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@ -227,7 +207,6 @@ static void agp_intel_commit_gatt(device_t dev)
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case 0x25608086: /* i845G */
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pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
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break;
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default: /* Intel Generic (maybe) */
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pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
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}
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@ -236,14 +215,16 @@ static void agp_intel_commit_gatt(device_t dev)
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static int
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agp_intel_attach(device_t dev)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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struct agp_intel_softc *sc;
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struct agp_gatt *gatt;
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u_int32_t value;
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int error;
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sc = device_get_softc(dev);
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error = agp_generic_attach(dev);
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if (error)
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return error;
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return (error);
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/* Determine maximum supported aperture size. */
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value = pci_read_config(dev, AGP_INTEL_APSIZE, 1);
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@ -264,28 +245,29 @@ agp_intel_attach(device_t dev)
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*/
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if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
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agp_generic_detach(dev);
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return ENOMEM;
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return (ENOMEM);
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}
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}
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sc->gatt = gatt;
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agp_intel_commit_gatt(dev);
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return 0;
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return (0);
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}
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static int
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agp_intel_detach(device_t dev)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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u_int32_t type = pci_get_devid(dev);
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struct agp_intel_softc *sc;
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int error;
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sc = device_get_softc(dev);
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error = agp_generic_detach(dev);
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if (error)
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return error;
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return (error);
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switch (type) {
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switch (pci_get_devid(dev)) {
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case 0x1a218086: /* i840 */
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case 0x25308086: /* i850 */
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case 0x25318086: /* i860 */
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@ -295,7 +277,7 @@ agp_intel_detach(device_t dev)
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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& ~(1 << 9)), 2);
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/* FALLTHRU */
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case 0x25008086: /* i820 */
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case 0x25018086: /* i820 */
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printf("%s: set RDCR to %x\n", __func__, (unsigned)
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@ -304,7 +286,7 @@ agp_intel_detach(device_t dev)
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pci_write_config(dev, AGP_INTEL_I820_RDCR,
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(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
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& ~(1 << 1)), 1);
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/* FALLTHRU */
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case 0x1a308086: /* i845 */
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case 0x25608086: /* i845G */
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case 0x33408086: /* i855 */
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@ -319,7 +301,7 @@ agp_intel_detach(device_t dev)
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pci_write_config(dev, AGP_INTEL_MCHCFG,
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(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
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& ~(1 << 1)), 1);
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/* FALLTHRU */
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default: /* Intel Generic (maybe) */
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printf("%s: set NBXCFG to %x\n", __func__,
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(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
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@ -332,21 +314,24 @@ agp_intel_detach(device_t dev)
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AGP_SET_APERTURE(dev, sc->initial_aperture);
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agp_free_gatt(sc->gatt);
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return 0;
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return (0);
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}
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static int agp_intel_resume(device_t dev)
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static int
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agp_intel_resume(device_t dev)
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{
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agp_intel_commit_gatt(dev);
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return bus_generic_resume(dev);
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return (bus_generic_resume(dev));
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}
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static u_int32_t
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agp_intel_get_aperture(device_t dev)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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struct agp_intel_softc *sc;
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u_int32_t apsize;
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sc = device_get_softc(dev);
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apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask;
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/*
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@ -356,15 +341,17 @@ agp_intel_get_aperture(device_t dev)
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* field just read forces the corresponding bit in the 27:22
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* to be zero. We calculate the aperture size accordingly.
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*/
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return (((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1;
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return ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1);
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}
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static int
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agp_intel_set_aperture(device_t dev, u_int32_t aperture)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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struct agp_intel_softc *sc;
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u_int32_t apsize;
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sc = device_get_softc(dev);
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/*
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* Reverse the magic from get_aperture.
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*/
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@ -374,35 +361,39 @@ agp_intel_set_aperture(device_t dev, u_int32_t aperture)
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* Double check for sanity.
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*/
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if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture)
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return EINVAL;
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return (EINVAL);
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pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1);
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return 0;
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return (0);
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}
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static int
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agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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struct agp_intel_softc *sc;
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sc = device_get_softc(dev);
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if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
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return EINVAL;
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return (EINVAL);
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sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17;
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return 0;
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return (0);
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}
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static int
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agp_intel_unbind_page(device_t dev, int offset)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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struct agp_intel_softc *sc;
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sc = device_get_softc(dev);
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if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
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return EINVAL;
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return (EINVAL);
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sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
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return 0;
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return (0);
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}
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static void
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@ -50,8 +50,6 @@ __FBSDID("$FreeBSD$");
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#define MAX_APSIZE 0x3f /* 256 MB */
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static void agp_intel_commit_gatt(device_t dev);
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struct agp_intel_softc {
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struct agp_softc agp;
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u_int32_t initial_aperture; /* aperture size at startup */
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@ -64,70 +62,53 @@ agp_intel_match(device_t dev)
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{
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if (pci_get_class(dev) != PCIC_BRIDGE
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|| pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
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return NULL;
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return (NULL);
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if (agp_find_caps(dev) == 0)
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return NULL;
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return (NULL);
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switch (pci_get_devid(dev)) {
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/* Intel -- vendor 0x8086 */
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case 0x71808086:
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return ("Intel 82443LX (440 LX) host to PCI bridge");
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|
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case 0x71908086:
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return ("Intel 82443BX (440 BX) host to PCI bridge");
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case 0x71a08086:
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return ("Intel 82443GX host to PCI bridge");
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case 0x71a18086:
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return ("Intel 82443GX host to AGP bridge");
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|
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case 0x11308086:
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return ("Intel 82815 (i815 GMCH) host to PCI bridge");
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case 0x25008086:
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case 0x25018086:
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return ("Intel 82820 host to AGP bridge");
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|
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case 0x35758086:
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return ("Intel 82830 host to AGP bridge");
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|
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case 0x1a218086:
|
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return ("Intel 82840 host to AGP bridge");
|
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|
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case 0x1a308086:
|
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return ("Intel 82845 host to AGP bridge");
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|
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case 0x25308086:
|
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return ("Intel 82850 host to AGP bridge");
|
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|
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case 0x33408086:
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return ("Intel 82855 host to AGP bridge");
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case 0x25318086:
|
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return ("Intel 82860 host to AGP bridge");
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case 0x25708086:
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return ("Intel 82865 host to AGP bridge");
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|
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case 0x255d8086:
|
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return ("Intel E7205 host to AGP bridge");
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|
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case 0x25508086:
|
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return ("Intel E7505 host to AGP bridge");
|
||||
|
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case 0x25788086:
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return ("Intel 82875P host to AGP bridge");
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case 0x25608086:
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return ("Intel 82845G host to AGP bridge");
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case 0x35808086:
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return ("Intel 82855GM host to AGP bridge");
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};
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return NULL;
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return (NULL);
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}
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static int
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|
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@ -140,21 +121,24 @@ agp_intel_probe(device_t dev)
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desc = agp_intel_match(dev);
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if (desc) {
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device_set_desc(dev, desc);
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return BUS_PROBE_DEFAULT;
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return (BUS_PROBE_DEFAULT);
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}
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return ENXIO;
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return (ENXIO);
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}
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static void agp_intel_commit_gatt(device_t dev)
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static void
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agp_intel_commit_gatt(device_t dev)
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{
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struct agp_intel_softc *sc = device_get_softc(dev);
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struct agp_gatt *gatt = sc->gatt;
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u_int32_t type = pci_get_devid(dev);
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struct agp_intel_softc *sc;
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u_int32_t type;
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u_int32_t value;
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sc = device_get_softc(dev);
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type = pci_get_devid(dev);
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/* Install the gatt. */
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pci_write_config(dev, AGP_INTEL_ATTBASE, gatt->ag_physical, 4);
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pci_write_config(dev, AGP_INTEL_ATTBASE, sc->gatt->ag_physical, 4);
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/* Enable the GLTB and setup the control register. */
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switch (type) {
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|
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@ -182,14 +166,12 @@ static void agp_intel_commit_gatt(device_t dev)
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(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
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| (1 << 9)), 2);
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break;
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case 0x25008086: /* i820 */
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case 0x25018086: /* i820 */
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pci_write_config(dev, AGP_INTEL_I820_RDCR,
|
||||
(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
|
||||
| (1 << 1)), 1);
|
||||
break;
|
||||
|
||||
case 0x1a308086: /* i845 */
|
||||
case 0x33408086: /* i855 */
|
||||
case 0x35808086: /* i855GM */
|
||||
|
|
@ -202,7 +184,6 @@ static void agp_intel_commit_gatt(device_t dev)
|
|||
(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
|
||||
| (1 << 1)), 1);
|
||||
break;
|
||||
|
||||
default: /* Intel Generic (maybe) */
|
||||
pci_write_config(dev, AGP_INTEL_NBXCFG,
|
||||
(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
|
||||
|
|
@ -213,7 +194,6 @@ static void agp_intel_commit_gatt(device_t dev)
|
|||
case 0x1a218086: /* i840 */
|
||||
pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
|
||||
break;
|
||||
|
||||
case 0x25008086: /* i820 */
|
||||
case 0x25018086: /* i820 */
|
||||
case 0x1a308086: /* i845 */
|
||||
|
|
@ -227,7 +207,6 @@ static void agp_intel_commit_gatt(device_t dev)
|
|||
case 0x25608086: /* i845G */
|
||||
pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
|
||||
break;
|
||||
|
||||
default: /* Intel Generic (maybe) */
|
||||
pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
|
||||
}
|
||||
|
|
@ -236,14 +215,16 @@ static void agp_intel_commit_gatt(device_t dev)
|
|||
static int
|
||||
agp_intel_attach(device_t dev)
|
||||
{
|
||||
struct agp_intel_softc *sc = device_get_softc(dev);
|
||||
struct agp_intel_softc *sc;
|
||||
struct agp_gatt *gatt;
|
||||
u_int32_t value;
|
||||
int error;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
error = agp_generic_attach(dev);
|
||||
if (error)
|
||||
return error;
|
||||
return (error);
|
||||
|
||||
/* Determine maximum supported aperture size. */
|
||||
value = pci_read_config(dev, AGP_INTEL_APSIZE, 1);
|
||||
|
|
@ -264,28 +245,29 @@ agp_intel_attach(device_t dev)
|
|||
*/
|
||||
if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
|
||||
agp_generic_detach(dev);
|
||||
return ENOMEM;
|
||||
return (ENOMEM);
|
||||
}
|
||||
}
|
||||
sc->gatt = gatt;
|
||||
|
||||
|
||||
agp_intel_commit_gatt(dev);
|
||||
|
||||
return 0;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
agp_intel_detach(device_t dev)
|
||||
{
|
||||
struct agp_intel_softc *sc = device_get_softc(dev);
|
||||
u_int32_t type = pci_get_devid(dev);
|
||||
struct agp_intel_softc *sc;
|
||||
int error;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
error = agp_generic_detach(dev);
|
||||
if (error)
|
||||
return error;
|
||||
return (error);
|
||||
|
||||
switch (type) {
|
||||
switch (pci_get_devid(dev)) {
|
||||
case 0x1a218086: /* i840 */
|
||||
case 0x25308086: /* i850 */
|
||||
case 0x25318086: /* i860 */
|
||||
|
|
@ -295,7 +277,7 @@ agp_intel_detach(device_t dev)
|
|||
pci_write_config(dev, AGP_INTEL_MCHCFG,
|
||||
(pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
|
||||
& ~(1 << 9)), 2);
|
||||
|
||||
/* FALLTHRU */
|
||||
case 0x25008086: /* i820 */
|
||||
case 0x25018086: /* i820 */
|
||||
printf("%s: set RDCR to %x\n", __func__, (unsigned)
|
||||
|
|
@ -304,7 +286,7 @@ agp_intel_detach(device_t dev)
|
|||
pci_write_config(dev, AGP_INTEL_I820_RDCR,
|
||||
(pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
|
||||
& ~(1 << 1)), 1);
|
||||
|
||||
/* FALLTHRU */
|
||||
case 0x1a308086: /* i845 */
|
||||
case 0x25608086: /* i845G */
|
||||
case 0x33408086: /* i855 */
|
||||
|
|
@ -319,7 +301,7 @@ agp_intel_detach(device_t dev)
|
|||
pci_write_config(dev, AGP_INTEL_MCHCFG,
|
||||
(pci_read_config(dev, AGP_INTEL_I845_MCHCFG, 1)
|
||||
& ~(1 << 1)), 1);
|
||||
|
||||
/* FALLTHRU */
|
||||
default: /* Intel Generic (maybe) */
|
||||
printf("%s: set NBXCFG to %x\n", __func__,
|
||||
(pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
|
||||
|
|
@ -332,21 +314,24 @@ agp_intel_detach(device_t dev)
|
|||
AGP_SET_APERTURE(dev, sc->initial_aperture);
|
||||
agp_free_gatt(sc->gatt);
|
||||
|
||||
return 0;
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int agp_intel_resume(device_t dev)
|
||||
static int
|
||||
agp_intel_resume(device_t dev)
|
||||
{
|
||||
agp_intel_commit_gatt(dev);
|
||||
return bus_generic_resume(dev);
|
||||
return (bus_generic_resume(dev));
|
||||
}
|
||||
|
||||
static u_int32_t
|
||||
agp_intel_get_aperture(device_t dev)
|
||||
{
|
||||
struct agp_intel_softc *sc = device_get_softc(dev);
|
||||
struct agp_intel_softc *sc;
|
||||
u_int32_t apsize;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask;
|
||||
|
||||
/*
|
||||
|
|
@ -356,15 +341,17 @@ agp_intel_get_aperture(device_t dev)
|
|||
* field just read forces the corresponding bit in the 27:22
|
||||
* to be zero. We calculate the aperture size accordingly.
|
||||
*/
|
||||
return (((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1;
|
||||
return ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1);
|
||||
}
|
||||
|
||||
static int
|
||||
agp_intel_set_aperture(device_t dev, u_int32_t aperture)
|
||||
{
|
||||
struct agp_intel_softc *sc = device_get_softc(dev);
|
||||
struct agp_intel_softc *sc;
|
||||
u_int32_t apsize;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
/*
|
||||
* Reverse the magic from get_aperture.
|
||||
*/
|
||||
|
|
@ -374,35 +361,39 @@ agp_intel_set_aperture(device_t dev, u_int32_t aperture)
|
|||
* Double check for sanity.
|
||||
*/
|
||||
if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture)
|
||||
return EINVAL;
|
||||
return (EINVAL);
|
||||
|
||||
pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1);
|
||||
|
||||
return 0;
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
agp_intel_bind_page(device_t dev, int offset, vm_offset_t physical)
|
||||
{
|
||||
struct agp_intel_softc *sc = device_get_softc(dev);
|
||||
struct agp_intel_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
|
||||
return EINVAL;
|
||||
return (EINVAL);
|
||||
|
||||
sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17;
|
||||
return 0;
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
agp_intel_unbind_page(device_t dev, int offset)
|
||||
{
|
||||
struct agp_intel_softc *sc = device_get_softc(dev);
|
||||
struct agp_intel_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
|
||||
return EINVAL;
|
||||
return (EINVAL);
|
||||
|
||||
sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
|
||||
return 0;
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
|
|||
Loading…
Reference in a new issue