mirror of
https://github.com/freebsd/freebsd-src
synced 2024-09-06 09:10:28 +00:00
Since if_gem is being touted as one of our more architecturally
correct network drivers with respect to busmaster DMA, go over it with at duster to make other aspects of it a role model: Eliminate the pci specific softc, it serves no rational purpose. Use convenience resource allocation/deallocation functions to save code and errorhandling. Switch from bus_space_{read|write}_%u() to bus_{read|write}_%u() functions and forget about tags and handles, the resource will know about those, should they be needed. This also eliminates a number of inconsistently named local variables.
This commit is contained in:
parent
1cd6eadfbb
commit
e1bb13cd30
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=169269
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@ -55,6 +55,7 @@ __FBSDID("$FreeBSD$");
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#include <sys/mutex.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/rman.h>
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#include <net/bpf.h>
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#include <net/ethernet.h>
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@ -257,10 +258,10 @@ gem_attach(sc)
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/* Get RX FIFO size */
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sc->sc_rxfifosize = 64 *
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bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE);
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bus_read_4(sc->sc_res[0], GEM_RX_FIFO_SIZE);
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/* Get TX FIFO size */
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v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE);
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v = bus_read_4(sc->sc_res[0], GEM_TX_FIFO_SIZE);
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device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n",
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sc->sc_rxfifosize / 1024, v / 16);
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@ -315,7 +316,7 @@ gem_attach(sc)
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#endif
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sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL;
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}
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bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG,
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bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG,
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sc->sc_mif_config);
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/* Attach the interface. */
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ether_ifattach(ifp, sc->sc_enaddr);
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@ -559,7 +560,7 @@ gem_bitwait(sc, r, clr, set)
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u_int32_t reg;
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for (i = TRIES; i--; DELAY(100)) {
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reg = bus_space_read_4(sc->sc_bustag, sc->sc_h, r);
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reg = bus_read_4(sc->sc_res[0], r);
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if ((r & clr) == 0 && (r & set) == set)
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return (1);
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}
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@ -570,8 +571,6 @@ void
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gem_reset(sc)
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struct gem_softc *sc;
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{
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bus_space_tag_t t = sc->sc_bustag;
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bus_space_handle_t h = sc->sc_h;
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#ifdef GEM_DEBUG
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CTR1(KTR_GEM, "%s: gem_reset", device_get_name(sc->sc_dev));
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@ -580,7 +579,7 @@ gem_reset(sc)
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gem_reset_tx(sc);
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/* Do a full reset */
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bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX);
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bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_RX | GEM_RESET_TX);
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if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
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device_printf(sc->sc_dev, "cannot reset device\n");
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}
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@ -668,15 +667,13 @@ int
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gem_reset_rx(sc)
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struct gem_softc *sc;
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{
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bus_space_tag_t t = sc->sc_bustag;
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bus_space_handle_t h = sc->sc_h;
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/*
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* Resetting while DMA is in progress can cause a bus hang, so we
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* disable DMA first.
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*/
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gem_disable_rx(sc);
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bus_space_write_4(t, h, GEM_RX_CONFIG, 0);
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bus_write_4(sc->sc_res[0], GEM_RX_CONFIG, 0);
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/* Wait till it finishes */
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if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0))
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device_printf(sc->sc_dev, "cannot disable read dma\n");
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@ -685,7 +682,7 @@ gem_reset_rx(sc)
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DELAY(5000);
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/* Finally, reset the ERX */
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bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX);
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bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_RX);
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/* Wait till it finishes */
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if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) {
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device_printf(sc->sc_dev, "cannot reset receiver\n");
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@ -702,8 +699,6 @@ static int
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gem_reset_tx(sc)
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struct gem_softc *sc;
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{
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bus_space_tag_t t = sc->sc_bustag;
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bus_space_handle_t h = sc->sc_h;
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int i;
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/*
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@ -711,7 +706,7 @@ gem_reset_tx(sc)
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* disable DMA first.
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*/
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gem_disable_tx(sc);
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bus_space_write_4(t, h, GEM_TX_CONFIG, 0);
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bus_write_4(sc->sc_res[0], GEM_TX_CONFIG, 0);
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/* Wait till it finishes */
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if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0))
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device_printf(sc->sc_dev, "cannot disable read dma\n");
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@ -720,10 +715,10 @@ gem_reset_tx(sc)
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DELAY(5000);
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/* Finally, reset the ETX */
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bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX);
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bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_TX);
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/* Wait till it finishes */
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for (i = TRIES; i--; DELAY(100))
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if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0)
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if ((bus_read_4(sc->sc_res[0], GEM_RESET) & GEM_RESET_TX) == 0)
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break;
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if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) {
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device_printf(sc->sc_dev, "cannot reset receiver\n");
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@ -739,14 +734,12 @@ static int
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gem_disable_rx(sc)
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struct gem_softc *sc;
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{
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bus_space_tag_t t = sc->sc_bustag;
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bus_space_handle_t h = sc->sc_h;
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u_int32_t cfg;
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/* Flip the enable bit */
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cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
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cfg = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
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cfg &= ~GEM_MAC_RX_ENABLE;
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bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg);
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bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, cfg);
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/* Wait for it to finish */
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return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0));
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gem_disable_tx(sc)
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struct gem_softc *sc;
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{
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bus_space_tag_t t = sc->sc_bustag;
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bus_space_handle_t h = sc->sc_h;
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u_int32_t cfg;
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/* Flip the enable bit */
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cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG);
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cfg = bus_read_4(sc->sc_res[0], GEM_MAC_TX_CONFIG);
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cfg &= ~GEM_MAC_TX_ENABLE;
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bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg);
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bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, cfg);
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/* Wait for it to finish */
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return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0));
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@ -882,8 +873,6 @@ gem_init_locked(sc)
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struct gem_softc *sc;
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{
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struct ifnet *ifp = sc->sc_ifp;
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bus_space_tag_t t = sc->sc_bustag;
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bus_space_handle_t h = sc->sc_h;
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u_int32_t v;
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GEM_LOCK_ASSERT(sc, MA_OWNED);
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@ -919,34 +908,34 @@ gem_init_locked(sc)
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/* step 6 & 7. Program Descriptor Ring Base Addresses */
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/* NOTE: we use only 32-bit DMA addresses here. */
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bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0);
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bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
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bus_write_4(sc->sc_res[0], GEM_TX_RING_PTR_HI, 0);
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bus_write_4(sc->sc_res[0], GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
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bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0);
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bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
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bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_HI, 0);
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bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
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#ifdef GEM_DEBUG
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CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx",
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GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma);
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#endif
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/* step 8. Global Configuration & Interrupt Mask */
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bus_space_write_4(t, h, GEM_INTMASK,
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bus_write_4(sc->sc_res[0], GEM_INTMASK,
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~(GEM_INTR_TX_INTME|
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GEM_INTR_TX_EMPTY|
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GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF|
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GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS|
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GEM_INTR_MAC_CONTROL|GEM_INTR_MIF|
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GEM_INTR_BERR));
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bus_space_write_4(t, h, GEM_MAC_RX_MASK,
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bus_write_4(sc->sc_res[0], GEM_MAC_RX_MASK,
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GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT);
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bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */
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bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */
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bus_write_4(sc->sc_res[0], GEM_MAC_TX_MASK, 0xffff); /* XXXX */
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bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_MASK, 0); /* XXXX */
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/* step 9. ETX Configuration: use mostly default values */
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/* Enable DMA */
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v = gem_ringsize(GEM_NTXDESC /*XXX*/);
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bus_space_write_4(t, h, GEM_TX_CONFIG,
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bus_write_4(sc->sc_res[0], GEM_TX_CONFIG,
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v|GEM_TX_CONFIG_TXDMA_EN|
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((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH));
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v = gem_ringsize(GEM_NRXDESC /*XXX*/);
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/* Enable DMA */
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bus_space_write_4(t, h, GEM_RX_CONFIG,
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bus_write_4(sc->sc_res[0], GEM_RX_CONFIG,
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v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)|
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(2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN|
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(0<<GEM_RX_CONFIG_CXM_START_SHFT));
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* The following value is for an OFF Threshold of about 3/4 full
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* and an ON Threshold of 1/4 full.
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*/
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bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH,
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bus_write_4(sc->sc_res[0], GEM_RX_PAUSE_THRESH,
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(3 * sc->sc_rxfifosize / 256) |
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( (sc->sc_rxfifosize / 256) << 12));
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bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6);
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bus_write_4(sc->sc_res[0], GEM_RX_BLANKING, (6<<12)|6);
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/* step 11. Configure Media */
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mii_mediachg(sc->sc_mii);
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/* step 12. RX_MAC Configuration Register */
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v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
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v = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
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v |= GEM_MAC_RX_ENABLE;
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bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
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bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v);
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/* step 14. Issue Transmit Pending command */
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/* step 15. Give the reciever a swift kick */
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bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4);
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bus_write_4(sc->sc_res[0], GEM_RX_KICK, GEM_NRXDESC-4);
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/* Start the one second timer. */
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sc->sc_wdog_timer = 0;
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gem_init_regs(sc)
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struct gem_softc *sc;
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{
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bus_space_tag_t t = sc->sc_bustag;
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bus_space_handle_t h = sc->sc_h;
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const u_char *laddr = IF_LLADDR(sc->sc_ifp);
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u_int32_t v;
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if (!sc->sc_inited) {
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/* Wooo. Magic values. */
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bus_space_write_4(t, h, GEM_MAC_IPG0, 0);
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bus_space_write_4(t, h, GEM_MAC_IPG1, 8);
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bus_space_write_4(t, h, GEM_MAC_IPG2, 4);
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bus_write_4(sc->sc_res[0], GEM_MAC_IPG0, 0);
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bus_write_4(sc->sc_res[0], GEM_MAC_IPG1, 8);
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bus_write_4(sc->sc_res[0], GEM_MAC_IPG2, 4);
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bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
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bus_write_4(sc->sc_res[0], GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
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/* Max frame and max burst size */
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bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
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bus_write_4(sc->sc_res[0], GEM_MAC_MAC_MAX_FRAME,
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(ETHER_MAX_LEN + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) |
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(0x2000 << 16));
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bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7);
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bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4);
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bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10);
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bus_write_4(sc->sc_res[0], GEM_MAC_PREAMBLE_LEN, 0x7);
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bus_write_4(sc->sc_res[0], GEM_MAC_JAM_SIZE, 0x4);
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bus_write_4(sc->sc_res[0], GEM_MAC_ATTEMPT_LIMIT, 0x10);
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/* Dunno.... */
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bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088);
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bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED,
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bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_TYPE, 0x8088);
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bus_write_4(sc->sc_res[0], GEM_MAC_RANDOM_SEED,
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((laddr[5]<<8)|laddr[4])&0x3ff);
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/* Secondary MAC addr set to 0:0:0:0:0:0 */
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bus_space_write_4(t, h, GEM_MAC_ADDR3, 0);
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bus_space_write_4(t, h, GEM_MAC_ADDR4, 0);
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bus_space_write_4(t, h, GEM_MAC_ADDR5, 0);
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bus_write_4(sc->sc_res[0], GEM_MAC_ADDR3, 0);
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bus_write_4(sc->sc_res[0], GEM_MAC_ADDR4, 0);
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bus_write_4(sc->sc_res[0], GEM_MAC_ADDR5, 0);
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/* MAC control addr set to 01:80:c2:00:00:01 */
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bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001);
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bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200);
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bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180);
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bus_write_4(sc->sc_res[0], GEM_MAC_ADDR6, 0x0001);
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bus_write_4(sc->sc_res[0], GEM_MAC_ADDR7, 0xc200);
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bus_write_4(sc->sc_res[0], GEM_MAC_ADDR8, 0x0180);
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/* MAC filter addr set to 0:0:0:0:0:0 */
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bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0);
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bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0);
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bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0);
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bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER0, 0);
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bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER1, 0);
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bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER2, 0);
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bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0);
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bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0);
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bus_write_4(sc->sc_res[0], GEM_MAC_ADR_FLT_MASK1_2, 0);
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bus_write_4(sc->sc_res[0], GEM_MAC_ADR_FLT_MASK0, 0);
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sc->sc_inited = 1;
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}
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/* Counters need to be zeroed */
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bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0);
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bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0);
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bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0);
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bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0);
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bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0);
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bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0);
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bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0);
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bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0);
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bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0);
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bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0);
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bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0);
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bus_write_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT, 0);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT, 0);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT, 0);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_LATE_COLL_CNT, 0);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_DEFER_TMR_CNT, 0);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_PEAK_ATTEMPTS, 0);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_RX_FRAME_COUNT, 0);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_RX_LEN_ERR_CNT, 0);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_RX_ALIGN_ERR, 0);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_RX_CRC_ERR_CNT, 0);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_RX_CODE_VIOL, 0);
|
||||
|
||||
/* Un-pause stuff */
|
||||
#if 0
|
||||
bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
|
||||
#else
|
||||
bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_SEND_PAUSE_CMD, 0);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Set the station address.
|
||||
*/
|
||||
bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]);
|
||||
bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]);
|
||||
bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]);
|
||||
|
||||
/*
|
||||
* Enable MII outputs. Enable GMII if there is a gigabit PHY.
|
||||
*/
|
||||
sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG);
|
||||
sc->sc_mif_config = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
|
||||
v = GEM_MAC_XIF_TX_MII_ENA;
|
||||
if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) {
|
||||
v |= GEM_MAC_XIF_FDPLX_LED;
|
||||
if (sc->sc_flags & GEM_GIGABIT)
|
||||
v |= GEM_MAC_XIF_GMII_MODE;
|
||||
}
|
||||
bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_XIF_CONFIG, v);
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -1204,7 +1191,7 @@ gem_start_locked(ifp)
|
|||
CTR2(KTR_GEM, "%s: gem_start: kicking tx %d",
|
||||
device_get_name(sc->sc_dev), sc->sc_txnext);
|
||||
#endif
|
||||
bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK,
|
||||
bus_write_4(sc->sc_res[0], GEM_TX_KICK,
|
||||
sc->sc_txnext);
|
||||
|
||||
BPF_MTAP(ifp, m0);
|
||||
|
@ -1240,8 +1227,6 @@ gem_tint(sc)
|
|||
struct gem_softc *sc;
|
||||
{
|
||||
struct ifnet *ifp = sc->sc_ifp;
|
||||
bus_space_tag_t t = sc->sc_bustag;
|
||||
bus_space_handle_t mac = sc->sc_h;
|
||||
struct gem_txsoft *txs;
|
||||
int txlast;
|
||||
int progress = 0;
|
||||
|
@ -1255,18 +1240,18 @@ gem_tint(sc)
|
|||
* Unload collision counters
|
||||
*/
|
||||
ifp->if_collisions +=
|
||||
bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) +
|
||||
bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) +
|
||||
bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) +
|
||||
bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT);
|
||||
bus_read_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT) +
|
||||
bus_read_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT) +
|
||||
bus_read_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT) +
|
||||
bus_read_4(sc->sc_res[0], GEM_MAC_LATE_COLL_CNT);
|
||||
|
||||
/*
|
||||
* then clear the hardware counters.
|
||||
*/
|
||||
bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0);
|
||||
bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0);
|
||||
bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0);
|
||||
bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT, 0);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT, 0);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT, 0);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_LATE_COLL_CNT, 0);
|
||||
|
||||
/*
|
||||
* Go through our Tx list and free mbufs for those
|
||||
|
@ -1298,7 +1283,7 @@ gem_tint(sc)
|
|||
* GEM_TX_COMPLETION points to the last descriptor
|
||||
* processed +1.
|
||||
*/
|
||||
txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION);
|
||||
txlast = bus_read_4(sc->sc_res[0], GEM_TX_COMPLETION);
|
||||
#ifdef GEM_DEBUG
|
||||
CTR3(KTR_GEM, "gem_tint: txs->txs_firstdesc = %d, "
|
||||
"txs->txs_lastdesc = %d, txlast = %d",
|
||||
|
@ -1340,12 +1325,12 @@ gem_tint(sc)
|
|||
CTR3(KTR_GEM, "gem_tint: GEM_TX_STATE_MACHINE %x "
|
||||
"GEM_TX_DATA_PTR %llx "
|
||||
"GEM_TX_COMPLETION %x",
|
||||
bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE),
|
||||
((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h,
|
||||
bus_read_4(sc->sc_res[0], GEM_TX_STATE_MACHINE),
|
||||
((long long) bus_read_4(sc->sc_res[0],
|
||||
GEM_TX_DATA_PTR_HI) << 32) |
|
||||
bus_space_read_4(sc->sc_bustag, sc->sc_h,
|
||||
bus_read_4(sc->sc_res[0],
|
||||
GEM_TX_DATA_PTR_LO),
|
||||
bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION));
|
||||
bus_read_4(sc->sc_res[0], GEM_TX_COMPLETION));
|
||||
#endif
|
||||
|
||||
if (progress) {
|
||||
|
@ -1385,8 +1370,6 @@ gem_rint(sc)
|
|||
struct gem_softc *sc;
|
||||
{
|
||||
struct ifnet *ifp = sc->sc_ifp;
|
||||
bus_space_tag_t t = sc->sc_bustag;
|
||||
bus_space_handle_t h = sc->sc_h;
|
||||
struct gem_rxsoft *rxs;
|
||||
struct mbuf *m;
|
||||
u_int64_t rxstat;
|
||||
|
@ -1404,7 +1387,7 @@ gem_rint(sc)
|
|||
* Read the completion register once. This limits
|
||||
* how long the following loop can execute.
|
||||
*/
|
||||
rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION);
|
||||
rxcomp = bus_read_4(sc->sc_res[0], GEM_RX_COMPLETION);
|
||||
|
||||
#ifdef GEM_DEBUG
|
||||
CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d",
|
||||
|
@ -1488,12 +1471,12 @@ gem_rint(sc)
|
|||
device_printf(sc->sc_dev, "rint: ring wrap\n");
|
||||
}
|
||||
sc->sc_rxptr = i;
|
||||
bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i));
|
||||
bus_write_4(sc->sc_res[0], GEM_RX_KICK, GEM_PREVRX(i));
|
||||
}
|
||||
|
||||
#ifdef GEM_DEBUG
|
||||
CTR2(KTR_GEM, "gem_rint: done sc->rxptr %d, complete %d",
|
||||
sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION));
|
||||
sc->sc_rxptr, bus_read_4(sc->sc_res[0], GEM_RX_COMPLETION));
|
||||
#endif
|
||||
}
|
||||
|
||||
|
@ -1571,12 +1554,10 @@ gem_intr(v)
|
|||
void *v;
|
||||
{
|
||||
struct gem_softc *sc = (struct gem_softc *)v;
|
||||
bus_space_tag_t t = sc->sc_bustag;
|
||||
bus_space_handle_t seb = sc->sc_h;
|
||||
u_int32_t status;
|
||||
|
||||
GEM_LOCK(sc);
|
||||
status = bus_space_read_4(t, seb, GEM_STATUS);
|
||||
status = bus_read_4(sc->sc_res[0], GEM_STATUS);
|
||||
#ifdef GEM_DEBUG
|
||||
CTR3(KTR_GEM, "%s: gem_intr: cplt %x, status %x",
|
||||
device_get_name(sc->sc_dev), (status>>19),
|
||||
|
@ -1594,7 +1575,7 @@ gem_intr(v)
|
|||
|
||||
/* We should eventually do more than just print out error stats. */
|
||||
if (status & GEM_INTR_TX_MAC) {
|
||||
int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS);
|
||||
int txstat = bus_read_4(sc->sc_res[0], GEM_MAC_TX_STATUS);
|
||||
if (txstat & ~GEM_MAC_TX_XMIT_DONE)
|
||||
device_printf(sc->sc_dev, "MAC tx fault, status %x\n",
|
||||
txstat);
|
||||
|
@ -1602,7 +1583,7 @@ gem_intr(v)
|
|||
gem_init_locked(sc);
|
||||
}
|
||||
if (status & GEM_INTR_RX_MAC) {
|
||||
int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS);
|
||||
int rxstat = bus_read_4(sc->sc_res[0], GEM_MAC_RX_STATUS);
|
||||
/*
|
||||
* On some chip revisions GEM_MAC_RX_OVERFLOW happen often
|
||||
* due to a silicon bug so handle them silently.
|
||||
|
@ -1626,14 +1607,14 @@ gem_watchdog(sc)
|
|||
#ifdef GEM_DEBUG
|
||||
CTR3(KTR_GEM, "gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x "
|
||||
"GEM_MAC_RX_CONFIG %x",
|
||||
bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG),
|
||||
bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS),
|
||||
bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG));
|
||||
bus_read_4(sc->sc_res[0], GEM_RX_CONFIG),
|
||||
bus_read_4(sc->sc_res[0], GEM_MAC_RX_STATUS),
|
||||
bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG));
|
||||
CTR3(KTR_GEM, "gem_watchdog: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x "
|
||||
"GEM_MAC_TX_CONFIG %x",
|
||||
bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_CONFIG),
|
||||
bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_STATUS),
|
||||
bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_CONFIG));
|
||||
bus_read_4(sc->sc_res[0], GEM_TX_CONFIG),
|
||||
bus_read_4(sc->sc_res[0], GEM_MAC_TX_STATUS),
|
||||
bus_read_4(sc->sc_res[0], GEM_MAC_TX_CONFIG));
|
||||
#endif
|
||||
|
||||
if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0)
|
||||
|
@ -1654,13 +1635,11 @@ static void
|
|||
gem_mifinit(sc)
|
||||
struct gem_softc *sc;
|
||||
{
|
||||
bus_space_tag_t t = sc->sc_bustag;
|
||||
bus_space_handle_t mif = sc->sc_h;
|
||||
|
||||
/* Configure the MIF in frame mode */
|
||||
sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
|
||||
sc->sc_mif_config = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
|
||||
sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA;
|
||||
bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config);
|
||||
bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, sc->sc_mif_config);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -1683,8 +1662,6 @@ gem_mii_readreg(dev, phy, reg)
|
|||
int phy, reg;
|
||||
{
|
||||
struct gem_softc *sc = device_get_softc(dev);
|
||||
bus_space_tag_t t = sc->sc_bustag;
|
||||
bus_space_handle_t mif = sc->sc_h;
|
||||
int n;
|
||||
u_int32_t v;
|
||||
|
||||
|
@ -1694,23 +1671,23 @@ gem_mii_readreg(dev, phy, reg)
|
|||
|
||||
#if 0
|
||||
/* Select the desired PHY in the MIF configuration register */
|
||||
v = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
|
||||
v = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
|
||||
/* Clear PHY select bit */
|
||||
v &= ~GEM_MIF_CONFIG_PHY_SEL;
|
||||
if (phy == GEM_PHYAD_EXTERNAL)
|
||||
/* Set PHY select bit to get at external device */
|
||||
v |= GEM_MIF_CONFIG_PHY_SEL;
|
||||
bus_space_write_4(t, mif, GEM_MIF_CONFIG, v);
|
||||
bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, v);
|
||||
#endif
|
||||
|
||||
/* Construct the frame command */
|
||||
v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) |
|
||||
GEM_MIF_FRAME_READ;
|
||||
|
||||
bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
|
||||
bus_write_4(sc->sc_res[0], GEM_MIF_FRAME, v);
|
||||
for (n = 0; n < 100; n++) {
|
||||
DELAY(1);
|
||||
v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
|
||||
v = bus_read_4(sc->sc_res[0], GEM_MIF_FRAME);
|
||||
if (v & GEM_MIF_FRAME_TA0)
|
||||
return (v & GEM_MIF_FRAME_DATA);
|
||||
}
|
||||
|
@ -1725,8 +1702,6 @@ gem_mii_writereg(dev, phy, reg, val)
|
|||
int phy, reg, val;
|
||||
{
|
||||
struct gem_softc *sc = device_get_softc(dev);
|
||||
bus_space_tag_t t = sc->sc_bustag;
|
||||
bus_space_handle_t mif = sc->sc_h;
|
||||
int n;
|
||||
u_int32_t v;
|
||||
|
||||
|
@ -1736,13 +1711,13 @@ gem_mii_writereg(dev, phy, reg, val)
|
|||
|
||||
#if 0
|
||||
/* Select the desired PHY in the MIF configuration register */
|
||||
v = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
|
||||
v = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
|
||||
/* Clear PHY select bit */
|
||||
v &= ~GEM_MIF_CONFIG_PHY_SEL;
|
||||
if (phy == GEM_PHYAD_EXTERNAL)
|
||||
/* Set PHY select bit to get at external device */
|
||||
v |= GEM_MIF_CONFIG_PHY_SEL;
|
||||
bus_space_write_4(t, mif, GEM_MIF_CONFIG, v);
|
||||
bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, v);
|
||||
#endif
|
||||
/* Construct the frame command */
|
||||
v = GEM_MIF_FRAME_WRITE |
|
||||
|
@ -1750,10 +1725,10 @@ gem_mii_writereg(dev, phy, reg, val)
|
|||
(reg << GEM_MIF_REG_SHIFT) |
|
||||
(val & GEM_MIF_FRAME_DATA);
|
||||
|
||||
bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
|
||||
bus_write_4(sc->sc_res[0], GEM_MIF_FRAME, v);
|
||||
for (n = 0; n < 100; n++) {
|
||||
DELAY(1);
|
||||
v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
|
||||
v = bus_read_4(sc->sc_res[0], GEM_MIF_FRAME);
|
||||
if (v & GEM_MIF_FRAME_TA0)
|
||||
return (1);
|
||||
}
|
||||
|
@ -1770,8 +1745,6 @@ gem_mii_statchg(dev)
|
|||
#ifdef GEM_DEBUG
|
||||
int instance;
|
||||
#endif
|
||||
bus_space_tag_t t = sc->sc_bustag;
|
||||
bus_space_handle_t mac = sc->sc_h;
|
||||
u_int32_t v;
|
||||
|
||||
#ifdef GEM_DEBUG
|
||||
|
@ -1782,21 +1755,21 @@ gem_mii_statchg(dev)
|
|||
#endif
|
||||
|
||||
/* Set tx full duplex options */
|
||||
bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, 0);
|
||||
DELAY(10000); /* reg must be cleared and delay before changing. */
|
||||
v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT|
|
||||
GEM_MAC_TX_ENABLE;
|
||||
if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) {
|
||||
v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS;
|
||||
}
|
||||
bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, v);
|
||||
|
||||
/* XIF Configuration */
|
||||
v = GEM_MAC_XIF_LINK_LED;
|
||||
v |= GEM_MAC_XIF_TX_MII_ENA;
|
||||
|
||||
/* If an external transceiver is connected, enable its MII drivers */
|
||||
sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG);
|
||||
sc->sc_mif_config = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
|
||||
if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) {
|
||||
/* External MII needs echo disable if half duplex. */
|
||||
if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
|
||||
|
@ -1814,7 +1787,7 @@ gem_mii_statchg(dev)
|
|||
/* Internal MII needs buf enable */
|
||||
v |= GEM_MAC_XIF_MII_BUF_ENA;
|
||||
}
|
||||
bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_XIF_CONFIG, v);
|
||||
}
|
||||
|
||||
int
|
||||
|
@ -1911,8 +1884,6 @@ gem_setladrf(sc)
|
|||
{
|
||||
struct ifnet *ifp = sc->sc_ifp;
|
||||
struct ifmultiaddr *inm;
|
||||
bus_space_tag_t t = sc->sc_bustag;
|
||||
bus_space_handle_t h = sc->sc_h;
|
||||
u_int32_t crc;
|
||||
u_int32_t hash[16];
|
||||
u_int32_t v;
|
||||
|
@ -1921,7 +1892,7 @@ gem_setladrf(sc)
|
|||
GEM_LOCK_ASSERT(sc, MA_OWNED);
|
||||
|
||||
/* Get current RX configuration */
|
||||
v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
|
||||
v = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
|
||||
|
||||
/*
|
||||
* Turn off promiscuous mode, promiscuous group mode (all multicast),
|
||||
|
@ -1974,11 +1945,11 @@ gem_setladrf(sc)
|
|||
|
||||
/* Now load the hash table into the chip (if we are using it) */
|
||||
for (i = 0; i < 16; i++) {
|
||||
bus_space_write_4(t, h,
|
||||
bus_write_4(sc->sc_res[0],
|
||||
GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0),
|
||||
hash[i]);
|
||||
}
|
||||
|
||||
chipit:
|
||||
bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
|
||||
bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v);
|
||||
}
|
||||
|
|
|
@ -72,15 +72,6 @@ __FBSDID("$FreeBSD$");
|
|||
|
||||
#include "miibus_if.h"
|
||||
|
||||
struct gem_pci_softc {
|
||||
struct gem_softc gsc_gem; /* GEM device */
|
||||
struct resource *gsc_sres;
|
||||
int gsc_srid;
|
||||
struct resource *gsc_ires;
|
||||
int gsc_irid;
|
||||
void *gsc_ih;
|
||||
};
|
||||
|
||||
static int gem_pci_probe(device_t);
|
||||
static int gem_pci_attach(device_t);
|
||||
static int gem_pci_detach(device_t);
|
||||
|
@ -112,7 +103,7 @@ static device_method_t gem_pci_methods[] = {
|
|||
static driver_t gem_pci_driver = {
|
||||
"gem",
|
||||
gem_pci_methods,
|
||||
sizeof(struct gem_pci_softc)
|
||||
sizeof(struct gem_softc)
|
||||
};
|
||||
|
||||
|
||||
|
@ -142,15 +133,14 @@ gem_pci_probe(dev)
|
|||
{
|
||||
int i;
|
||||
u_int32_t devid;
|
||||
struct gem_pci_softc *gsc;
|
||||
struct gem_softc *sc;
|
||||
|
||||
devid = pci_get_devid(dev);
|
||||
for (i = 0; gem_pci_devlist[i].gpd_desc != NULL; i++) {
|
||||
if (devid == gem_pci_devlist[i].gpd_devid) {
|
||||
device_set_desc(dev, gem_pci_devlist[i].gpd_desc);
|
||||
gsc = device_get_softc(dev);
|
||||
gsc->gsc_gem.sc_variant =
|
||||
gem_pci_devlist[i].gpd_variant;
|
||||
sc = device_get_softc(dev);
|
||||
sc->sc_variant = gem_pci_devlist[i].gpd_variant;
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
}
|
||||
|
@ -158,12 +148,17 @@ gem_pci_probe(dev)
|
|||
return (ENXIO);
|
||||
}
|
||||
|
||||
static struct resource_spec gem_pci_res_spec[] = {
|
||||
{ SYS_RES_MEMORY, PCI_GEM_BASEADDR, RF_ACTIVE },
|
||||
{ SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE },
|
||||
{ -1, 0 }
|
||||
};
|
||||
|
||||
static int
|
||||
gem_pci_attach(dev)
|
||||
device_t dev;
|
||||
{
|
||||
struct gem_pci_softc *gsc = device_get_softc(dev);
|
||||
struct gem_softc *sc = &gsc->gsc_gem;
|
||||
struct gem_softc *sc = device_get_softc(dev);
|
||||
|
||||
pci_enable_busmaster(dev);
|
||||
|
||||
|
@ -177,27 +172,14 @@ gem_pci_attach(dev)
|
|||
sc->sc_dev = dev;
|
||||
sc->sc_pci = 1; /* XXX */
|
||||
|
||||
if (bus_alloc_resources(dev, gem_pci_res_spec, sc->sc_res)) {
|
||||
device_printf(dev, "failed to allocate resources\n");
|
||||
bus_release_resources(dev, gem_pci_res_spec, sc->sc_res);
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
GEM_LOCK_INIT(sc, device_get_nameunit(dev));
|
||||
|
||||
gsc->gsc_srid = PCI_GEM_BASEADDR;
|
||||
gsc->gsc_sres = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
||||
&gsc->gsc_srid, RF_ACTIVE);
|
||||
if (gsc->gsc_sres == NULL) {
|
||||
device_printf(dev, "failed to allocate bus space resource\n");
|
||||
goto fail_mtx;
|
||||
}
|
||||
|
||||
gsc->gsc_irid = 0;
|
||||
gsc->gsc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ,
|
||||
&gsc->gsc_irid, RF_SHAREABLE | RF_ACTIVE);
|
||||
if (gsc->gsc_ires == NULL) {
|
||||
device_printf(dev, "failed to allocate interrupt resource\n");
|
||||
goto fail_sres;
|
||||
}
|
||||
|
||||
sc->sc_bustag = rman_get_bustag(gsc->gsc_sres);
|
||||
sc->sc_h = rman_get_bushandle(gsc->gsc_sres);
|
||||
|
||||
/* All platform that this driver is used on must provide this. */
|
||||
OF_getetheraddr(dev, sc->sc_enaddr);
|
||||
|
||||
|
@ -206,22 +188,19 @@ gem_pci_attach(dev)
|
|||
*/
|
||||
if (gem_attach(sc) != 0) {
|
||||
device_printf(dev, "could not be configured\n");
|
||||
goto fail_ires;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
if (bus_setup_intr(dev, gsc->gsc_ires, INTR_TYPE_NET | INTR_MPSAFE,
|
||||
NULL, gem_intr, sc, &gsc->gsc_ih) != 0) {
|
||||
if (bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE,
|
||||
NULL, gem_intr, sc, &sc->sc_ih) != 0) {
|
||||
device_printf(dev, "failed to set up interrupt\n");
|
||||
gem_detach(sc);
|
||||
goto fail_ires;
|
||||
goto fail;
|
||||
}
|
||||
return (0);
|
||||
|
||||
fail_ires:
|
||||
bus_release_resource(dev, SYS_RES_IRQ, gsc->gsc_irid, gsc->gsc_ires);
|
||||
fail_sres:
|
||||
bus_release_resource(dev, SYS_RES_MEMORY, gsc->gsc_srid, gsc->gsc_sres);
|
||||
fail_mtx:
|
||||
fail:
|
||||
bus_release_resources(dev, gem_pci_res_spec, sc->sc_res);
|
||||
GEM_LOCK_DESTROY(sc);
|
||||
return (ENXIO);
|
||||
}
|
||||
|
@ -230,14 +209,12 @@ static int
|
|||
gem_pci_detach(dev)
|
||||
device_t dev;
|
||||
{
|
||||
struct gem_pci_softc *gsc = device_get_softc(dev);
|
||||
struct gem_softc *sc = &gsc->gsc_gem;
|
||||
struct gem_softc *sc = device_get_softc(dev);
|
||||
|
||||
bus_teardown_intr(dev, gsc->gsc_ires, gsc->gsc_ih);
|
||||
bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih);
|
||||
gem_detach(sc);
|
||||
bus_release_resource(dev, SYS_RES_IRQ, gsc->gsc_irid, gsc->gsc_ires);
|
||||
bus_release_resource(dev, SYS_RES_MEMORY, gsc->gsc_srid, gsc->gsc_sres);
|
||||
GEM_LOCK_DESTROY(sc);
|
||||
bus_release_resources(dev, gem_pci_res_spec, sc->sc_res);
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
@ -245,8 +222,7 @@ static int
|
|||
gem_pci_suspend(dev)
|
||||
device_t dev;
|
||||
{
|
||||
struct gem_pci_softc *gsc = device_get_softc(dev);
|
||||
struct gem_softc *sc = &gsc->gsc_gem;
|
||||
struct gem_softc *sc = device_get_softc(dev);
|
||||
|
||||
gem_suspend(sc);
|
||||
return (0);
|
||||
|
@ -256,8 +232,7 @@ static int
|
|||
gem_pci_resume(dev)
|
||||
device_t dev;
|
||||
{
|
||||
struct gem_pci_softc *gsc = device_get_softc(dev);
|
||||
struct gem_softc *sc = &gsc->gsc_gem;
|
||||
struct gem_softc *sc = device_get_softc(dev);
|
||||
|
||||
gem_resume(sc);
|
||||
return (0);
|
||||
|
|
|
@ -133,13 +133,13 @@ struct gem_softc {
|
|||
int sc_wdog_timer; /* watchdog timer */
|
||||
|
||||
/* The following bus handles are to be provided by the bus front-end */
|
||||
bus_space_tag_t sc_bustag; /* bus tag */
|
||||
void *sc_ih;
|
||||
struct resource *sc_res[2];
|
||||
bus_dma_tag_t sc_pdmatag; /* parent bus dma tag */
|
||||
bus_dma_tag_t sc_rdmatag; /* RX bus dma tag */
|
||||
bus_dma_tag_t sc_tdmatag; /* TX bus dma tag */
|
||||
bus_dma_tag_t sc_cdmatag; /* control data bus dma tag */
|
||||
bus_dmamap_t sc_dmamap; /* bus dma handle */
|
||||
bus_space_handle_t sc_h; /* bus space handle for all regs */
|
||||
|
||||
int sc_phys[2]; /* MII instance -> PHY map */
|
||||
|
||||
|
|
Loading…
Reference in a new issue