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Eliminate flushing of L2 cache in ARM context switch routines.

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With VIPT L2 cache such syncing not only is redundant, but also a performance
penalty.

Pointed out by:	cognet
This commit is contained in:
Rafal Jaworowski 2008-10-16 19:06:24 +00:00
parent ee81baecd8
commit df38b76405
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=183958
1 changed files with 0 additions and 8 deletions
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8
sys/arm/arm/swtch.S
View file

@ -143,8 +143,6 @@ ENTRY(cpu_throw)
ldr r9, .Lcpufuncs
mov lr, pc
ldr pc, [r9, #CF_IDCACHE_WBINV_ALL]
mov lr, pc
ldr pc, [r9, #CF_L2CACHE_WBINV_ALL]
ldr r0, [r7, #(PCB_PL1VEC)]
ldr r1, [r7, #(PCB_DACR)]
/*
@ -174,8 +172,6 @@ ENTRY(cpu_throw)
movne r1, #4
movne lr, pc
ldrne pc, [r9, #CF_DCACHE_WB_RANGE]
movne lr, pc
ldrne pc, [r9, #CF_L2CACHE_WB_RANGE]
#endif /* PMAP_INCLUDE_PTE_SYNC */
/*
@ -332,8 +328,6 @@ ENTRY(cpu_switch)
ldr r1, .Lcpufuncs
mov lr, pc
ldr pc, [r1, #CF_IDCACHE_WBINV_ALL]
mov lr, pc
ldr pc, [r1, #CF_L2CACHE_WBINV_ALL]
.Lcs_cache_purge_skipped:
/* rem: r6 = lock */
/* rem: r9 = new PCB */
@ -366,8 +360,6 @@ ENTRY(cpu_switch)
mov r1, #4
mov lr, pc
ldr pc, [r2, #CF_DCACHE_WB_RANGE]
mov lr, pc
ldr pc, [r2, #CF_L2CACHE_WB_RANGE]
.Lcs_same_vector:
#endif /* PMAP_INCLUDE_PTE_SYNC */