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Eliminate flushing of L2 cache in ARM context switch routines.
With VIPT L2 cache such syncing not only is redundant, but also a performance penalty. Pointed out by: cognet
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parent
ee81baecd8
commit
df38b76405
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=183958
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@ -143,8 +143,6 @@ ENTRY(cpu_throw)
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ldr r9, .Lcpufuncs
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mov lr, pc
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ldr pc, [r9, #CF_IDCACHE_WBINV_ALL]
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mov lr, pc
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ldr pc, [r9, #CF_L2CACHE_WBINV_ALL]
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ldr r0, [r7, #(PCB_PL1VEC)]
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ldr r1, [r7, #(PCB_DACR)]
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/*
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@ -174,8 +172,6 @@ ENTRY(cpu_throw)
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movne r1, #4
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movne lr, pc
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ldrne pc, [r9, #CF_DCACHE_WB_RANGE]
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movne lr, pc
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ldrne pc, [r9, #CF_L2CACHE_WB_RANGE]
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#endif /* PMAP_INCLUDE_PTE_SYNC */
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/*
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@ -332,8 +328,6 @@ ENTRY(cpu_switch)
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ldr r1, .Lcpufuncs
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mov lr, pc
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ldr pc, [r1, #CF_IDCACHE_WBINV_ALL]
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mov lr, pc
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ldr pc, [r1, #CF_L2CACHE_WBINV_ALL]
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.Lcs_cache_purge_skipped:
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/* rem: r6 = lock */
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/* rem: r9 = new PCB */
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@ -366,8 +360,6 @@ ENTRY(cpu_switch)
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mov r1, #4
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mov lr, pc
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ldr pc, [r2, #CF_DCACHE_WB_RANGE]
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mov lr, pc
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ldr pc, [r2, #CF_L2CACHE_WB_RANGE]
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.Lcs_same_vector:
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#endif /* PMAP_INCLUDE_PTE_SYNC */
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