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riscv: Fix SSTC extension support

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From the SSTC spec:
"If the stimecmp (supervisor-mode timer compare) register is implemented,
then STIP is read-only in mip and reflects the supervisor-level timer
interrupt signal resulting from stimecmp. This timer interrupt signal
is cleared by writing stimecmp with a value greater than the current time
value."

This fixes operation in Spike with sstc extension enabled.
Example:
  spike --isa RV64IMAFDCH_zicntr_zihpm_sstc

Reviewed by:	mhorne
Differential Revision:	https://reviews.freebsd.org/D45226
This commit is contained in:
Ruslan Bukin 2024-05-22 15:51:45 +01:00
parent bea2bf458d
commit ddd0d4f4cd
1 changed files with 5 additions and 2 deletions
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7
sys/riscv/riscv/timer.c
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@ -1,5 +1,5 @@
/*-
* Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com>
* Copyright (c) 2015-2024 Ruslan Bukin <br@bsdpad.com>
* All rights reserved.
*
* Portions of this software were developed by SRI International and the
@ -143,7 +143,10 @@ riscv_timer_intr(void *arg)
sc = (struct riscv_timer_softc *)arg;
csr_clear(sip, SIP_STIP);
if (has_sstc)
csr_write(stimecmp, -1UL);
else
csr_clear(sip, SIP_STIP);
if (sc->et.et_active)
sc->et.et_event_cb(&sc->et, sc->et.et_arg);