mirror of
https://github.com/freebsd/freebsd-src
synced 2024-09-29 13:15:05 +00:00
Very preliminary pcic device support. Will make depend, but won't
(yet) compile and link. Renamed pcic back to pcic from pcicx, but conditionalize its inclusion on pccard being included also. card is the old and pccard is the new, which is a handy way to have both in the tree at the same time. Obtained from: newconfig project More to follow...
This commit is contained in:
Warner Losh
parent
05c30f03e6
commit
dc781fe4ff
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=52528
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@ -174,6 +174,9 @@ dev/mlx/mlx.c optional mlx
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dev/pccard/pccard.c optional pccard
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dev/pccard/pccard_cis.c optional pccard
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dev/pccard/pccard_cis_quirks.c optional pccard
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dev/pcic/i82365.c optional pcic pccard
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dev/pcic/i82365_isa.c optional pcic pccard
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dev/pcic/i82365_isasubr.c optional pcic pccard
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dev/pdq/pdq.c optional fea
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dev/pdq/pdq_ifsubr.c optional fea
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dev/pdq/pdq.c optional fpa
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@ -305,7 +308,6 @@ i4b/layer4/i4b_i4bdrv.c optional i4b
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i4b/layer4/i4b_l4.c optional i4b
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i4b/layer4/i4b_l4mgmt.c optional i4b
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i4b/layer4/i4b_l4timer.c optional i4b
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isa/pcicx.c optional pcicx pccard
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isofs/cd9660/cd9660_bmap.c optional cd9660
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isofs/cd9660/cd9660_lookup.c optional cd9660
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isofs/cd9660/cd9660_node.c optional cd9660
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1358
sys/dev/pcic/i82365.c
Normal file
1358
sys/dev/pcic/i82365.c
Normal file
File diff suppressed because it is too large
Load diff
262
sys/dev/pcic/i82365_isa.c
Normal file
262
sys/dev/pcic/i82365_isa.c
Normal file
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@ -0,0 +1,262 @@
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/* $NetBSD: i82365_isa.c,v 1.11 1998/06/09 07:25:00 thorpej Exp $ */
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/* $FreeBSD$ */
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#define PCICISADEBUG
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/*
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* Copyright (c) 1997 Marc Horowitz. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Marc Horowitz.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/kernel.h>
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#include <sys/queue.h>
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#include <sys/types.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <machine/resource.h>
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#ifdef __FreeBSD__
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#include <i386/isa/isa_device.h>
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typedef int isa_chipset_tag_t;
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#define ia_msize ia_memsize
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#define delay(x) DELAY(x)
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#else
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#include <dev/isa/isareg.h>
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#include <dev/isa/isavar.h>
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#endif
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#include <dev/pccard/pccardreg.h>
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#include <dev/pccard/pccardvar.h>
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#include <dev/pccard/pccardchip.h>
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#include <dev/pcic/i82365reg.h>
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#include <dev/pcic/i82365var.h>
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#include <dev/pcic/i82365_isavar.h>
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#ifdef PCICISADEBUG
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int pcicisa_debug = 0 /* XXX */ ;
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#define DPRINTF(arg) if (pcicisa_debug) printf arg;
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#else
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#define DPRINTF(arg)
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#endif
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int pcic_isa_probe __P((struct device *, struct cfdata *, void *));
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void pcic_isa_attach __P((struct device *, struct device *, void *));
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void *pcic_isa_chip_intr_establish __P((pccard_chipset_handle_t,
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struct pccard_function *, int, int (*) (void *), void *));
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void pcic_isa_chip_intr_disestablish __P((pccard_chipset_handle_t, void *));
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#ifdef __FreeBSD__
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struct cfattach pcic_isa_ca = {
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sizeof(struct pcic_softc), pcic_isa_probe, pcic_isa_attach
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};
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#else
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struct cfattach pcic_isa_ca = {
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sizeof(struct pcic_softc), pcic_isa_probe, pcic_isa_attach
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};
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#endif
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static struct pccard_chip_functions pcic_isa_functions = {
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pcic_chip_mem_alloc,
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pcic_chip_mem_free,
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pcic_chip_mem_map,
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pcic_chip_mem_unmap,
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pcic_chip_io_alloc,
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pcic_chip_io_free,
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pcic_chip_io_map,
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pcic_chip_io_unmap,
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pcic_isa_chip_intr_establish,
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pcic_isa_chip_intr_disestablish,
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pcic_chip_socket_enable,
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pcic_chip_socket_disable,
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};
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int
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pcic_isa_probe(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct isa_attach_args *ia = aux;
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bus_space_tag_t iot = ia->ia_iot;
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bus_space_handle_t ioh, memh;
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int val, found;
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/* Disallow wildcarded i/o address. */
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#ifdef __FreeBSD__
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if (ia->ia_iobase == ISACF_IOBASE_DEFAULT)
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#else
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if (ia->ia_iobase == ISACF_PORT_DEFAULT)
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#endif
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return (0);
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if (bus_space_map(iot, ia->ia_iobase, PCIC_IOSIZE, 0, &ioh))
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return (0);
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if (ia->ia_msize == -1)
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ia->ia_msize = PCIC_MEMSIZE;
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#ifdef __FreeBSD__
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if (bus_space_map(ia->ia_memt, kvtop(ia->ia_membase), ia->ia_msize, 0, &memh))
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#else
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if (bus_space_map(ia->ia_memt, ia->ia_maddr, ia->ia_msize, 0, &memh))
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#endif
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return (0);
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found = 0;
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/*
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* this could be done with a loop, but it would violate the
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* abstraction
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*/
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bus_space_write_1(iot, ioh, PCIC_REG_INDEX, C0SA + PCIC_IDENT);
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val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
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if (pcic_ident_ok(val))
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found++;
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bus_space_write_1(iot, ioh, PCIC_REG_INDEX, C0SB + PCIC_IDENT);
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val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
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if (pcic_ident_ok(val))
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found++;
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bus_space_write_1(iot, ioh, PCIC_REG_INDEX, C1SA + PCIC_IDENT);
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val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
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if (pcic_ident_ok(val))
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found++;
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bus_space_write_1(iot, ioh, PCIC_REG_INDEX, C1SB + PCIC_IDENT);
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val = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
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if (pcic_ident_ok(val))
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found++;
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bus_space_unmap(iot, ioh, PCIC_IOSIZE);
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bus_space_unmap(ia->ia_memt, memh, ia->ia_msize);
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if (!found)
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return (0);
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ia->ia_iosize = PCIC_IOSIZE;
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return (1);
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}
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void
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pcic_isa_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct pcic_softc *sc = (void *) self;
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struct isa_attach_args *ia = aux;
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isa_chipset_tag_t ic = ia->ia_ic;
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bus_space_tag_t iot = ia->ia_iot;
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bus_space_tag_t memt = ia->ia_memt;
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bus_space_handle_t ioh;
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bus_space_handle_t memh;
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/* Map i/o space. */
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if (bus_space_map(iot, ia->ia_iobase, ia->ia_iosize, 0, &ioh)) {
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printf(": can't map i/o space\n");
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return;
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}
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/* Map mem space. */
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#ifdef __FreeBSD__
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if (bus_space_map(memt, kvtop(ia->ia_membase), ia->ia_memsize, 0, &memh)) {
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#else
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if (bus_space_map(memt, ia->ia_maddr, ia->ia_msize, 0, &memh)) {
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#endif
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printf(": can't map mem space\n");
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return;
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}
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#ifdef __FreeBSD__
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sc->membase = kvtop(ia->ia_membase);
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#else
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sc->membase = ia->ia_maddr;
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#endif
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sc->subregionmask = (1 << (ia->ia_msize / PCIC_MEM_PAGESIZE)) - 1;
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sc->intr_est = ic;
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sc->pct = (pccard_chipset_tag_t) & pcic_isa_functions;
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sc->iot = iot;
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sc->ioh = ioh;
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sc->memt = memt;
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sc->memh = memh;
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/*
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* allocate an irq. it will be used by both controllers. I could
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* use two different interrupts, but interrupts are relatively
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* scarce, shareable, and for PCIC controllers, very infrequent.
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*/
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if ((sc->irq = ia->ia_irq) == IRQUNK) {
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if (isa_intr_alloc(ic,
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PCIC_CSC_INTR_IRQ_VALIDMASK & pcic_isa_intr_alloc_mask,
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IST_EDGE, &sc->irq)) {
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printf("\n%s: can't allocate interrupt\n",
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sc->dev.dv_xname);
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return;
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}
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printf(": using irq %d", sc->irq);
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}
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printf("\n");
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pcic_attach(sc);
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pcic_isa_bus_width_probe (sc, iot, ioh, ia->ia_iobase, ia->ia_iosize);
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sc->ih = isa_intr_establish(ic, sc->irq, IST_EDGE, IPL_TTY,
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pcic_intr, sc);
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if (sc->ih == NULL) {
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printf("%s: can't establish interrupt\n", sc->dev.dv_xname);
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return;
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}
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pcic_attach_sockets(sc);
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}
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278
sys/dev/pcic/i82365_isasubr.c
Normal file
278
sys/dev/pcic/i82365_isasubr.c
Normal file
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@ -0,0 +1,278 @@
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/* $NetBSD: i82365_isasubr.c,v 1.1 1998/06/07 18:28:31 sommerfe Exp $ */
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/* $FreeBSD$ */
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#define PCICISADEBUG
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/*
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* Copyright (c) 1998 Bill Sommerfeld. All rights reserved.
|
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* Copyright (c) 1997 Marc Horowitz. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Marc Horowitz.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/queue.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include <sys/bus.h>
|
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#include <machine/bus.h>
|
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#include <sys/rman.h>
|
||||
#include <machine/resource.h>
|
||||
#include <vm/vm.h>
|
||||
|
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#ifdef __FreeBSD__
|
||||
#include <i386/isa/isa_device.h>
|
||||
typedef int isa_chipset_tag_t;
|
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#define delay(x) DELAY(x)
|
||||
#else
|
||||
#include <dev/isa/isareg.h>
|
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#include <dev/isa/isavar.h>
|
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#endif
|
||||
|
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#include <dev/pccard/pccardreg.h>
|
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#include <dev/pccard/pccardvar.h>
|
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#include <dev/pccard/pccardchip.h>
|
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|
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#include <dev/pcic/i82365reg.h>
|
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#include <dev/pcic/i82365var.h>
|
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#include <dev/pcic/i82365_isavar.h>
|
||||
|
||||
/*****************************************************************************
|
||||
* Configurable parameters.
|
||||
*****************************************************************************/
|
||||
|
||||
#if 0
|
||||
#include "opt_pcic_isa_alloc_iobase.h"
|
||||
#include "opt_pcic_isa_alloc_iosize.h"
|
||||
#include "opt_pcic_isa_intr_alloc_mask.h"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Default I/O allocation range. If both are set to non-zero, these
|
||||
* values will be used instead. Otherwise, the code attempts to probe
|
||||
* the bus width. Systems with 10 address bits should use 0x300 and 0xff.
|
||||
* Systems with 12 address bits (most) should use 0x400 and 0xbff.
|
||||
*/
|
||||
|
||||
#ifndef PCIC_ISA_ALLOC_IOBASE
|
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#define PCIC_ISA_ALLOC_IOBASE 0
|
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#endif
|
||||
|
||||
#ifndef PCIC_ISA_ALLOC_IOSIZE
|
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#define PCIC_ISA_ALLOC_IOSIZE 0
|
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#endif
|
||||
|
||||
int pcic_isa_alloc_iobase = PCIC_ISA_ALLOC_IOBASE;
|
||||
int pcic_isa_alloc_iosize = PCIC_ISA_ALLOC_IOSIZE;
|
||||
|
||||
|
||||
/*
|
||||
* Default IRQ allocation bitmask. This defines the range of allowable
|
||||
* IRQs for PCCARD slots. Useful if order of probing would screw up other
|
||||
* devices, or if PCIC hardware/cards have trouble with certain interrupt
|
||||
* lines.
|
||||
*
|
||||
* We disable IRQ 10 by default, since some common laptops (namely, the
|
||||
* NEC Versa series) reserve IRQ 10 for the docking station SCSI interface.
|
||||
*/
|
||||
|
||||
#ifndef PCIC_ISA_INTR_ALLOC_MASK
|
||||
#define PCIC_ISA_INTR_ALLOC_MASK 0xfbff
|
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#endif
|
||||
|
||||
int pcic_isa_intr_alloc_mask = PCIC_ISA_INTR_ALLOC_MASK;
|
||||
|
||||
/*****************************************************************************
|
||||
* End of configurable parameters.
|
||||
*****************************************************************************/
|
||||
|
||||
#ifdef PCICISADEBUG
|
||||
int pcicsubr_debug = 0 /* XXX */ ;
|
||||
#define DPRINTF(arg) if (pcicsubr_debug) printf arg;
|
||||
#else
|
||||
#define DPRINTF(arg)
|
||||
#endif
|
||||
|
||||
void pcic_isa_bus_width_probe (sc, iot, ioh, base, length)
|
||||
struct pcic_softc *sc;
|
||||
bus_space_tag_t iot;
|
||||
bus_space_handle_t ioh;
|
||||
bus_addr_t base;
|
||||
u_int32_t length;
|
||||
{
|
||||
bus_space_handle_t ioh_high;
|
||||
int i, iobuswidth, tmp1, tmp2;
|
||||
|
||||
/*
|
||||
* figure out how wide the isa bus is. Do this by checking if the
|
||||
* pcic controller is mirrored 0x400 above where we expect it to be.
|
||||
*/
|
||||
|
||||
iobuswidth = 12;
|
||||
|
||||
/* Map i/o space. */
|
||||
if (bus_space_map(iot, base + 0x400, length, 0, &ioh_high)) {
|
||||
printf("%s: can't map high i/o space\n", sc->dev.dv_xname);
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < PCIC_NSLOTS; i++) {
|
||||
if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) {
|
||||
/*
|
||||
* read the ident flags from the normal space and
|
||||
* from the mirror, and compare them
|
||||
*/
|
||||
|
||||
bus_space_write_1(iot, ioh, PCIC_REG_INDEX,
|
||||
sc->handle[i].sock + PCIC_IDENT);
|
||||
tmp1 = bus_space_read_1(iot, ioh, PCIC_REG_DATA);
|
||||
|
||||
bus_space_write_1(iot, ioh_high, PCIC_REG_INDEX,
|
||||
sc->handle[i].sock + PCIC_IDENT);
|
||||
tmp2 = bus_space_read_1(iot, ioh_high, PCIC_REG_DATA);
|
||||
|
||||
if (tmp1 == tmp2)
|
||||
iobuswidth = 10;
|
||||
}
|
||||
}
|
||||
|
||||
bus_space_free(iot, ioh_high, length);
|
||||
|
||||
/*
|
||||
* XXX mycroft recommends I/O space range 0x400-0xfff . I should put
|
||||
* this in a header somewhere
|
||||
*/
|
||||
|
||||
/*
|
||||
* XXX some hardware doesn't seem to grok addresses in 0x400 range--
|
||||
* apparently missing a bit or more of address lines. (e.g.
|
||||
* CIRRUS_PD672X with Linksys EthernetCard ne2000 clone in TI
|
||||
* TravelMate 5000--not clear which is at fault)
|
||||
*
|
||||
* Add a kludge to detect 10 bit wide buses and deal with them,
|
||||
* and also a config file option to override the probe.
|
||||
*/
|
||||
|
||||
if (iobuswidth == 10) {
|
||||
sc->iobase = 0x300;
|
||||
sc->iosize = 0x0ff;
|
||||
} else {
|
||||
#if 0
|
||||
/*
|
||||
* This is what we'd like to use, but...
|
||||
*/
|
||||
sc->iobase = 0x400;
|
||||
sc->iosize = 0xbff;
|
||||
#else
|
||||
/*
|
||||
* ...the above bus width probe doesn't always work.
|
||||
* So, experimentation has shown the following range
|
||||
* to not lose on systems that 0x300-0x3ff loses on
|
||||
* (e.g. the NEC Versa 6030X).
|
||||
*/
|
||||
sc->iobase = 0x330;
|
||||
sc->iosize = 0x0cf;
|
||||
#endif
|
||||
}
|
||||
|
||||
DPRINTF(("%s: bus_space_alloc range 0x%04lx-0x%04lx (probed)\n",
|
||||
sc->dev.dv_xname, (long) sc->iobase,
|
||||
|
||||
(long) sc->iobase + sc->iosize));
|
||||
|
||||
if (pcic_isa_alloc_iobase && pcic_isa_alloc_iosize) {
|
||||
sc->iobase = pcic_isa_alloc_iobase;
|
||||
sc->iosize = pcic_isa_alloc_iosize;
|
||||
|
||||
DPRINTF(("%s: bus_space_alloc range 0x%04lx-0x%04lx "
|
||||
"(config override)\n", sc->dev.dv_xname, (long) sc->iobase,
|
||||
(long) sc->iobase + sc->iosize));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void *
|
||||
pcic_isa_chip_intr_establish(pch, pf, ipl, fct, arg)
|
||||
pccard_chipset_handle_t pch;
|
||||
struct pccard_function *pf;
|
||||
int ipl;
|
||||
int (*fct) __P((void *));
|
||||
void *arg;
|
||||
{
|
||||
struct pcic_handle *h = (struct pcic_handle *) pch;
|
||||
isa_chipset_tag_t ic = h->sc->intr_est;
|
||||
int irq, ist;
|
||||
void *ih;
|
||||
int reg;
|
||||
|
||||
if (pf->cfe->flags & PCCARD_CFE_IRQLEVEL)
|
||||
ist = IST_LEVEL;
|
||||
else if (pf->cfe->flags & PCCARD_CFE_IRQPULSE)
|
||||
ist = IST_PULSE;
|
||||
else
|
||||
ist = IST_LEVEL;
|
||||
|
||||
if (isa_intr_alloc(ic,
|
||||
PCIC_INTR_IRQ_VALIDMASK & pcic_isa_intr_alloc_mask, ist, &irq))
|
||||
return (NULL);
|
||||
if ((ih = isa_intr_establish(ic, irq, ist, ipl,
|
||||
fct, arg)) == NULL)
|
||||
return (NULL);
|
||||
|
||||
reg = pcic_read(h, PCIC_INTR);
|
||||
reg &= ~PCIC_INTR_IRQ_MASK;
|
||||
reg |= irq;
|
||||
pcic_write(h, PCIC_INTR, reg);
|
||||
|
||||
h->ih_irq = irq;
|
||||
|
||||
printf("%s: card irq %d\n", h->pccard->dv_xname, irq);
|
||||
|
||||
return (ih);
|
||||
}
|
||||
|
||||
void
|
||||
pcic_isa_chip_intr_disestablish(pch, ih)
|
||||
pccard_chipset_handle_t pch;
|
||||
void *ih;
|
||||
{
|
||||
struct pcic_handle *h = (struct pcic_handle *) pch;
|
||||
isa_chipset_tag_t ic = h->sc->intr_est;
|
||||
int reg;
|
||||
|
||||
h->ih_irq = 0;
|
||||
|
||||
reg = pcic_read(h, PCIC_INTR);
|
||||
reg &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE);
|
||||
pcic_write(h, PCIC_INTR, reg);
|
||||
|
||||
isa_intr_disestablish(ic, ih);
|
||||
}
|
||||
50
sys/dev/pcic/i82365_isavar.h
Normal file
50
sys/dev/pcic/i82365_isavar.h
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
/* $NetBSD: i82365_isavar.h,v 1.1 1998/06/07 18:28:31 sommerfe Exp $ */
|
||||
/* $FreeBSD$ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1998 Bill Sommerfeld. All rights reserved.
|
||||
* Copyright (c) 1997 Marc Horowitz. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Marc Horowitz.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
extern int pcic_isa_intr_alloc_mask;
|
||||
|
||||
/*
|
||||
* Establish/disestablish interrupts for PCMCIA functions.
|
||||
*/
|
||||
|
||||
void *pcic_isa_chip_intr_establish __P((pcmcia_chipset_handle_t,
|
||||
struct pcmcia_function *, int, int (*) (void *), void *));
|
||||
void pcic_isa_chip_intr_disestablish __P((pcmcia_chipset_handle_t, void *));
|
||||
|
||||
/*
|
||||
* Figure out how wide the ISA bus is...
|
||||
*/
|
||||
|
||||
void pcic_isa_bus_width_probe __P((struct pcic_softc *, bus_space_tag_t,
|
||||
bus_space_handle_t, bus_addr_t, u_int32_t));
|
||||
|
||||
338
sys/dev/pcic/i82365reg.h
Normal file
338
sys/dev/pcic/i82365reg.h
Normal file
|
|
@ -0,0 +1,338 @@
|
|||
/* $NetBSD: i82365reg.h,v 1.3 1998/12/20 17:53:28 nathanw Exp $ */
|
||||
/* $FreeBSD$ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Marc Horowitz. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Marc Horowitz.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* All information is from the intel 82365sl PC Card Interface Controller
|
||||
* (PCIC) data sheet, marked "preliminary". Order number 290423-002, January
|
||||
* 1993.
|
||||
*/
|
||||
|
||||
#define PCIC_IOSIZE 2
|
||||
|
||||
#define PCIC_REG_INDEX 0
|
||||
#define PCIC_REG_DATA 1
|
||||
|
||||
/*
|
||||
* The PCIC allows two chips to share the same address. In order not to run
|
||||
* afoul of the netbsd device model, this driver will treat those chips as
|
||||
* the same device.
|
||||
*/
|
||||
|
||||
#define PCIC_CHIP0_BASE 0x00
|
||||
#define PCIC_CHIP1_BASE 0x80
|
||||
|
||||
/* Each PCIC chip can drive two sockets */
|
||||
|
||||
#define PCIC_SOCKETA_INDEX 0x00
|
||||
#define PCIC_SOCKETB_INDEX 0x40
|
||||
|
||||
/* general setup registers */
|
||||
|
||||
#define PCIC_IDENT 0x00 /* RO */
|
||||
#define PCIC_IDENT_IFTYPE_MASK 0xC0
|
||||
#define PCIC_IDENT_IFTYPE_IO_ONLY 0x00
|
||||
#define PCIC_IDENT_IFTYPE_MEM_ONLY 0x40
|
||||
#define PCIC_IDENT_IFTYPE_MEM_AND_IO 0x80
|
||||
#define PCIC_IDENT_IFTYPE_RESERVED 0xC0
|
||||
#define PCIC_IDENT_ZERO 0x30
|
||||
#define PCIC_IDENT_REV_MASK 0x0F
|
||||
#define PCIC_IDENT_REV_I82365SLR0 0x02
|
||||
#define PCIC_IDENT_REV_I82365SLR1 0x03
|
||||
|
||||
#define PCIC_IF_STATUS 0x01 /* RO */
|
||||
#define PCIC_IF_STATUS_GPI 0x80 /* General Purpose Input */
|
||||
#define PCIC_IF_STATUS_POWERACTIVE 0x40
|
||||
#define PCIC_IF_STATUS_READY 0x20 /* really READY/!BUSY */
|
||||
#define PCIC_IF_STATUS_MEM_WP 0x10
|
||||
#define PCIC_IF_STATUS_CARDDETECT_MASK 0x0C
|
||||
#define PCIC_IF_STATUS_CARDDETECT_PRESENT 0x0C
|
||||
#define PCIC_IF_STATUS_BATTERY_MASK 0x03
|
||||
#define PCIC_IF_STATUS_BATTERY_DEAD1 0x00
|
||||
#define PCIC_IF_STATUS_BATTERY_DEAD2 0x01
|
||||
#define PCIC_IF_STATUS_BATTERY_WARNING 0x02
|
||||
#define PCIC_IF_STATUS_BATTERY_GOOD 0x03
|
||||
|
||||
#define PCIC_PWRCTL 0x02 /* RW */
|
||||
#define PCIC_PWRCTL_OE 0x80 /* output enable */
|
||||
#define PCIC_PWRCTL_DISABLE_RESETDRV 0x40
|
||||
#define PCIC_PWRCTL_AUTOSWITCH_ENABLE 0x20
|
||||
#define PCIC_PWRCTL_PWR_ENABLE 0x10
|
||||
#define PCIC_PWRCTL_VPP2_MASK 0x0C
|
||||
/* XXX these are a little unclear from the data sheet */
|
||||
#define PCIC_PWRCTL_VPP2_RESERVED 0x0C
|
||||
#define PCIC_PWRCTL_VPP2_EN1 0x08
|
||||
#define PCIC_PWRCTL_VPP2_EN0 0x04
|
||||
#define PCIC_PWRCTL_VPP2_ENX 0x00
|
||||
#define PCIC_PWRCTL_VPP1_MASK 0x03
|
||||
/* XXX these are a little unclear from the data sheet */
|
||||
#define PCIC_PWRCTL_VPP1_RESERVED 0x03
|
||||
#define PCIC_PWRCTL_VPP1_EN1 0x02
|
||||
#define PCIC_PWRCTL_VPP1_EN0 0x01
|
||||
#define PCIC_PWRCTL_VPP1_ENX 0x00
|
||||
|
||||
#define PCIC_CSC 0x04 /* RW */
|
||||
#define PCIC_CSC_ZERO 0xE0
|
||||
#define PCIC_CSC_GPI 0x10
|
||||
#define PCIC_CSC_CD 0x08 /* Card Detect Change */
|
||||
#define PCIC_CSC_READY 0x04
|
||||
#define PCIC_CSC_BATTWARN 0x02
|
||||
#define PCIC_CSC_BATTDEAD 0x01 /* for memory cards */
|
||||
#define PCIC_CSC_RI 0x01 /* for i/o cards */
|
||||
|
||||
#define PCIC_ADDRWIN_ENABLE 0x06 /* RW */
|
||||
#define PCIC_ADDRWIN_ENABLE_IO1 0x80
|
||||
#define PCIC_ADDRWIN_ENABLE_IO0 0x40
|
||||
#define PCIC_ADDRWIN_ENABLE_MEMCS16 0x20 /* rtfds if you care */
|
||||
#define PCIC_ADDRWIN_ENABLE_MEM4 0x10
|
||||
#define PCIC_ADDRWIN_ENABLE_MEM3 0x08
|
||||
#define PCIC_ADDRWIN_ENABLE_MEM2 0x04
|
||||
#define PCIC_ADDRWIN_ENABLE_MEM1 0x02
|
||||
#define PCIC_ADDRWIN_ENABLE_MEM0 0x01
|
||||
|
||||
#define PCIC_CARD_DETECT 0x16 /* RW */
|
||||
#define PCIC_CARD_DETECT_RESERVED 0xC0
|
||||
#define PCIC_CARD_DETECT_SW_INTR 0x20
|
||||
#define PCIC_CARD_DETECT_RESUME_ENABLE 0x10
|
||||
#define PCIC_CARD_DETECT_GPI_TRANSCTL 0x08
|
||||
#define PCIC_CARD_DETECT_GPI_ENABLE 0x04
|
||||
#define PCIC_CARD_DETECT_CFGRST_ENABLE 0x02
|
||||
#define PCIC_CARD_DETECT_MEMDLY_INHIBIT 0x01
|
||||
|
||||
/* interrupt registers */
|
||||
|
||||
#define PCIC_INTR 0x03 /* RW */
|
||||
#define PCIC_INTR_RI_ENABLE 0x80
|
||||
#define PCIC_INTR_RESET 0x40 /* active low (zero) */
|
||||
#define PCIC_INTR_CARDTYPE_MASK 0x20
|
||||
#define PCIC_INTR_CARDTYPE_IO 0x20
|
||||
#define PCIC_INTR_CARDTYPE_MEM 0x00
|
||||
#define PCIC_INTR_ENABLE 0x10
|
||||
#define PCIC_INTR_IRQ_MASK 0x0F
|
||||
#define PCIC_INTR_IRQ_SHIFT 0
|
||||
#define PCIC_INTR_IRQ_NONE 0x00
|
||||
#define PCIC_INTR_IRQ_RESERVED1 0x01
|
||||
#define PCIC_INTR_IRQ_RESERVED2 0x02
|
||||
#define PCIC_INTR_IRQ3 0x03
|
||||
#define PCIC_INTR_IRQ4 0x04
|
||||
#define PCIC_INTR_IRQ5 0x05
|
||||
#define PCIC_INTR_IRQ_RESERVED6 0x06
|
||||
#define PCIC_INTR_IRQ7 0x07
|
||||
#define PCIC_INTR_IRQ_RESERVED8 0x08
|
||||
#define PCIC_INTR_IRQ9 0x09
|
||||
#define PCIC_INTR_IRQ10 0x0A
|
||||
#define PCIC_INTR_IRQ11 0x0B
|
||||
#define PCIC_INTR_IRQ12 0x0C
|
||||
#define PCIC_INTR_IRQ_RESERVED13 0x0D
|
||||
#define PCIC_INTR_IRQ14 0x0E
|
||||
#define PCIC_INTR_IRQ15 0x0F
|
||||
|
||||
#define PCIC_INTR_IRQ_VALIDMASK 0xDEB8 /* 1101 1110 1011 1000 */
|
||||
|
||||
#define PCIC_CSC_INTR 0x05 /* RW */
|
||||
#define PCIC_CSC_INTR_IRQ_MASK 0xF0
|
||||
#define PCIC_CSC_INTR_IRQ_SHIFT 4
|
||||
#define PCIC_CSC_INTR_IRQ_NONE 0x00
|
||||
#define PCIC_CSC_INTR_IRQ_RESERVED1 0x10
|
||||
#define PCIC_CSC_INTR_IRQ_RESERVED2 0x20
|
||||
#define PCIC_CSC_INTR_IRQ3 0x30
|
||||
#define PCIC_CSC_INTR_IRQ4 0x40
|
||||
#define PCIC_CSC_INTR_IRQ5 0x50
|
||||
#define PCIC_CSC_INTR_IRQ_RESERVED6 0x60
|
||||
#define PCIC_CSC_INTR_IRQ7 0x70
|
||||
#define PCIC_CSC_INTR_IRQ_RESERVED8 0x80
|
||||
#define PCIC_CSC_INTR_IRQ9 0x90
|
||||
#define PCIC_CSC_INTR_IRQ10 0xA0
|
||||
#define PCIC_CSC_INTR_IRQ11 0xB0
|
||||
#define PCIC_CSC_INTR_IRQ12 0xC0
|
||||
#define PCIC_CSC_INTR_IRQ_RESERVED13 0xD0
|
||||
#define PCIC_CSC_INTR_IRQ14 0xE0
|
||||
#define PCIC_CSC_INTR_IRQ15 0xF0
|
||||
#define PCIC_CSC_INTR_CD_ENABLE 0x08
|
||||
#define PCIC_CSC_INTR_READY_ENABLE 0x04
|
||||
#define PCIC_CSC_INTR_BATTWARN_ENABLE 0x02
|
||||
#define PCIC_CSC_INTR_BATTDEAD_ENABLE 0x01 /* for memory cards */
|
||||
#define PCIC_CSC_INTR_RI_ENABLE 0x01 /* for I/O cards */
|
||||
|
||||
#define PCIC_CSC_INTR_IRQ_VALIDMASK 0xDEB8 /* 1101 1110 1011 1000 */
|
||||
|
||||
/* I/O registers */
|
||||
|
||||
#define PCIC_IO_WINS 2
|
||||
|
||||
#define PCIC_IOCTL 0x07 /* RW */
|
||||
#define PCIC_IOCTL_IO1_WAITSTATE 0x80
|
||||
#define PCIC_IOCTL_IO1_ZEROWAIT 0x40
|
||||
#define PCIC_IOCTL_IO1_IOCS16SRC_MASK 0x20
|
||||
#define PCIC_IOCTL_IO1_IOCS16SRC_CARD 0x20
|
||||
#define PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE 0x00
|
||||
#define PCIC_IOCTL_IO1_DATASIZE_MASK 0x10
|
||||
#define PCIC_IOCTL_IO1_DATASIZE_16BIT 0x10
|
||||
#define PCIC_IOCTL_IO1_DATASIZE_8BIT 0x00
|
||||
#define PCIC_IOCTL_IO0_WAITSTATE 0x08
|
||||
#define PCIC_IOCTL_IO0_ZEROWAIT 0x04
|
||||
#define PCIC_IOCTL_IO0_IOCS16SRC_MASK 0x02
|
||||
#define PCIC_IOCTL_IO0_IOCS16SRC_CARD 0x02
|
||||
#define PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE 0x00
|
||||
#define PCIC_IOCTL_IO0_DATASIZE_MASK 0x01
|
||||
#define PCIC_IOCTL_IO0_DATASIZE_16BIT 0x01
|
||||
#define PCIC_IOCTL_IO0_DATASIZE_8BIT 0x00
|
||||
|
||||
#define PCIC_IOADDR0_START_LSB 0x08
|
||||
#define PCIC_IOADDR0_START_MSB 0x09
|
||||
#define PCIC_IOADDR0_STOP_LSB 0x0A
|
||||
#define PCIC_IOADDR0_STOP_MSB 0x0B
|
||||
#define PCIC_IOADDR1_START_LSB 0x0C
|
||||
#define PCIC_IOADDR1_START_MSB 0x0D
|
||||
#define PCIC_IOADDR1_STOP_LSB 0x0E
|
||||
#define PCIC_IOADDR1_STOP_MSB 0x0F
|
||||
|
||||
/* memory registers */
|
||||
|
||||
/*
|
||||
* memory window addresses refer to bits A23-A12 of the ISA system memory
|
||||
* address. This is a shift of 12 bits. The LSB contains A19-A12, and the
|
||||
* MSB contains A23-A20, plus some other bits.
|
||||
*/
|
||||
|
||||
#define PCIC_MEM_WINS 5
|
||||
|
||||
#define PCIC_MEM_SHIFT 12
|
||||
#define PCIC_MEM_PAGESIZE (1<<PCIC_MEM_SHIFT)
|
||||
|
||||
#define PCIC_SYSMEM_ADDRX_SHIFT PCIC_MEM_SHIFT
|
||||
#define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_MASK 0x80
|
||||
#define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT 0x80
|
||||
#define PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_8BIT 0x00
|
||||
#define PCIC_SYSMEM_ADDRX_START_MSB_ZEROWAIT 0x40
|
||||
#define PCIC_SYSMEM_ADDRX_START_MSB_SCRATCH_MASK 0x30
|
||||
#define PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK 0x0F
|
||||
|
||||
#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT_MASK 0xC0
|
||||
#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT0 0x00
|
||||
#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT1 0x40
|
||||
#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2 0x80
|
||||
#define PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT3 0xC0
|
||||
#define PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK 0x0F
|
||||
|
||||
/*
|
||||
* The card side of a memory mapping consists of bits A19-A12 of the card
|
||||
* memory address in the LSB, and A25-A20 plus some other bits in the MSB.
|
||||
* Again, the shift is 12 bits.
|
||||
*/
|
||||
|
||||
#define PCIC_CARDMEM_ADDRX_SHIFT PCIC_MEM_SHIFT
|
||||
#define PCIC_CARDMEM_ADDRX_MSB_WP 0x80
|
||||
#define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_MASK 0x40
|
||||
#define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR 0x40
|
||||
#define PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_COMMON 0x00
|
||||
#define PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK 0x3F
|
||||
|
||||
#define PCIC_SYSMEM_ADDR0_START_LSB 0x10
|
||||
#define PCIC_SYSMEM_ADDR0_START_MSB 0x11
|
||||
#define PCIC_SYSMEM_ADDR0_STOP_LSB 0x12
|
||||
#define PCIC_SYSMEM_ADDR0_STOP_MSB 0x13
|
||||
|
||||
#define PCIC_CARDMEM_ADDR0_LSB 0x14
|
||||
#define PCIC_CARDMEM_ADDR0_MSB 0x15
|
||||
|
||||
/* #define PCIC_RESERVED 0x17 */
|
||||
|
||||
#define PCIC_SYSMEM_ADDR1_START_LSB 0x18
|
||||
#define PCIC_SYSMEM_ADDR1_START_MSB 0x19
|
||||
#define PCIC_SYSMEM_ADDR1_STOP_LSB 0x1A
|
||||
#define PCIC_SYSMEM_ADDR1_STOP_MSB 0x1B
|
||||
|
||||
#define PCIC_CARDMEM_ADDR1_LSB 0x1C
|
||||
#define PCIC_CARDMEM_ADDR1_MSB 0x1D
|
||||
|
||||
#define PCIC_SYSMEM_ADDR2_START_LSB 0x20
|
||||
#define PCIC_SYSMEM_ADDR2_START_MSB 0x21
|
||||
#define PCIC_SYSMEM_ADDR2_STOP_LSB 0x22
|
||||
#define PCIC_SYSMEM_ADDR2_STOP_MSB 0x23
|
||||
|
||||
#define PCIC_CARDMEM_ADDR2_LSB 0x24
|
||||
#define PCIC_CARDMEM_ADDR2_MSB 0x25
|
||||
|
||||
/* #define PCIC_RESERVED 0x26 */
|
||||
/* #define PCIC_RESERVED 0x27 */
|
||||
|
||||
#define PCIC_SYSMEM_ADDR3_START_LSB 0x28
|
||||
#define PCIC_SYSMEM_ADDR3_START_MSB 0x29
|
||||
#define PCIC_SYSMEM_ADDR3_STOP_LSB 0x2A
|
||||
#define PCIC_SYSMEM_ADDR3_STOP_MSB 0x2B
|
||||
|
||||
#define PCIC_CARDMEM_ADDR3_LSB 0x2C
|
||||
#define PCIC_CARDMEM_ADDR3_MSB 0x2D
|
||||
|
||||
/* #define PCIC_RESERVED 0x2E */
|
||||
/* #define PCIC_RESERVED 0x2F */
|
||||
|
||||
#define PCIC_SYSMEM_ADDR4_START_LSB 0x30
|
||||
#define PCIC_SYSMEM_ADDR4_START_MSB 0x31
|
||||
#define PCIC_SYSMEM_ADDR4_STOP_LSB 0x32
|
||||
#define PCIC_SYSMEM_ADDR4_STOP_MSB 0x33
|
||||
|
||||
#define PCIC_CARDMEM_ADDR4_LSB 0x34
|
||||
#define PCIC_CARDMEM_ADDR4_MSB 0x35
|
||||
|
||||
/* #define PCIC_RESERVED 0x36 */
|
||||
/* #define PCIC_RESERVED 0x37 */
|
||||
/* #define PCIC_RESERVED 0x38 */
|
||||
/* #define PCIC_RESERVED 0x39 */
|
||||
/* #define PCIC_RESERVED 0x3A */
|
||||
/* #define PCIC_RESERVED 0x3B */
|
||||
/* #define PCIC_RESERVED 0x3C */
|
||||
/* #define PCIC_RESERVED 0x3D */
|
||||
/* #define PCIC_RESERVED 0x3E */
|
||||
/* #define PCIC_RESERVED 0x3F */
|
||||
|
||||
/* vendor-specific registers */
|
||||
|
||||
#define PCIC_INTEL_GLOBAL_CTL 0x1E /* RW */
|
||||
#define PCIC_INTEL_GLOBAL_CTL_RESERVED 0xF0
|
||||
#define PCIC_INTEL_GLOBAL_CTL_IRQ14PULSE_ENABLE 0x08
|
||||
#define PCIC_INTEL_GLOBAL_CTL_EXPLICIT_CSC_ACK 0x04
|
||||
#define PCIC_INTEL_GLOBAL_CTL_IRQLEVEL_ENABLE 0x02
|
||||
#define PCIC_INTEL_GLOBAL_CTL_POWERDOWN 0x01
|
||||
|
||||
#define PCIC_CIRRUS_MISC_CTL_2 0x1E
|
||||
#define PCIC_CIRRUS_MISC_CTL_2_SUSPEND 0x04
|
||||
|
||||
#define PCIC_CIRRUS_CHIP_INFO 0x1F
|
||||
#define PCIC_CIRRUS_CHIP_INFO_CHIP_ID 0xC0
|
||||
#define PCIC_CIRRUS_CHIP_INFO_SLOTS 0x20
|
||||
#define PCIC_CIRRUS_CHIP_INFO_REV 0x1F
|
||||
|
||||
#define PCIC_CIRRUS_EXTENDED_INDEX 0x2E
|
||||
#define PCIC_CIRRUS_EXTENDED_DATA 0x2F
|
||||
#define PCIC_CIRRUS_EXT_CONTROL_1 0x03
|
||||
#define PCIC_CIRRUS_EXT_CONTROL_1_PCI_INTR_MASK 0x18
|
||||
188
sys/dev/pcic/i82365var.h
Normal file
188
sys/dev/pcic/i82365var.h
Normal file
|
|
@ -0,0 +1,188 @@
|
|||
/* $NetBSD: i82365var.h,v 1.7 1999/01/21 07:43:33 msaitoh Exp $ */
|
||||
/* $FreeBSD$ */
|
||||
|
||||
/*
|
||||
* Copyright (c) 1997 Marc Horowitz. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Marc Horowitz.
|
||||
* 4. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <dev/pccard/pccardreg.h>
|
||||
#include <dev/pccard/pccardchip.h>
|
||||
|
||||
#include <dev/pcic/i82365reg.h>
|
||||
|
||||
struct proc;
|
||||
|
||||
struct pcic_event {
|
||||
SIMPLEQ_ENTRY(pcic_event) pe_q;
|
||||
int pe_type;
|
||||
};
|
||||
|
||||
/* pe_type */
|
||||
#define PCIC_EVENT_INSERTION 0
|
||||
#define PCIC_EVENT_REMOVAL 1
|
||||
|
||||
struct pcic_handle {
|
||||
struct pcic_softc *sc;
|
||||
int vendor;
|
||||
int sock;
|
||||
int flags;
|
||||
int laststate;
|
||||
int memalloc;
|
||||
struct {
|
||||
bus_addr_t addr;
|
||||
bus_size_t size;
|
||||
long offset;
|
||||
int kind;
|
||||
} mem[PCIC_MEM_WINS];
|
||||
int ioalloc;
|
||||
struct {
|
||||
bus_addr_t addr;
|
||||
bus_size_t size;
|
||||
int width;
|
||||
} io[PCIC_IO_WINS];
|
||||
int ih_irq;
|
||||
struct device *pccard;
|
||||
|
||||
int shutdown;
|
||||
struct proc *event_thread;
|
||||
SIMPLEQ_HEAD(, pcic_event) events;
|
||||
};
|
||||
|
||||
#define PCIC_FLAG_SOCKETP 0x0001
|
||||
#define PCIC_FLAG_CARDP 0x0002
|
||||
|
||||
#define PCIC_LASTSTATE_PRESENT 0x0002
|
||||
#define PCIC_LASTSTATE_HALF 0x0001
|
||||
#define PCIC_LASTSTATE_EMPTY 0x0000
|
||||
|
||||
#define C0SA PCIC_CHIP0_BASE+PCIC_SOCKETA_INDEX
|
||||
#define C0SB PCIC_CHIP0_BASE+PCIC_SOCKETB_INDEX
|
||||
#define C1SA PCIC_CHIP1_BASE+PCIC_SOCKETA_INDEX
|
||||
#define C1SB PCIC_CHIP1_BASE+PCIC_SOCKETB_INDEX
|
||||
|
||||
/*
|
||||
* This is sort of arbitrary. It merely needs to be "enough". It can be
|
||||
* overridden in the conf file, anyway.
|
||||
*/
|
||||
|
||||
#define PCIC_MEM_PAGES 4
|
||||
#define PCIC_MEMSIZE PCIC_MEM_PAGES*PCIC_MEM_PAGESIZE
|
||||
|
||||
#define PCIC_NSLOTS 4
|
||||
|
||||
struct pcic_softc {
|
||||
struct device dev;
|
||||
|
||||
bus_space_tag_t memt;
|
||||
bus_space_handle_t memh;
|
||||
bus_space_tag_t iot;
|
||||
bus_space_handle_t ioh;
|
||||
|
||||
/* XXX isa_chipset_tag_t, pci_chipset_tag_t, etc. */
|
||||
void *intr_est;
|
||||
|
||||
pccard_chipset_tag_t pct;
|
||||
|
||||
/* this needs to be large enough to hold PCIC_MEM_PAGES bits */
|
||||
int subregionmask;
|
||||
#define PCIC_MAX_MEM_PAGES (8 * sizeof(int))
|
||||
|
||||
/* used by memory window mapping functions */
|
||||
bus_addr_t membase;
|
||||
|
||||
/*
|
||||
* used by io window mapping functions. These can actually overlap
|
||||
* with another pcic, since the underlying extent mapper will deal
|
||||
* with individual allocations. This is here to deal with the fact
|
||||
* that different busses have different real widths (different pc
|
||||
* hardware seems to use 10 or 12 bits for the I/O bus).
|
||||
*/
|
||||
bus_addr_t iobase;
|
||||
bus_addr_t iosize;
|
||||
|
||||
int irq;
|
||||
void *ih;
|
||||
|
||||
struct pcic_handle handle[PCIC_NSLOTS];
|
||||
};
|
||||
|
||||
|
||||
int pcic_ident_ok __P((int));
|
||||
int pcic_vendor __P((struct pcic_handle *));
|
||||
char *pcic_vendor_to_string __P((int));
|
||||
|
||||
void pcic_attach __P((struct pcic_softc *));
|
||||
void pcic_attach_sockets __P((struct pcic_softc *));
|
||||
int pcic_intr __P((void *arg));
|
||||
|
||||
static __inline int pcic_read __P((struct pcic_handle *, int));
|
||||
static __inline void pcic_write __P((struct pcic_handle *, int, int));
|
||||
|
||||
int pcic_chip_mem_alloc __P((pccard_chipset_handle_t, bus_size_t,
|
||||
struct pccard_mem_handle *));
|
||||
void pcic_chip_mem_free __P((pccard_chipset_handle_t,
|
||||
struct pccard_mem_handle *));
|
||||
int pcic_chip_mem_map __P((pccard_chipset_handle_t, int, bus_addr_t,
|
||||
bus_size_t, struct pccard_mem_handle *, bus_addr_t *, int *));
|
||||
void pcic_chip_mem_unmap __P((pccard_chipset_handle_t, int));
|
||||
|
||||
int pcic_chip_io_alloc __P((pccard_chipset_handle_t, bus_addr_t,
|
||||
bus_size_t, bus_size_t, struct pccard_io_handle *));
|
||||
void pcic_chip_io_free __P((pccard_chipset_handle_t,
|
||||
struct pccard_io_handle *));
|
||||
int pcic_chip_io_map __P((pccard_chipset_handle_t, int, bus_addr_t,
|
||||
bus_size_t, struct pccard_io_handle *, int *));
|
||||
void pcic_chip_io_unmap __P((pccard_chipset_handle_t, int));
|
||||
|
||||
void pcic_chip_socket_enable __P((pccard_chipset_handle_t));
|
||||
void pcic_chip_socket_disable __P((pccard_chipset_handle_t));
|
||||
|
||||
static __inline int pcic_read __P((struct pcic_handle *, int));
|
||||
static __inline int
|
||||
pcic_read(h, idx)
|
||||
struct pcic_handle *h;
|
||||
int idx;
|
||||
{
|
||||
if (idx != -1)
|
||||
bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_INDEX,
|
||||
h->sock + idx);
|
||||
return (bus_space_read_1(h->sc->iot, h->sc->ioh, PCIC_REG_DATA));
|
||||
}
|
||||
|
||||
static __inline void pcic_write __P((struct pcic_handle *, int, int));
|
||||
static __inline void
|
||||
pcic_write(h, idx, data)
|
||||
struct pcic_handle *h;
|
||||
int idx;
|
||||
int data;
|
||||
{
|
||||
if (idx != -1)
|
||||
bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_INDEX,
|
||||
h->sock + idx);
|
||||
bus_space_write_1(h->sc->iot, h->sc->ioh, PCIC_REG_DATA, (data));
|
||||
}
|
||||
|
|
@ -146,8 +146,8 @@ device npx0 at nexus? port IO_NPX irq 13
|
|||
device apm0 at nexus? disable flags 0x31 # Advanced Power Management
|
||||
|
||||
# PCCARD (PCMCIA) support
|
||||
controller pcicx0 at isa?
|
||||
controller pcicx1 at isa?
|
||||
controller pcic0 at isa?
|
||||
controller pcic1 at isa?
|
||||
# controller pccbb0
|
||||
|
||||
# Serial (COM) ports
|
||||
|
|
|
|||
Loading…
Reference in a new issue