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hpwmc_amd.c: style improvements
- Return style - Explicit value checks - Whitespace formatting - Comment formatting - Local variable declaration order - __unused annotations Reviewed by: jkoshy MFC after: 1 week Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D41272
This commit is contained in:
Mitchell Horne
parent
440e7cb4ac
commit
d9e3fe3226
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@ -383,23 +383,20 @@ const int amd_event_codes_size = nitems(amd_event_codes);
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/*
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* Per-processor information
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*/
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struct amd_cpu {
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struct pmc_hw pc_amdpmcs[AMD_NPMCS];
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};
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static struct amd_cpu **amd_pcpu;
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/*
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* read a pmc register
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* Read a PMC value from the MSR.
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*/
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static int
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amd_read_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t *v)
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{
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enum pmc_mode mode;
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const struct amd_descr *pd;
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pmc_value_t tmp;
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enum pmc_mode mode;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[amd,%d] illegal CPU value %d", __LINE__, cpu));
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@ -411,7 +408,8 @@ amd_read_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t *v)
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pd = &amd_pmcdesc[ri];
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mode = PMC_TO_MODE(pm);
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PMCDBG2(MDP,REA,1,"amd-read id=%d class=%d", ri, pd->pm_descr.pd_class);
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PMCDBG2(MDP, REA, 1, "amd-read id=%d class=%d", ri,
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pd->pm_descr.pd_class);
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#ifdef HWPMC_DEBUG
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KASSERT(pd->pm_descr.pd_class == amd_pmc_class,
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@ -420,7 +418,7 @@ amd_read_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t *v)
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#endif
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tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */
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PMCDBG2(MDP,REA,2,"amd-read (pre-munge) id=%d -> %jd", ri, tmp);
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PMCDBG2(MDP, REA, 2, "amd-read (pre-munge) id=%d -> %jd", ri, tmp);
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if (PMC_IS_SAMPLING_MODE(mode)) {
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/*
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* Clamp value to 0 if the counter just overflowed,
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@ -437,15 +435,14 @@ amd_read_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t *v)
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}
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*v = tmp;
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PMCDBG2(MDP,REA,2,"amd-read (post-munge) id=%d -> %jd", ri, *v);
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PMCDBG2(MDP, REA, 2, "amd-read (post-munge) id=%d -> %jd", ri, *v);
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return 0;
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return (0);
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}
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/*
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* Write a PMC MSR.
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*/
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static int
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amd_write_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t v)
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{
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@ -470,24 +467,22 @@ amd_write_pmc(int cpu, int ri, struct pmc *pm, pmc_value_t v)
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if (PMC_IS_SAMPLING_MODE(mode))
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v = AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v);
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PMCDBG3(MDP,WRI,1,"amd-write cpu=%d ri=%d v=%jx", cpu, ri, v);
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PMCDBG3(MDP, WRI, 1, "amd-write cpu=%d ri=%d v=%jx", cpu, ri, v);
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/* write the PMC value */
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wrmsr(pd->pm_perfctr, v);
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return 0;
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return (0);
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}
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/*
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* configure hardware pmc according to the configuration recorded in
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* pmc 'pm'.
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* Configure hardware PMC according to the configuration recorded in 'pm'.
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*/
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static int
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amd_config_pmc(int cpu, int ri, struct pmc *pm)
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{
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struct pmc_hw *phw;
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PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
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PMCDBG3(MDP, CFG, 1, "cpu=%d ri=%d pm=%p", cpu, ri, pm);
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[amd,%d] illegal CPU value %d", __LINE__, cpu));
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@ -501,78 +496,65 @@ amd_config_pmc(int cpu, int ri, struct pmc *pm)
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__LINE__, pm, phw->phw_pmc));
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phw->phw_pmc = pm;
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return 0;
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return (0);
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}
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/*
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* Retrieve a configured PMC pointer from hardware state.
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*/
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static int
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amd_get_config(int cpu, int ri, struct pmc **ppm)
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{
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*ppm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc;
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return 0;
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return (0);
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}
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/*
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* Machine dependent actions taken during the context switch in of a
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* Machine-dependent actions taken during the context switch in of a
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* thread.
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*/
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static int
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amd_switch_in(struct pmc_cpu *pc, struct pmc_process *pp)
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amd_switch_in(struct pmc_cpu *pc __pmcdbg_used, struct pmc_process *pp)
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{
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(void) pc;
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PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp,
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PMCDBG3(MDP, SWI, 1, "pc=%p pp=%p enable-msr=%d", pc, pp,
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(pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) != 0);
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/* enable the RDPMC instruction if needed */
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if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS)
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load_cr4(rcr4() | CR4_PCE);
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return 0;
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return (0);
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}
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/*
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* Machine dependent actions taken during the context switch out of a
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* Machine-dependent actions taken during the context switch out of a
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* thread.
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*/
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static int
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amd_switch_out(struct pmc_cpu *pc, struct pmc_process *pp)
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amd_switch_out(struct pmc_cpu *pc __pmcdbg_used,
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struct pmc_process *pp __pmcdbg_used)
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{
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(void) pc;
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(void) pp; /* can be NULL */
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PMCDBG3(MDP,SWO,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp ?
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PMCDBG3(MDP, SWO, 1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp ?
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(pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) == 1 : 0);
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/* always turn off the RDPMC instruction */
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load_cr4(rcr4() & ~CR4_PCE);
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return 0;
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return (0);
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}
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/*
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* Check if a given allocation is feasible.
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* Check if a given PMC allocation is feasible.
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*/
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static int
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amd_allocate_pmc(int cpu, int ri, struct pmc *pm,
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amd_allocate_pmc(int cpu __unused, int ri, struct pmc *pm,
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const struct pmc_op_pmcallocate *a)
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{
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int i;
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const struct pmc_descr *pd;
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uint64_t allowed_unitmask, caps, config, unitmask;
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enum pmc_event pe;
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const struct pmc_descr *pd;
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int i;
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(void) cpu;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[amd,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < AMD_NPMCS,
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("[amd,%d] illegal row index %d", __LINE__, ri));
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@ -580,26 +562,30 @@ amd_allocate_pmc(int cpu, int ri, struct pmc *pm,
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/* check class match */
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if (pd->pd_class != a->pm_class)
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return EINVAL;
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return (EINVAL);
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if ((a->pm_flags & PMC_F_EV_PMU) == 0)
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return (EINVAL);
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caps = pm->pm_caps;
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PMCDBG2(MDP,ALL,1,"amd-allocate ri=%d caps=0x%x", ri, caps);
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PMCDBG2(MDP, ALL, 1,"amd-allocate ri=%d caps=0x%x", ri, caps);
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if((ri >= 0 && ri < 6) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_CORE))
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return EINVAL;
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if((ri >= 6 && ri < 12) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_L3_CACHE))
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return EINVAL;
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if((ri >= 12 && ri < 16) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_DATA_FABRIC))
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return EINVAL;
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/* Validate sub-class. */
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if ((ri >= 0 && ri < 6) && a->pm_md.pm_amd.pm_amd_sub_class !=
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PMC_AMD_SUB_CLASS_CORE)
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return (EINVAL);
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if ((ri >= 6 && ri < 12) && a->pm_md.pm_amd.pm_amd_sub_class !=
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PMC_AMD_SUB_CLASS_L3_CACHE)
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return (EINVAL);
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if ((ri >= 12 && ri < 16) && a->pm_md.pm_amd.pm_amd_sub_class !=
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PMC_AMD_SUB_CLASS_DATA_FABRIC)
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return (EINVAL);
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if (strlen(pmc_cpuid) != 0) {
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pm->pm_md.pm_amd.pm_amd_evsel =
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a->pm_md.pm_amd.pm_amd_config;
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PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, a->pm_md.pm_amd.pm_amd_config);
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pm->pm_md.pm_amd.pm_amd_evsel = a->pm_md.pm_amd.pm_amd_config;
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PMCDBG2(MDP, ALL, 2,"amd-allocate ri=%d -> config=0x%x", ri,
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a->pm_md.pm_amd.pm_amd_config);
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return (0);
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}
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@ -607,7 +593,7 @@ amd_allocate_pmc(int cpu, int ri, struct pmc *pm,
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/* map ev to the correct event mask code */
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config = allowed_unitmask = 0;
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for (i = 0; i < amd_event_codes_size; i++)
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for (i = 0; i < amd_event_codes_size; i++) {
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if (amd_event_codes[i].pe_ev == pe) {
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config =
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AMD_PMC_TO_EVENTMASK(amd_event_codes[i].pe_code);
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@ -615,58 +601,52 @@ amd_allocate_pmc(int cpu, int ri, struct pmc *pm,
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AMD_PMC_TO_UNITMASK(amd_event_codes[i].pe_mask);
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break;
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}
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}
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if (i == amd_event_codes_size)
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return EINVAL;
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return (EINVAL);
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unitmask = a->pm_md.pm_amd.pm_amd_config & AMD_PMC_UNITMASK;
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if (unitmask & ~allowed_unitmask) /* disallow reserved bits */
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return EINVAL;
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if ((unitmask & ~allowed_unitmask) != 0) /* disallow reserved bits */
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return (EINVAL);
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if (unitmask && (caps & PMC_CAP_QUALIFIER))
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if (unitmask && (caps & PMC_CAP_QUALIFIER) != 0)
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config |= unitmask;
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if (caps & PMC_CAP_THRESHOLD)
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if ((caps & PMC_CAP_THRESHOLD) != 0)
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config |= a->pm_md.pm_amd.pm_amd_config & AMD_PMC_COUNTERMASK;
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/* set at least one of the 'usr' or 'os' caps */
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if (caps & PMC_CAP_USER)
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/* Set at least one of the 'usr' or 'os' caps. */
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if ((caps & PMC_CAP_USER) != 0)
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config |= AMD_PMC_USR;
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if (caps & PMC_CAP_SYSTEM)
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if ((caps & PMC_CAP_SYSTEM) != 0)
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config |= AMD_PMC_OS;
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if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0)
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if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0)
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config |= (AMD_PMC_USR|AMD_PMC_OS);
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if (caps & PMC_CAP_EDGE)
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if ((caps & PMC_CAP_EDGE) != 0)
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config |= AMD_PMC_EDGE;
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if (caps & PMC_CAP_INVERT)
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if ((caps & PMC_CAP_INVERT) != 0)
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config |= AMD_PMC_INVERT;
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if (caps & PMC_CAP_INTERRUPT)
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if ((caps & PMC_CAP_INTERRUPT) != 0)
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config |= AMD_PMC_INT;
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pm->pm_md.pm_amd.pm_amd_evsel = config; /* save config value */
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PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, config);
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PMCDBG2(MDP, ALL, 2, "amd-allocate ri=%d -> config=0x%x", ri, config);
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return 0;
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return (0);
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}
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/*
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* Release machine dependent state associated with a PMC. This is a
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* no-op on this architecture.
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*
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*/
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/* ARGSUSED0 */
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static int
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amd_release_pmc(int cpu, int ri, struct pmc *pmc)
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amd_release_pmc(int cpu, int ri, struct pmc *pmc __unused)
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{
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#ifdef HWPMC_DEBUG
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const struct amd_descr *pd;
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#endif
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const struct amd_descr *pd __pmcdbg_used;
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struct pmc_hw *phw __diagused;
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(void) pmc;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[amd,%d] illegal CPU value %d", __LINE__, cpu));
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KASSERT(ri >= 0 && ri < AMD_NPMCS,
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@ -677,25 +657,23 @@ amd_release_pmc(int cpu, int ri, struct pmc *pmc)
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KASSERT(phw->phw_pmc == NULL,
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("[amd,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc));
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#ifdef HWPMC_DEBUG
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#ifdef HWPMC_DEBUG
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pd = &amd_pmcdesc[ri];
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if (pd->pm_descr.pd_class == amd_pmc_class)
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KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel),
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("[amd,%d] PMC %d released while active", __LINE__, ri));
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#endif
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return 0;
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return (0);
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}
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/*
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* start a PMC.
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* Start a PMC.
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*/
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static int
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amd_start_pmc(int cpu, int ri, struct pmc *pm)
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amd_start_pmc(int cpu __diagused, int ri, struct pmc *pm)
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{
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uint64_t config;
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const struct amd_descr *pd;
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uint64_t config;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[amd,%d] illegal CPU value %d", __LINE__, cpu));
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@ -704,7 +682,7 @@ amd_start_pmc(int cpu, int ri, struct pmc *pm)
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pd = &amd_pmcdesc[ri];
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PMCDBG2(MDP,STA,1,"amd-start cpu=%d ri=%d", cpu, ri);
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PMCDBG2(MDP, STA, 1, "amd-start cpu=%d ri=%d", cpu, ri);
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KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel),
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("[amd,%d] pmc%d,cpu%d: Starting active PMC \"%s\"", __LINE__,
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@ -713,18 +691,17 @@ amd_start_pmc(int cpu, int ri, struct pmc *pm)
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/* turn on the PMC ENABLE bit */
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config = pm->pm_md.pm_amd.pm_amd_evsel | AMD_PMC_ENABLE;
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PMCDBG1(MDP,STA,2,"amd-start config=0x%x", config);
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PMCDBG1(MDP, STA, 2, "amd-start config=0x%x", config);
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wrmsr(pd->pm_evsel, config);
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return 0;
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return (0);
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}
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/*
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* Stop a PMC.
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*/
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static int
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amd_stop_pmc(int cpu, int ri, struct pmc *pm)
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amd_stop_pmc(int cpu __diagused, int ri, struct pmc *pm)
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{
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const struct amd_descr *pd;
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uint64_t config;
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@ -741,7 +718,7 @@ amd_stop_pmc(int cpu, int ri, struct pmc *pm)
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("[amd,%d] PMC%d, CPU%d \"%s\" already stopped",
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__LINE__, ri, cpu, pd->pm_descr.pd_name));
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PMCDBG1(MDP,STO,1,"amd-stop ri=%d", ri);
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PMCDBG1(MDP, STO, 1, "amd-stop ri=%d", ri);
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/* turn off the PMC ENABLE bit */
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config = pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE;
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@ -761,7 +738,7 @@ amd_stop_pmc(int cpu, int ri, struct pmc *pm)
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DELAY(1);
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}
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return 0;
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return (0);
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}
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/*
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@ -770,23 +747,21 @@ amd_stop_pmc(int cpu, int ri, struct pmc *pm)
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* to sleep or do anything a 'fast' interrupt handler is not allowed
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* to do.
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*/
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static int
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amd_intr(struct trapframe *tf)
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{
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int i, error, retval, cpu;
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uint64_t config, evsel, perfctr;
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struct pmc *pm;
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struct amd_cpu *pac;
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struct pmc *pm;
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pmc_value_t v;
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uint64_t config, evsel, perfctr;
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uint32_t active = 0, count = 0;
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int i, error, retval, cpu;
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cpu = curcpu;
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KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
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("[amd,%d] out of range CPU %d", __LINE__, cpu));
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|
||||
PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf,
|
||||
TRAPF_USERMODE(tf));
|
||||
PMCDBG3(MDP, INT, 1, "cpu=%d tf=%p um=%d", cpu, tf, TRAPF_USERMODE(tf));
|
||||
|
||||
retval = 0;
|
||||
|
||||
|
|
@ -803,9 +778,7 @@ amd_intr(struct trapframe *tf)
|
|||
* a single interrupt. Check all the valid pmcs for
|
||||
* overflow.
|
||||
*/
|
||||
|
||||
for (i = 0; i < AMD_CORE_NPMCS; i++) {
|
||||
|
||||
if ((pm = pac->pc_amdpmcs[i].phw_pmc) == NULL ||
|
||||
!PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) {
|
||||
continue;
|
||||
|
|
@ -823,8 +796,8 @@ amd_intr(struct trapframe *tf)
|
|||
continue;
|
||||
|
||||
/* Stop the PMC, reload count. */
|
||||
evsel = amd_pmcdesc[i].pm_evsel;
|
||||
perfctr = amd_pmcdesc[i].pm_perfctr;
|
||||
evsel = amd_pmcdesc[i].pm_evsel;
|
||||
perfctr = amd_pmcdesc[i].pm_perfctr;
|
||||
v = pm->pm_sc.pm_reloadcount;
|
||||
config = rdmsr(evsel);
|
||||
|
||||
|
|
@ -852,7 +825,6 @@ amd_intr(struct trapframe *tf)
|
|||
* if this NMI was for a pmc overflow which was serviced
|
||||
* in an earlier request or should be ignored.
|
||||
*/
|
||||
|
||||
if (retval) {
|
||||
DPCPU_SET(nmi_counter, min(2, active));
|
||||
} else {
|
||||
|
|
@ -867,12 +839,12 @@ amd_intr(struct trapframe *tf)
|
|||
else
|
||||
counter_u64_add(pmc_stats.pm_intr_ignored, 1);
|
||||
|
||||
PMCDBG1(MDP,INT,2, "retval=%d", retval);
|
||||
PMCDBG1(MDP, INT, 2, "retval=%d", retval);
|
||||
return (retval);
|
||||
}
|
||||
|
||||
/*
|
||||
* describe a PMC
|
||||
* Describe a PMC.
|
||||
*/
|
||||
static int
|
||||
amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
|
||||
|
|
@ -891,25 +863,20 @@ amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc)
|
|||
strlcpy(pi->pm_name, pd->pm_descr.pd_name, sizeof(pi->pm_name));
|
||||
pi->pm_class = pd->pm_descr.pd_class;
|
||||
|
||||
if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) {
|
||||
pi->pm_enabled = TRUE;
|
||||
if ((phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) != 0) {
|
||||
pi->pm_enabled = true;
|
||||
*ppmc = phw->phw_pmc;
|
||||
} else {
|
||||
pi->pm_enabled = FALSE;
|
||||
pi->pm_enabled = false;
|
||||
*ppmc = NULL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* i386 specific entry points
|
||||
* Return the MSR address of the given PMC.
|
||||
*/
|
||||
|
||||
/*
|
||||
* return the MSR address of the given PMC.
|
||||
*/
|
||||
|
||||
static int
|
||||
amd_get_msr(int ri, uint32_t *msr)
|
||||
{
|
||||
|
|
@ -917,29 +884,27 @@ amd_get_msr(int ri, uint32_t *msr)
|
|||
("[amd,%d] ri %d out of range", __LINE__, ri));
|
||||
|
||||
*msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* processor dependent initialization.
|
||||
* Processor-dependent initialization.
|
||||
*/
|
||||
|
||||
static int
|
||||
amd_pcpu_init(struct pmc_mdep *md, int cpu)
|
||||
{
|
||||
int classindex, first_ri, n;
|
||||
struct pmc_cpu *pc;
|
||||
struct amd_cpu *pac;
|
||||
struct pmc_cpu *pc;
|
||||
struct pmc_hw *phw;
|
||||
int classindex, first_ri, n;
|
||||
|
||||
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
||||
("[amd,%d] insane cpu number %d", __LINE__, cpu));
|
||||
|
||||
PMCDBG1(MDP,INI,1,"amd-init cpu=%d", cpu);
|
||||
PMCDBG1(MDP, INI, 1, "amd-init cpu=%d", cpu);
|
||||
|
||||
amd_pcpu[cpu] = pac = malloc(sizeof(struct amd_cpu), M_PMC,
|
||||
M_WAITOK|M_ZERO);
|
||||
M_WAITOK | M_ZERO);
|
||||
|
||||
/*
|
||||
* Set the content of the hardware descriptors to a known
|
||||
|
|
@ -957,33 +922,30 @@ amd_pcpu_init(struct pmc_mdep *md, int cpu)
|
|||
KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu pointer", __LINE__));
|
||||
|
||||
for (n = 0, phw = pac->pc_amdpmcs; n < AMD_NPMCS; n++, phw++) {
|
||||
phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
|
||||
phw->phw_state = PMC_PHW_FLAG_IS_ENABLED |
|
||||
PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n);
|
||||
phw->phw_pmc = NULL;
|
||||
pc->pc_hwpmcs[n + first_ri] = phw;
|
||||
phw->phw_pmc = NULL;
|
||||
pc->pc_hwpmcs[n + first_ri] = phw;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* processor dependent cleanup prior to the KLD
|
||||
* being unloaded
|
||||
* Processor-dependent cleanup prior to the KLD being unloaded.
|
||||
*/
|
||||
|
||||
static int
|
||||
amd_pcpu_fini(struct pmc_mdep *md, int cpu)
|
||||
{
|
||||
int classindex, first_ri, i;
|
||||
uint32_t evsel;
|
||||
struct pmc_cpu *pc;
|
||||
struct amd_cpu *pac;
|
||||
struct pmc_cpu *pc;
|
||||
uint32_t evsel;
|
||||
int classindex, first_ri, i;
|
||||
|
||||
KASSERT(cpu >= 0 && cpu < pmc_cpu_max(),
|
||||
("[amd,%d] insane cpu number (%d)", __LINE__, cpu));
|
||||
|
||||
PMCDBG1(MDP,INI,1,"amd-cleanup cpu=%d", cpu);
|
||||
PMCDBG1(MDP, INI, 1, "amd-cleanup cpu=%d", cpu);
|
||||
|
||||
/*
|
||||
* First, turn off all PMCs on this CPU.
|
||||
|
|
@ -1014,9 +976,9 @@ amd_pcpu_fini(struct pmc_mdep *md, int cpu)
|
|||
pc = pmc_pcpu[cpu];
|
||||
KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu state", __LINE__));
|
||||
|
||||
#if defined(__amd64__)
|
||||
#ifdef __amd64__
|
||||
classindex = PMC_MDEP_CLASS_INDEX_K8;
|
||||
#elif defined(__i386__)
|
||||
#else
|
||||
classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? PMC_MDEP_CLASS_INDEX_K8 :
|
||||
PMC_MDEP_CLASS_INDEX_K7;
|
||||
#endif
|
||||
|
|
@ -1025,30 +987,26 @@ amd_pcpu_fini(struct pmc_mdep *md, int cpu)
|
|||
/*
|
||||
* Reset pointers in the MI 'per-cpu' state.
|
||||
*/
|
||||
for (i = 0; i < AMD_NPMCS; i++) {
|
||||
for (i = 0; i < AMD_NPMCS; i++)
|
||||
pc->pc_hwpmcs[i + first_ri] = NULL;
|
||||
}
|
||||
|
||||
|
||||
free(pac, M_PMC);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize ourselves.
|
||||
*/
|
||||
|
||||
struct pmc_mdep *
|
||||
pmc_amd_initialize(void)
|
||||
{
|
||||
int classindex, error, i, ncpus;
|
||||
struct pmc_classdep *pcd;
|
||||
enum pmc_cputype cputype;
|
||||
struct pmc_mdep *pmc_mdep;
|
||||
enum pmc_class class;
|
||||
int family, model, stepping;
|
||||
char *name;
|
||||
enum pmc_cputype cputype;
|
||||
enum pmc_class class;
|
||||
int classindex, error, i, ncpus;
|
||||
int family, model, stepping;
|
||||
|
||||
/*
|
||||
* The presence of hardware performance counters on the AMD
|
||||
|
|
@ -1071,7 +1029,7 @@ pmc_amd_initialize(void)
|
|||
family, model, stepping);
|
||||
|
||||
switch (cpu_id & 0xF00) {
|
||||
#if defined(__i386__)
|
||||
#ifdef __i386__
|
||||
case 0x600: /* Athlon(tm) processor */
|
||||
classindex = PMC_MDEP_CLASS_INDEX_K7;
|
||||
cputype = PMC_CPU_AMD_K7;
|
||||
|
|
@ -1087,11 +1045,12 @@ pmc_amd_initialize(void)
|
|||
break;
|
||||
|
||||
default:
|
||||
(void) printf("pmc: Unknown AMD CPU %x %d-%d.\n", cpu_id, (cpu_id & 0xF00) >> 8, model);
|
||||
return NULL;
|
||||
printf("pmc: Unknown AMD CPU %x %d-%d.\n", cpu_id, family,
|
||||
model);
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
#ifdef HWPMC_DEBUG
|
||||
#ifdef HWPMC_DEBUG
|
||||
amd_pmc_class = class;
|
||||
#endif
|
||||
|
||||
|
|
@ -1100,7 +1059,7 @@ pmc_amd_initialize(void)
|
|||
* the MDEP structure used by MI code.
|
||||
*/
|
||||
amd_pcpu = malloc(sizeof(struct amd_cpu *) * pmc_cpu_max(), M_PMC,
|
||||
M_WAITOK|M_ZERO);
|
||||
M_WAITOK | M_ZERO);
|
||||
|
||||
/*
|
||||
* These processors have two classes of PMCs: the TSC and
|
||||
|
|
@ -1108,13 +1067,11 @@ pmc_amd_initialize(void)
|
|||
*/
|
||||
pmc_mdep = pmc_mdep_alloc(2);
|
||||
|
||||
pmc_mdep->pmd_cputype = cputype;
|
||||
|
||||
ncpus = pmc_cpu_max();
|
||||
|
||||
/* Initialize the TSC. */
|
||||
error = pmc_tsc_initialize(pmc_mdep, ncpus);
|
||||
if (error)
|
||||
if (error != 0)
|
||||
goto error;
|
||||
|
||||
/* Initialize AMD K7 and K8 PMC handling. */
|
||||
|
|
@ -1128,8 +1085,7 @@ pmc_amd_initialize(void)
|
|||
|
||||
/* fill in the correct pmc name and class */
|
||||
for (i = 0; i < AMD_NPMCS; i++) {
|
||||
(void) snprintf(amd_pmcdesc[i].pm_descr.pd_name,
|
||||
sizeof(amd_pmcdesc[i].pm_descr.pd_name), "%s-%d",
|
||||
snprintf(amd_pmcdesc[i].pm_descr.pd_name, PMC_NAME_MAX, "%s-%d",
|
||||
name, i);
|
||||
amd_pmcdesc[i].pm_descr.pd_class = class;
|
||||
}
|
||||
|
|
@ -1147,29 +1103,25 @@ pmc_amd_initialize(void)
|
|||
pcd->pcd_stop_pmc = amd_stop_pmc;
|
||||
pcd->pcd_write_pmc = amd_write_pmc;
|
||||
|
||||
pmc_mdep->pmd_cputype = cputype;
|
||||
pmc_mdep->pmd_intr = amd_intr;
|
||||
pmc_mdep->pmd_switch_in = amd_switch_in;
|
||||
pmc_mdep->pmd_switch_in = amd_switch_in;
|
||||
pmc_mdep->pmd_switch_out = amd_switch_out;
|
||||
|
||||
pmc_mdep->pmd_npmc += AMD_NPMCS;
|
||||
pmc_mdep->pmd_npmc += AMD_NPMCS;
|
||||
|
||||
PMCDBG0(MDP,INI,0,"amd-initialize");
|
||||
PMCDBG0(MDP, INI, 0, "amd-initialize");
|
||||
|
||||
return (pmc_mdep);
|
||||
|
||||
error:
|
||||
if (error) {
|
||||
free(pmc_mdep, M_PMC);
|
||||
pmc_mdep = NULL;
|
||||
}
|
||||
|
||||
error:
|
||||
free(pmc_mdep, M_PMC);
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
/*
|
||||
* Finalization code for AMD CPUs.
|
||||
*/
|
||||
|
||||
void
|
||||
pmc_amd_finalize(struct pmc_mdep *md)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in a new issue