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pmc(3): remove Pentium-related man pages and references
Support for Pentium events was removed completely in e92a1350b5
.
Don't bump .Dd where we are just removing xrefs.
Reviewed by: emaste
MFC after: 1 week
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D31423
This commit is contained in:
parent
12e8addd32
commit
d78896e46f
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@ -40,6 +40,11 @@
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# xargs -n1 | sort | uniq -d;
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# done
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# 20210810: remove Pentium-related man pages and references
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OLD_FILES+=usr/share/man/man3/pmc.p4.3.gz
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OLD_FILES+=usr/share/man/man3/pmc.p5.3.gz
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OLD_FILES+=usr/share/man/man3/pmc.p6.3.gz
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# 20210805: C.UTF-8 installed to the wrong location
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OLD_FILES+=usr/share/C.UTF-8.LC_CTYPE
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@ -83,9 +83,6 @@ MAN+= pmc.k7.3
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MAN+= pmc.k8.3
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MAN+= pmc.mips24k.3
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MAN+= pmc.octeon.3
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MAN+= pmc.p4.3
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MAN+= pmc.p5.3
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MAN+= pmc.p6.3
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MAN+= pmc.sandybridge.3
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MAN+= pmc.sandybridgeuc.3
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MAN+= pmc.sandybridgexeon.3
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@ -23,7 +23,7 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd December 12, 2020
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.Dd August 10, 2021
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.Dt PMC 3
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.Os
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.Sh NAME
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@ -161,26 +161,6 @@ and
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CPUs, and other CPUs conforming to version 2 of the
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.Tn Intel
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performance measurement architecture.
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.It Li PMC_CPU_INTEL_P5
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.Tn Intel
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.Tn "Pentium"
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CPUs.
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.It Li PMC_CPU_INTEL_P6
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.Tn Intel
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.Tn "Pentium Pro"
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CPUs.
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.It Li PMC_CPU_INTEL_PII
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.Tn "Intel Pentium II"
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CPUs.
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.It Li PMC_CPU_INTEL_PIII
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.Tn "Intel Pentium III"
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CPUs.
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.It Li PMC_CPU_INTEL_PIV
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.Tn "Intel Pentium 4"
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CPUs.
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.It Li PMC_CPU_INTEL_PM
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.Tn "Intel Pentium M"
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CPUs.
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.El
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.Ss Supported PMCs
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PMC supported by this library are named by the
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@ -205,25 +185,6 @@ CPUs.
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Programmable hardware counters present in
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.Tn "AMD Athlon64"
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CPUs.
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.It Li PMC_CLASS_P4
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Programmable hardware counters present in
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.Tn "Intel Pentium 4"
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CPUs.
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.It Li PMC_CLASS_P5
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Programmable hardware counters present in
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.Tn Intel
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.Tn Pentium
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CPUs.
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.It Li PMC_CLASS_P6
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Programmable hardware counters present in
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.Tn Intel
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.Tn "Pentium Pro" ,
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.Tn "Pentium II" ,
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.Tn "Pentium III" ,
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.Tn "Celeron" ,
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and
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.Tn "Pentium M"
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CPUs.
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.It Li PMC_CLASS_TSC
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The timestamp counter on i386 and amd64 architecture CPUs.
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.It Li PMC_CLASS_SOFT
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@ -473,9 +434,6 @@ following manual pages:
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.It Li PMC_CLASS_IAP Ta Xr pmc.atom 3 , Xr pmc.core 3 , Xr pmc.core2 3
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.It Li PMC_CLASS_K7 Ta Xr pmc.k7 3
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.It Li PMC_CLASS_K8 Ta Xr pmc.k8 3
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.It Li PMC_CLASS_P4 Ta Xr pmc.p4 3
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.It Li PMC_CLASS_P5 Ta Xr pmc.p5 3
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.It Li PMC_CLASS_P6 Ta Xr pmc.p6 3
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.It Li PMC_CLASS_TSC Ta Xr pmc.tsc 3
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.El
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.Ss Event Name Aliases
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@ -535,9 +493,6 @@ API is
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.Xr pmc.k8 3 ,
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.Xr pmc.mips24k 3 ,
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.Xr pmc.octeon 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.sandybridge 3 ,
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.Xr pmc.sandybridgeuc 3 ,
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.Xr pmc.sandybridgexeon 3 ,
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@ -1174,9 +1174,6 @@ and the underlying hardware events used on these CPUs.
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.Xr pmc.iaf 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.soft 3 ,
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.Xr pmc.tsc 3 ,
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.Xr pmc_cpuinfo 3 ,
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@ -512,9 +512,6 @@ The number of times the MSROM starts a flow of UOPS.
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.Xr pmc.iaf 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.soft 3 ,
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.Xr pmc.tsc 3 ,
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.Xr pmc_cpuinfo 3 ,
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@ -789,9 +789,6 @@ may not count some transitions.
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.Xr pmc.iaf 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.soft 3 ,
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.Xr pmc.tsc 3 ,
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.Xr pmclog 3 ,
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@ -1104,9 +1104,6 @@ and the underlying hardware events used.
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.Xr pmc.iaf 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.soft 3 ,
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.Xr pmc.tsc 3 ,
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.Xr pmc_cpuinfo 3 ,
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@ -1583,9 +1583,6 @@ Counts number of segment register loads.
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.Xr pmc.iaf 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.soft 3 ,
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.Xr pmc.tsc 3 ,
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.Xr pmc.ucf 3 ,
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@ -886,9 +886,6 @@ into a power down mode.
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.Xr pmc.iaf 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.soft 3 ,
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.Xr pmc.tsc 3 ,
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.Xr pmc.ucf 3 ,
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@ -921,9 +921,6 @@ Dirty L2 cache lines evicted by demand.
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.Xr pmc.ivybridgexeon 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.sandybridge 3 ,
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.Xr pmc.sandybridgeuc 3 ,
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.Xr pmc.sandybridgexeon 3 ,
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@ -205,9 +205,6 @@ Number of requests allocated in Coherency Tracker.
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.Xr pmc.iaf 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.sandybridge 3 ,
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.Xr pmc.sandybridgeuc 3 ,
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.Xr pmc.sandybridgexeon 3 ,
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@ -935,9 +935,6 @@ Dirty L2 cache lines evicted by demand.
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.Xr pmc.ivybridgexeon 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.sandybridge 3 ,
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.Xr pmc.sandybridgeuc 3 ,
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.Xr pmc.sandybridgexeon 3 ,
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@ -128,9 +128,6 @@ CPU, use the event specifier
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.Xr pmc.core2 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.soft 3 ,
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.Xr pmc.tsc 3 ,
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.Xr pmc_cpuinfo 3 ,
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@ -833,9 +833,6 @@ Dirty L2 cache lines evicted by the MLC prefetcher.
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.Xr pmc.ivybridgexeon 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.sandybridge 3 ,
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.Xr pmc.sandybridgeuc 3 ,
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.Xr pmc.sandybridgexeon 3 ,
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@ -866,9 +866,6 @@ Dirty L2 cache lines filling the L2.
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.Xr pmc.ivybridge 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.sandybridge 3 ,
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.Xr pmc.sandybridgeuc 3 ,
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.Xr pmc.sandybridgexeon 3 ,
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|
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@ -246,9 +246,6 @@ and the underlying hardware events used.
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.Xr pmc.core2 3 ,
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.Xr pmc.iaf 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.soft 3 ,
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.Xr pmc.tsc 3 ,
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.Xr pmclog 3 ,
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@ -779,9 +779,6 @@ and the underlying hardware events used.
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.Xr pmc.core2 3 ,
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.Xr pmc.iaf 3 ,
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.Xr pmc.k7 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.soft 3 ,
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.Xr pmc.tsc 3 ,
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.Xr pmclog 3 ,
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@ -389,9 +389,6 @@ and the underlying hardware events used.
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.octeon 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.soft 3 ,
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.Xr pmc.tsc 3 ,
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.Xr pmc_cpuinfo 3 ,
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@ -229,9 +229,6 @@ and the underlying hardware events used.
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.Xr pmc.k7 3 ,
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.Xr pmc.k8 3 ,
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.Xr pmc.mips24k 3 ,
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.Xr pmc.p4 3 ,
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.Xr pmc.p5 3 ,
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.Xr pmc.p6 3 ,
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.Xr pmc.soft 3 ,
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.Xr pmc.tsc 3 ,
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.Xr pmc_cpuinfo 3 ,
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1223
lib/libpmc/pmc.p4.3
1223
lib/libpmc/pmc.p4.3
File diff suppressed because it is too large
Load diff
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@ -1,460 +0,0 @@
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.\" Copyright (c) 2003-2008 Joseph Koshy. All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
|
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.\" modification, are permitted provided that the following conditions
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.\" are met:
|
||||
.\" 1. Redistributions of source code must retain the above copyright
|
||||
.\" notice, this list of conditions and the following disclaimer.
|
||||
.\" 2. Redistributions in binary form must reproduce the above copyright
|
||||
.\" notice, this list of conditions and the following disclaimer in the
|
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.\" documentation and/or other materials provided with the distribution.
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.\"
|
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd October 4, 2008
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.Dt PMC 3
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.Os
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.Sh NAME
|
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.Nm pmc
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.Nd library for accessing hardware performance monitoring counters
|
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.Sh LIBRARY
|
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.Lb libpmc
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.Sh SYNOPSIS
|
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.In pmc.h
|
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.Sh DESCRIPTION
|
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Intel Pentium PMCs are present in Intel
|
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.Tn Pentium
|
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and
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.Tn "Pentium MMX"
|
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processors.
|
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These PMCs are documented in the
|
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.Rs
|
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.%B "Intel 64 and IA-32 Intel(R) Architectures Software Developer's Manual"
|
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.%T "Volume 3B: System Programming Guide, Part 2"
|
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.%N "Order Number 253669-024US"
|
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.%D "August 2007"
|
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.%Q "Intel Corporation"
|
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.Re
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.Ss PMC Features
|
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These CPUs contain two PMCs, each 40 bits wide.
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These PMCs support the following capabilities:
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.Bl -column "PMC_CAP_INTERRUPT" "Support"
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.It Em Capability Ta Em Support
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.It PMC_CAP_CASCADE Ta \&No
|
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.It PMC_CAP_EDGE Ta \&No
|
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.It PMC_CAP_INTERRUPT Ta \&No
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.It PMC_CAP_INVERT Ta \&No
|
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.It PMC_CAP_READ Ta Yes
|
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.It PMC_CAP_PRECISE Ta \&No
|
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.It PMC_CAP_SYSTEM Ta Yes
|
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.It PMC_CAP_TAGGING Ta \&No
|
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.It PMC_CAP_THRESHOLD Ta \&No
|
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.It PMC_CAP_USER Ta Yes
|
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.It PMC_CAP_WRITE Ta Yes
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.El
|
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.Ss Event Qualifiers
|
||||
Event specifiers for Intel Pentium PMCs can have the following common
|
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qualifiers:
|
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.Bl -tag -width indent
|
||||
.It Li duration
|
||||
Count duration (in clocks) of events.
|
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The default is to count events.
|
||||
.It Li os
|
||||
Measure events at privilege levels 0, 1 and 2.
|
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.It Li overflow
|
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Assert the external processor pin associated with a counter on counter
|
||||
overflow.
|
||||
.It Li usr
|
||||
Measure events at privilege level 3.
|
||||
.El
|
||||
.Pp
|
||||
If neither of the
|
||||
.Dq Li os
|
||||
or
|
||||
.Dq Li usr
|
||||
qualifiers are specified, the default is to enable both.
|
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.Pp
|
||||
Some events may only be used on specific counters and some events
|
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are defined only on processors supporting the MMX instruction set.
|
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Note that these PMCs do not have the ability to interrupt the CPU.
|
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.Ss Intel Pentium Event Specifiers
|
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The event specifiers supported by Intel Pentium PMCs are:
|
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.Bl -tag -width indent
|
||||
.It Li p5-any-segment-register-loaded
|
||||
.Pq Event 0FH
|
||||
The number of writes to any segment register, including the LDTR,
|
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GDTR, TR and IDTR.
|
||||
Far control transfers and task switches that involve privilege
|
||||
level changes will count this event twice.
|
||||
.It Li p5-bank-conflicts
|
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.Pq Event 0AH
|
||||
The number of actual bank conflicts.
|
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.It Li p5-branches
|
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.Pq Event 12H
|
||||
The number of taken and not taken branches including branches, jumps, calls,
|
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software interrupts and interrupt returns.
|
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.It Li p5-breakpoint-match-on-dr0-register
|
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.Pq Event 23H
|
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The number of matches on the DR0 breakpoint register.
|
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.It Li p5-breakpoint-match-on-dr1-register
|
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.Pq Event 24H
|
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The number of matches on the DR1 breakpoint register.
|
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.It Li p5-breakpoint-match-on-dr2-register
|
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.Pq Event 25H
|
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The number of matches on the DR2 breakpoint register.
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.It Li p5-breakpoint-match-on-dr3-register
|
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.Pq Event 26H
|
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The number of matches on the DR3 breakpoint register.
|
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.It Li p5-btb-false-entries
|
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.Pq Event 3AH , Tn Pentium MMX
|
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The number of false entries in the BTB.
|
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This event is only allocated on counter 0.
|
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.It Li p5-btb-hits
|
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.Pq Event 13H
|
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The number of branches executed that hit in the branch table buffer.
|
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.It Li p5-btb-miss-prediction-on-not-taken-branch
|
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.Pq Event 3AH , Tn Pentium MMX
|
||||
The number of times the BTB predicted a not-taken branch as taken.
|
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This event is only allocated on counter 1.
|
||||
.It Li p5-bus-cycle-duration
|
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.Pq Event 18H
|
||||
The number of cycles while a bus cycle was in progress.
|
||||
.It Li p5-bus-ownership-latency
|
||||
.Pq Event 2AH , Tn Pentium MMX
|
||||
The time from bus ownership being requested to ownership being granted.
|
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This event is only allocated on counter 0.
|
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.It Li p5-bus-ownership-transfers
|
||||
.Pq Event 2AH , Tn Pentium MMX
|
||||
The number of bus ownership transfers.
|
||||
This event is only allocated on counter 1.
|
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.It Li p5-bus-utilization-due-to-processor-activity
|
||||
.Pq Event 2EH , Tn Pentium MMX
|
||||
The number of clocks the bus is busy due to the processor's own
|
||||
activity.
|
||||
This event is only allocated on counter 0.
|
||||
.It Li p5-cache-line-sharing
|
||||
.Pq Event 2CH , Tn Pentium MMX
|
||||
The number of shared data lines in L1 cache.
|
||||
This event is only allocated on counter 1.
|
||||
.It Li p5-cache-m-state-line-sharing
|
||||
.Pq Event 2CH , Tn Pentium MMX
|
||||
The number of hits to an M- state line due to a memory access by
|
||||
another processor.
|
||||
This event is only allocated on counter 0.
|
||||
.It Li p5-code-cache-miss
|
||||
.Pq Event 0EH
|
||||
The number of instruction reads that miss the internal code cache.
|
||||
Both cacheable and un-cacheable misses are counted.
|
||||
.It Li p5-code-read
|
||||
.Pq Event 0CH
|
||||
The number of instruction reads to both cacheable and un-cacheable regions.
|
||||
.It Li p5-code-tlb-miss
|
||||
.Pq Event 0DH
|
||||
The number of instruction reads that miss the instruction TLB.
|
||||
Both cacheable and un-cacheable unreads are counted.
|
||||
.It Li p5-d1-starvation-and-fifo-is-empty
|
||||
.Pq Event 33H , Tn Pentium MMX
|
||||
The number of times the D1 stage cannot issue any instructions because
|
||||
the FIFO was empty.
|
||||
This event is only allocated on counter 0.
|
||||
.It Li p5-d1-starvation-and-only-one-instruction-in-fifo
|
||||
.Pq Event 33H , Tn Pentium MMX
|
||||
The number of times the D1 stage could issue only one instruction
|
||||
because the FIFO had one instruction ready.
|
||||
This event is only allocated on counter 1.
|
||||
.It Li p5-data-cache-lines-written-back
|
||||
.Pq Event 06H
|
||||
The number of data cache lines that are written back, including
|
||||
those caused by internal and external snoops.
|
||||
.It Li p5-data-cache-tlb-miss-stall-duration
|
||||
.Pq Event 30H , Tn Pentium MMX
|
||||
The number of clocks the pipeline is stalled due to a data cache
|
||||
TLB miss.
|
||||
This event is only allocated on counter 1.
|
||||
.It Li p5-data-read
|
||||
.Pq Event 00H
|
||||
The number of memory data reads, counting internal data cache hits and
|
||||
misses.
|
||||
I/O and data memory accesses due to TLB miss processing are
|
||||
not included.
|
||||
Split cycle reads are counted individually.
|
||||
.It Li p5-data-read-miss
|
||||
.Pq Event 03H
|
||||
The number of memory read accesses that miss the data cache, counting
|
||||
both cacheable and un-cacheable accesses.
|
||||
Data accesses that are part of TLB miss processing are not included.
|
||||
I/O accesses are not included.
|
||||
.It Li p5-data-read-miss-or-write-miss
|
||||
.Pq Event 29H
|
||||
The number of data reads and writes that miss the internal data cache,
|
||||
counting un-cacheable accesses.
|
||||
Data accesses due to TLB miss processing are not counted.
|
||||
.It Li p5-data-read-or-write
|
||||
.Pq Event 28H
|
||||
The number of data reads and writes including internal data cache hits
|
||||
and misses.
|
||||
Data reads due to TLB miss processing are not counted.
|
||||
.It Li p5-data-tlb-miss
|
||||
.Pq Event 02H
|
||||
The number of misses to the data cache translation look aside buffer.
|
||||
.It Li p5-data-write
|
||||
.Pq Event 01H
|
||||
The number of memory data writes, counting internal data cache hits
|
||||
and misses.
|
||||
I/O is not included and split cycle writes are counted individually.
|
||||
.It Li p5-data-write-miss
|
||||
.Pq Event 04H
|
||||
The number of memory write accesses that miss the data cache, counting
|
||||
both cacheable and un-cacheable accesses.
|
||||
I/O accesses are not counted.
|
||||
.It Li p5-emms-instructions-executed
|
||||
.Pq Event 2DH , Tn Pentium MMX
|
||||
The number of EMMS instructions executed.
|
||||
This event is only allocated on counter 0.
|
||||
.It Li p5-external-data-cache-snoop-hits
|
||||
.Pq Event 08H
|
||||
The number of external snoops to the data cache that hit a valid line,
|
||||
or the data line fill buffer, or one of the write back buffers.
|
||||
.It Li p5-external-snoops
|
||||
.Pq Event 07H
|
||||
The number of external snoop requests accepted, including snoops that
|
||||
hit in the code cache, the data cache and that hit in neither.
|
||||
.It Li p5-floating-point-stalls-duration
|
||||
.Pq Event 32H , Tn Pentium MMX
|
||||
The number of cycles the pipeline is stalled due to a floating point
|
||||
freeze.
|
||||
This event is only allocated on counter 0.
|
||||
.It Li p5-flops
|
||||
.Pq Event 22H
|
||||
The number of floating point adds, subtracts, multiples, divides and
|
||||
square roots.
|
||||
Transcendental instructions trigger this event multiple times.
|
||||
Instructions generating divide-by-zero, negative square root, special
|
||||
operand and stack exceptions are not counted.
|
||||
Integer multiply instructions that use the x87 FPU are counted.
|
||||
.It Li p5-full-write-buffer-stall-duration-while-executing-mmx-instructions
|
||||
.Pq Event 3BH , Tn Pentium MMX
|
||||
The number of clocks the pipeline has stalled due to full write
|
||||
buffers when executing MMX instructions.
|
||||
This event is only allocated on counter 0.
|
||||
.It Li p5-hardware-interrupts
|
||||
.Pq Event 27H
|
||||
The number of taken INTR and NMI interrupts.
|
||||
.It Li p5-instructions-executed
|
||||
.Pq Event 16H
|
||||
The number of instructions executed.
|
||||
Repeat prefixed instructions are counted only once.
|
||||
The HLT instruction is counted only once, irrespective of the number
|
||||
of cycles spent in the halted state.
|
||||
All hardware and software exceptions are counted as instructions, and
|
||||
fault handler invocations are also counted as instructions.
|
||||
.It Li p5-instructions-executed-v-pipe
|
||||
.Pq Event 17H
|
||||
The number of instructions that executed in the V pipe.
|
||||
.It Li p5-io-read-or-write-cycle
|
||||
.Pq Event 1DH
|
||||
The number of bus cycles directed to I/O space.
|
||||
.It Li p5-locked-bus-cycle
|
||||
.Pq Event 1CH
|
||||
The number of locked bus cycles that occur on account of the lock
|
||||
prefixes, LOCK instructions, page table updates and descriptor table
|
||||
updates.
|
||||
.It Li p5-memory-accesses-in-both-pipes
|
||||
.Pq Event 09H
|
||||
The number of data memory reads or writes that are paired in both pipes.
|
||||
.It Li p5-misaligned-data-memory-or-io-references
|
||||
.Pq Event 0BH
|
||||
The number of memory or I/O reads or writes that are not aligned on
|
||||
natural boundaries.
|
||||
2- and 4-byte accesses are counted as misaligned if they cross a 4
|
||||
byte boundary.
|
||||
.It Li p5-misaligned-data-memory-reference-on-mmx-instructions
|
||||
.Pq Event 36H , Tn Pentium MMX
|
||||
The number of misaligned data memory references when executing MMX
|
||||
instructions.
|
||||
This event is only allocated on counter 0.
|
||||
.It Li p5-mispredicted-or-unpredicted-returns
|
||||
.Pq Event 37H , Tn Pentium MMX
|
||||
The number of returns predicted incorrectly or not at all, only
|
||||
counting RET instructions.
|
||||
This event is only allocated on counter 0.
|
||||
.It Li p5-mmx-instruction-data-read-misses
|
||||
.Pq Event 31H , Tn Pentium MMX
|
||||
The number of MMX instruction data read misses.
|
||||
This event is only allocated on counter 1.
|
||||
.It Li p5-mmx-instruction-data-reads
|
||||
.Pq Event 31H , Tn Pentium MMX
|
||||
The number of MMX instruction data reads.
|
||||
This event is only allocated on counter 0.
|
||||
.It Li p5-mmx-instruction-data-write-misses
|
||||
.Pq Event 34H , Tn Pentium MMX
|
||||
The number of data write misses caused by MMX instructions.
|
||||
This event is only allocated on counter 1.
|
||||
.It Li p5-mmx-instruction-data-writes
|
||||
.Pq Event 34H , Tn Pentium MMX
|
||||
The number of data writes caused by MMX instructions.
|
||||
This event is only allocated on counter 0.
|
||||
.It Li p5-mmx-instructions-executed-u-pipe
|
||||
.Pq Event 2BH , Tn Pentium MMX
|
||||
The number of MMX instructions executed in the U pipe.
|
||||
This event is only allocated on counter 0.
|
||||
.It Li p5-mmx-instructions-executed-v-pipe
|
||||
.Pq Event 2BH , Tn Pentium MMX
|
||||
The number of MMX instructions executed in the V pipe.
|
||||
This event is only allocated on counter 1.
|
||||
.It Li p5-mmx-multiply-unit-interlock
|
||||
.Pq Event 38H , Tn Pentium MMX
|
||||
The number of clocks the pipeline is stalled because the destination
|
||||
of a prior MMX multiply is not ready.
|
||||
This event is only allocated on counter 0.
|
||||
.It Li p5-movd-movq-store-stall-due-to-previous-mmx-operation
|
||||
.Pq Event 38H , Tn Pentium MMX
|
||||
The number of clocks a MOVD/MOVQ instruction stalled in the D2 stage
|
||||
of the pipeline due to a previous MMX instruction.
|
||||
This event is only allocated on counter 1.
|
||||
.It Li p5-noncacheable-memory-reads
|
||||
.Pq Event 1EH
|
||||
The number of bus cycles for non-cacheable instruction or data reads,
|
||||
including cycles caused by TLB misses.
|
||||
.It Li p5-number-of-cycles-not-in-halt-state
|
||||
.Pq Event 30H , Tn Pentium MMX
|
||||
The number of cycles the processor is not idle due to the HLT
|
||||
instruction.
|
||||
This event is only allocated on counter 0.
|
||||
.It Li p5-pipeline-agi-stalls
|
||||
.Pq Event 1FH
|
||||
The number of address generation interlock stalls.
|
||||
An AGI that occurs in both the U and V pipelines in the same clock
|
||||
signals the event twice.
|
||||
.It Li p5-pipeline-flushes
|
||||
.Pq Event 15H
|
||||
The number of pipeline flushes that occur.
|
||||
Pipeline flushes are caused by branch mispredicts, exceptions,
|
||||
interrupts, some segment register loads, and BTB misses.
|
||||
Prefetch queue flushes due to serializing instructions are not
|
||||
counted.
|
||||
.It Li p5-pipeline-flushes-due-to-wrong-branch-predictions
|
||||
.Pq Event 35H , Tn Pentium MMX
|
||||
The number of pipeline flushes due to wrong branch predictions
|
||||
resolved in either the E- or WB- stage of the pipeline.
|
||||
This event is only allocated on counter 0.
|
||||
.It Li p5-pipeline-flushes-due-to-wrong-branch-predictions-resolved-in-wb-stage
|
||||
.Pq Event 35H , Tn Pentium MMX
|
||||
The number of pipeline flushes due to wrong branch predictions
|
||||
resolved in the stage of the pipeline.
|
||||
This event is only allocated on counter 1.
|
||||
.It Li p5-pipeline-stall-for-mmx-instruction-data-memory-reads
|
||||
.Pq Event 36H , Tn Pentium MMX
|
||||
The number of clocks during pipeline stalls caused by waiting MMX data
|
||||
memory reads.
|
||||
This event is only allocated on counter 1.
|
||||
.It Li p5-predicted-returns
|
||||
.Pq Event 37H , Tn Pentium MMX
|
||||
The number of predicted returns, whether correct or incorrect.
|
||||
This counter only counts RET instructions.
|
||||
This event is only allocated on counter 1.
|
||||
.It Li p5-returns
|
||||
.Pq Event 39H , Tn Pentium MMX
|
||||
The number of RET instructions executed.
|
||||
This event is only allocated on counter 0.
|
||||
.It Li p5-saturating-mmx-instructions-executed
|
||||
.Pq Event 2FH , Tn Pentium MMX
|
||||
The number of saturating MMX instructions executed.
|
||||
This event is only allocated on counter 0.
|
||||
.It Li p5-saturations-performed
|
||||
.Pq Event 2FH , Tn Pentium MMX
|
||||
The number of saturating MMX instructions executed when at least one
|
||||
of its results were actually saturated.
|
||||
This event is only allocated on counter 1.
|
||||
.It Li p5-stall-on-mmx-instruction-write-to-e-o-m-state-line
|
||||
.Pq Event 3BH , Tn Pentium MMX
|
||||
The number of clocks during stalls on MMX instructions writing to
|
||||
E- or M- state cache lines.
|
||||
This event is only allocated on counter 1.
|
||||
.It Li p5-stall-on-write-to-an-e-or-m-state-line
|
||||
.Pq Event 1BH
|
||||
The number of stalls on a write to an exclusive or modified data cache
|
||||
line.
|
||||
.It Li p5-taken-branch-or-btb-hit
|
||||
.Pq Event 14H
|
||||
The number of events that may cause a hit in the BTB, namely either
|
||||
taken branches or BTB hits.
|
||||
.It Li p5-taken-branches
|
||||
.Pq Event 32H , Tn Pentium MMX
|
||||
The number of taken branches.
|
||||
This event is only allocated on counter 1.
|
||||
.It Li p5-transitions-between-mmx-and-fp-instructions
|
||||
.Pq Event 2DH , Tn Pentium MMX
|
||||
The number of transitions between MMX and floating-point instructions
|
||||
and vice-versa.
|
||||
This event is only allocated on counter 1.
|
||||
.It Li p5-waiting-for-data-memory-read-stall-duration
|
||||
.Pq Event 1AH
|
||||
The number of clocks the pipeline was stalled waiting for data
|
||||
memory reads.
|
||||
Data TLB misses processing is included in this count.
|
||||
.It Li p5-write-buffer-full-stall-duration
|
||||
.Pq Event 19H
|
||||
The number of clocks while the pipeline was stalled due to write
|
||||
buffers being full.
|
||||
.It Li p5-write-hit-to-m-or-e-state-lines
|
||||
.Pq Event 05H
|
||||
The number of writes that hit exclusive or modified lines in the data
|
||||
cache.
|
||||
.It Li p5-writes-to-noncacheable-memory
|
||||
.Pq Event 2EH , Tn Pentium MMX
|
||||
The number of writes to non-cacheable memory, including write cycles
|
||||
caused by TLB misses and I/O writes.
|
||||
This event is only allocated on counter 1.
|
||||
.El
|
||||
.Ss Event Name Aliases
|
||||
The following table shows the mapping between the PMC-independent
|
||||
aliases supported by
|
||||
.Lb libpmc
|
||||
and the underlying hardware events used.
|
||||
.Bl -column "branch-mispredicts" "Description"
|
||||
.It Em Alias Ta Em Event
|
||||
.It Li branches Ta Li p5-taken-branches
|
||||
.It Li branch-mispredicts Ta Li (unsupported)
|
||||
.It Li dc-misses Ta Li p5-data-read-miss-or-write-miss
|
||||
.It Li ic-misses Ta Li p5-code-cache-miss
|
||||
.It Li instructions Ta Li p5-instructions-executed
|
||||
.It Li interrupts Ta Li p5-hardware-interrupts
|
||||
.It Li unhalted-cycles Ta Li p5-number-of-cycles-not-in-halt-state
|
||||
.El
|
||||
.Sh SEE ALSO
|
||||
.Xr pmc 3 ,
|
||||
.Xr pmc.atom 3 ,
|
||||
.Xr pmc.core 3 ,
|
||||
.Xr pmc.core2 3 ,
|
||||
.Xr pmc.iaf 3 ,
|
||||
.Xr pmc.k7 3 ,
|
||||
.Xr pmc.k8 3 ,
|
||||
.Xr pmc.p4 3 ,
|
||||
.Xr pmc.p6 3 ,
|
||||
.Xr pmc.soft 3 ,
|
||||
.Xr pmc.tsc 3 ,
|
||||
.Xr pmclog 3 ,
|
||||
.Xr hwpmc 4
|
||||
.Sh HISTORY
|
||||
The
|
||||
.Nm pmc
|
||||
library first appeared in
|
||||
.Fx 6.0 .
|
||||
.Sh AUTHORS
|
||||
The
|
||||
.Lb libpmc
|
||||
library was written by
|
||||
.An Joseph Koshy Aq Mt jkoshy@FreeBSD.org .
|
1026
lib/libpmc/pmc.p6.3
1026
lib/libpmc/pmc.p6.3
File diff suppressed because it is too large
Load diff
|
@ -913,9 +913,6 @@ Split locks in SQ.
|
|||
.Xr pmc.ivybridgexeon 3 ,
|
||||
.Xr pmc.k7 3 ,
|
||||
.Xr pmc.k8 3 ,
|
||||
.Xr pmc.p4 3 ,
|
||||
.Xr pmc.p5 3 ,
|
||||
.Xr pmc.p6 3 ,
|
||||
.Xr pmc.sandybridgeuc 3 ,
|
||||
.Xr pmc.sandybridgexeon 3 ,
|
||||
.Xr pmc.soft 3 ,
|
||||
|
|
|
@ -204,9 +204,6 @@ Counts the number of core-outgoing entries in the coherent tracker queue.
|
|||
.Xr pmc.iaf 3 ,
|
||||
.Xr pmc.k7 3 ,
|
||||
.Xr pmc.k8 3 ,
|
||||
.Xr pmc.p4 3 ,
|
||||
.Xr pmc.p5 3 ,
|
||||
.Xr pmc.p6 3 ,
|
||||
.Xr pmc.sandybridge 3 ,
|
||||
.Xr pmc.sandybridgexeon 3 ,
|
||||
.Xr pmc.soft 3 ,
|
||||
|
|
|
@ -990,9 +990,6 @@ Split locks in SQ.
|
|||
.Xr pmc.ivybridgexeon 3 ,
|
||||
.Xr pmc.k7 3 ,
|
||||
.Xr pmc.k8 3 ,
|
||||
.Xr pmc.p4 3 ,
|
||||
.Xr pmc.p5 3 ,
|
||||
.Xr pmc.p6 3 ,
|
||||
.Xr pmc.sandybridge 3 ,
|
||||
.Xr pmc.sandybridgeuc 3 ,
|
||||
.Xr pmc.soft 3 ,
|
||||
|
|
|
@ -81,9 +81,6 @@ Write page fault.
|
|||
.Xr pmc.iaf 3 ,
|
||||
.Xr pmc.k7 3 ,
|
||||
.Xr pmc.k8 3 ,
|
||||
.Xr pmc.p4 3 ,
|
||||
.Xr pmc.p5 3 ,
|
||||
.Xr pmc.p6 3 ,
|
||||
.Xr pmc.tsc 3 ,
|
||||
.Xr pmc.ucf 3 ,
|
||||
.Xr pmc.westmereuc 3 ,
|
||||
|
|
|
@ -65,9 +65,6 @@ maps to the TSC.
|
|||
.Xr pmc.iaf 3 ,
|
||||
.Xr pmc.k7 3 ,
|
||||
.Xr pmc.k8 3 ,
|
||||
.Xr pmc.p4 3 ,
|
||||
.Xr pmc.p5 3 ,
|
||||
.Xr pmc.p6 3 ,
|
||||
.Xr pmc.soft 3 ,
|
||||
.Xr pmclog 3 ,
|
||||
.Xr hwpmc 4
|
||||
|
|
|
@ -91,9 +91,6 @@ offset C0H under device number 0 and Function 0.
|
|||
.Xr pmc.iaf 3 ,
|
||||
.Xr pmc.k7 3 ,
|
||||
.Xr pmc.k8 3 ,
|
||||
.Xr pmc.p4 3 ,
|
||||
.Xr pmc.p5 3 ,
|
||||
.Xr pmc.p6 3 ,
|
||||
.Xr pmc.soft 3 ,
|
||||
.Xr pmc.tsc 3 ,
|
||||
.Xr pmc.westmere 3 ,
|
||||
|
|
|
@ -1376,9 +1376,6 @@ Counts number of SID integer 64 bit shift or move operations.
|
|||
.Xr pmc.iaf 3 ,
|
||||
.Xr pmc.k7 3 ,
|
||||
.Xr pmc.k8 3 ,
|
||||
.Xr pmc.p4 3 ,
|
||||
.Xr pmc.p5 3 ,
|
||||
.Xr pmc.p6 3 ,
|
||||
.Xr pmc.soft 3 ,
|
||||
.Xr pmc.tsc 3 ,
|
||||
.Xr pmc.ucf 3 ,
|
||||
|
|
|
@ -1080,9 +1080,6 @@ disabled.
|
|||
.Xr pmc.iaf 3 ,
|
||||
.Xr pmc.k7 3 ,
|
||||
.Xr pmc.k8 3 ,
|
||||
.Xr pmc.p4 3 ,
|
||||
.Xr pmc.p5 3 ,
|
||||
.Xr pmc.p6 3 ,
|
||||
.Xr pmc.soft 3 ,
|
||||
.Xr pmc.tsc 3 ,
|
||||
.Xr pmc.ucf 3 ,
|
||||
|
|
Loading…
Reference in a new issue