Upgrade our copies of clang, llvm, lldb and libc++ to r319231 from the

upstream release_50 branch.  This corresponds to 5.0.1 rc2.

MFC after:	2 weeks

ObsoleteFiles.inc

@@ -38,6 +38,123 @@
 #   xargs -n1 | sort | uniq -d;
 # done
 
+# 20171203: new clang import which bumps version from 5.0.0 to 5.0.1.
+OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/allocator_interface.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/asan_interface.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/common_interface_defs.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/coverage_interface.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/dfsan_interface.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/esan_interface.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/linux_syscall_hooks.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/lsan_interface.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/msan_interface.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/tsan_interface.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/tsan_interface_atomic.h
+OLD_DIRS+=usr/lib/clang/5.0.0/include/sanitizer
+OLD_FILES+=usr/lib/clang/5.0.0/include/__clang_cuda_builtin_vars.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/__clang_cuda_cmath.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/__clang_cuda_complex_builtins.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/__clang_cuda_intrinsics.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/__clang_cuda_math_forward_declares.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/__clang_cuda_runtime_wrapper.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/__stddef_max_align_t.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/__wmmintrin_aes.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/__wmmintrin_pclmul.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/adxintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/altivec.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/ammintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/arm_acle.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/arm_neon.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/armintr.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/avx2intrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/avx512bwintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/avx512cdintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/avx512dqintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/avx512erintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/avx512fintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/avx512ifmaintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/avx512ifmavlintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/avx512pfintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/avx512vbmiintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/avx512vbmivlintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/avx512vlbwintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/avx512vlcdintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/avx512vldqintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/avx512vlintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/avx512vpopcntdqintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/avxintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/bmi2intrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/bmiintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/clflushoptintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/clzerointrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/cpuid.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/emmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/f16cintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/fma4intrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/fmaintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/fxsrintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/htmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/htmxlintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/ia32intrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/immintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/lwpintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/lzcntintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/mm3dnow.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/mm_malloc.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/mmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/module.modulemap
+OLD_FILES+=usr/lib/clang/5.0.0/include/msa.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/mwaitxintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/nmmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/opencl-c.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/pkuintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/pmmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/popcntintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/prfchwintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/rdseedintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/rtmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/s390intrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/shaintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/smmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/tbmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/tmmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/vadefs.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/vecintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/wmmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/x86intrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/xmmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/xopintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/xsavecintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/xsaveintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/xsaveoptintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/xsavesintrin.h
+OLD_FILES+=usr/lib/clang/5.0.0/include/xtestintrin.h
+OLD_DIRS+=usr/lib/clang/5.0.0/include
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.asan-i386.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.asan-i386.so
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.asan-preinit-i386.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.asan-preinit-x86_64.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.asan-x86_64.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.asan-x86_64.so
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.asan_cxx-i386.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.asan_cxx-x86_64.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.profile-arm.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.profile-armhf.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.profile-i386.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.profile-x86_64.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.safestack-i386.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.safestack-x86_64.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.stats-i386.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.stats-x86_64.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.stats_client-i386.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.stats_client-x86_64.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.ubsan_standalone-i386.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.ubsan_standalone-x86_64.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.ubsan_standalone_cxx-i386.a
+OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.ubsan_standalone_cxx-x86_64.a
+OLD_DIRS+=usr/lib/clang/5.0.0/lib/freebsd
+OLD_DIRS+=usr/lib/clang/5.0.0/lib
+OLD_DIRS+=usr/lib/clang/5.0.0
 # 20171118: Remove old etc casper files
 OLD_FILES+=etc/casper/system.dns
 OLD_FILES+=etc/casper/system.grp

contrib/libc++/include/algorithm

@@ -3013,6 +3013,7 @@ template<class _Engine, class _UIntType>
 _UIntType
 __independent_bits_engine<_Engine, _UIntType>::__eval(true_type)
 {
+    const size_t _WRt = numeric_limits<result_type>::digits;
     result_type _Sp = 0;
     for (size_t __k = 0; __k < __n0_; ++__k)
     {
@@ -3021,7 +3022,7 @@ __independent_bits_engine<_Engine, _UIntType>::__eval(true_type)
         {
             __u = __e_() - _Engine::min();
         } while (__u >= __y0_);
-        if (__w0_ < _WDt)
+        if (__w0_ < _WRt)
             _Sp <<= __w0_;
         else
             _Sp = 0;
@@ -3034,7 +3035,7 @@ __independent_bits_engine<_Engine, _UIntType>::__eval(true_type)
         {
             __u = __e_() - _Engine::min();
         } while (__u >= __y1_);
-        if (__w0_ < _WDt - 1)
+        if (__w0_ < _WRt - 1)
             _Sp <<= __w0_ + 1;
         else
             _Sp = 0;

contrib/libc++/include/deque

@@ -1356,7 +1356,6 @@ public:
     iterator insert(const_iterator __p, initializer_list<value_type> __il)
         {return insert(__p, __il.begin(), __il.end());}
 #endif  // _LIBCPP_CXX03_LANG
-
     iterator insert(const_iterator __p, const value_type& __v);
     iterator insert(const_iterator __p, size_type __n, const value_type& __v);
     template <class _InputIter>
@@ -2224,7 +2223,11 @@ deque<_Tp, _Allocator>::__append(_InpIter __f, _InpIter __l,
                                                    !__is_forward_iterator<_InpIter>::value>::type*)
 {
     for (; __f != __l; ++__f)
+#ifdef _LIBCPP_CXX03_LANG
         push_back(*__f);
+#else
+        emplace_back(*__f);
+#endif
 }
 
 template <class _Tp, class _Allocator>

contrib/libc++/include/functional

@@ -1597,9 +1597,11 @@ class _LIBCPP_TEMPLATE_VIS function<_Rp(_ArgTypes...)>
       return reinterpret_cast<__base*>(p);
     }
 
-    template <class _Fp, bool = !is_same<_Fp, function>::value &&
+    template <class _Fp, bool = __lazy_and<
-                                __invokable<_Fp&, _ArgTypes...>::value>
+        integral_constant<bool, !is_same<__uncvref_t<_Fp>, function>::value>,
-        struct __callable;
+        __invokable<_Fp&, _ArgTypes...>
+    >::value>
+    struct __callable;
     template <class _Fp>
         struct __callable<_Fp, true>
         {
@@ -1612,6 +1614,9 @@ class _LIBCPP_TEMPLATE_VIS function<_Rp(_ArgTypes...)>
         {
             static const bool value = false;
         };
+
+  template <class _Fp>
+  using _EnableIfCallable = typename enable_if<__callable<_Fp>::value>::type;
 public:
     typedef _Rp result_type;
 
@@ -1622,9 +1627,7 @@ public:
     function(nullptr_t) _NOEXCEPT : __f_(0) {}
     function(const function&);
     function(function&&) _NOEXCEPT;
-    template<class _Fp, class = typename enable_if<
+    template<class _Fp, class = _EnableIfCallable<_Fp>>
-        __callable<_Fp>::value && !is_same<_Fp, function>::value
-    >::type>
     function(_Fp);
 
 #if _LIBCPP_STD_VER <= 14
@@ -1638,21 +1641,15 @@ public:
       function(allocator_arg_t, const _Alloc&, const function&);
     template<class _Alloc>
       function(allocator_arg_t, const _Alloc&, function&&);
-    template<class _Fp, class _Alloc, class = typename enable_if<__callable<_Fp>::value>::type>
+    template<class _Fp, class _Alloc, class = _EnableIfCallable<_Fp>>
       function(allocator_arg_t, const _Alloc& __a, _Fp __f);
 #endif
 
     function& operator=(const function&);
     function& operator=(function&&) _NOEXCEPT;
     function& operator=(nullptr_t) _NOEXCEPT;
-    template<class _Fp>
+    template<class _Fp, class = _EnableIfCallable<_Fp>>
-      typename enable_if
+    function& operator=(_Fp&&);
-      <
-        __callable<typename decay<_Fp>::type>::value &&
-        !is_same<typename remove_reference<_Fp>::type, function>::value,
-        function&
-      >::type
-      operator=(_Fp&&);
 
     ~function();
 
@@ -1854,13 +1851,8 @@ function<_Rp(_ArgTypes...)>::operator=(nullptr_t) _NOEXCEPT
 }
 
 template<class _Rp, class ..._ArgTypes>
-template <class _Fp>
+template <class _Fp, class>
-typename enable_if
+function<_Rp(_ArgTypes...)>&
-<
-    function<_Rp(_ArgTypes...)>::template __callable<typename decay<_Fp>::type>::value &&
-    !is_same<typename remove_reference<_Fp>::type, function<_Rp(_ArgTypes...)>>::value,
-    function<_Rp(_ArgTypes...)>&
->::type
 function<_Rp(_ArgTypes...)>::operator=(_Fp&& __f)
 {
     function(_VSTD::forward<_Fp>(__f)).swap(*this);

contrib/libc++/include/list

@@ -992,6 +992,15 @@ public:
     void push_front(const value_type& __x);
     void push_back(const value_type& __x);
 
+#ifndef _LIBCPP_CXX03_LANG
+    template <class _Arg>
+    _LIBCPP_INLINE_VISIBILITY
+    void __emplace_back(_Arg&& __arg) { emplace_back(_VSTD::forward<_Arg>(__arg)); }
+#else
+    _LIBCPP_INLINE_VISIBILITY
+    void __emplace_back(value_type const& __arg) { push_back(__arg); }
+#endif
+
     iterator insert(const_iterator __p, const value_type& __x);
     iterator insert(const_iterator __p, size_type __n, const value_type& __x);
     template <class _InpIter>
@@ -1189,7 +1198,7 @@ list<_Tp, _Alloc>::list(_InpIter __f, _InpIter __l,
     __get_db()->__insert_c(this);
 #endif
     for (; __f != __l; ++__f)
-        push_back(*__f);
+        __emplace_back(*__f);
 }
 
 template <class _Tp, class _Alloc>
@@ -1202,7 +1211,7 @@ list<_Tp, _Alloc>::list(_InpIter __f, _InpIter __l, const allocator_type& __a,
     __get_db()->__insert_c(this);
 #endif
     for (; __f != __l; ++__f)
-        push_back(*__f);
+        __emplace_back(*__f);
 }
 
 template <class _Tp, class _Alloc>

contrib/libc++/include/string

@@ -259,7 +259,7 @@ public:
     size_type find(value_type c, size_type pos = 0) const noexcept;
 
     size_type rfind(const basic_string& str, size_type pos = npos) const noexcept;
-    size_type ffind(basic_string_view<charT, traits> sv, size_type pos = 0) const noexcept;
+    size_type rfind(basic_string_view<charT, traits> sv, size_type pos = npos) const noexcept;
     size_type rfind(const value_type* s, size_type pos, size_type n) const noexcept;
     size_type rfind(const value_type* s, size_type pos = npos) const noexcept;
     size_type rfind(value_type c, size_type pos = npos) const noexcept;
@@ -271,7 +271,7 @@ public:
     size_type find_first_of(value_type c, size_type pos = 0) const noexcept;
 
     size_type find_last_of(const basic_string& str, size_type pos = npos) const noexcept;
-    size_type find_last_of(basic_string_view<charT, traits> sv, size_type pos = 0) const noexcept;
+    size_type find_last_of(basic_string_view<charT, traits> sv, size_type pos = npos) const noexcept;
     size_type find_last_of(const value_type* s, size_type pos, size_type n) const noexcept;
     size_type find_last_of(const value_type* s, size_type pos = npos) const noexcept;
     size_type find_last_of(value_type c, size_type pos = npos) const noexcept;
@@ -283,7 +283,7 @@ public:
     size_type find_first_not_of(value_type c, size_type pos = 0) const noexcept;
 
     size_type find_last_not_of(const basic_string& str, size_type pos = npos) const noexcept;
-    size_type find_last_not_of(basic_string_view<charT, traits> sv, size_type pos = 0) const noexcept;
+    size_type find_last_not_of(basic_string_view<charT, traits> sv, size_type pos = npos) const noexcept;
     size_type find_last_not_of(const value_type* s, size_type pos, size_type n) const noexcept;
     size_type find_last_not_of(const value_type* s, size_type pos = npos) const noexcept;
     size_type find_last_not_of(value_type c, size_type pos = npos) const noexcept;
@@ -1147,7 +1147,7 @@ public:
     _LIBCPP_INLINE_VISIBILITY
     size_type rfind(const basic_string& __str, size_type __pos = npos) const _NOEXCEPT;
     _LIBCPP_INLINE_VISIBILITY
-    size_type rfind(__self_view __sv, size_type __pos = 0) const _NOEXCEPT;
+    size_type rfind(__self_view __sv, size_type __pos = npos) const _NOEXCEPT;
     size_type rfind(const value_type* __s, size_type __pos, size_type __n) const _NOEXCEPT;
     _LIBCPP_INLINE_VISIBILITY
     size_type rfind(const value_type* __s, size_type __pos = npos) const _NOEXCEPT;
@@ -1166,7 +1166,7 @@ public:
     _LIBCPP_INLINE_VISIBILITY
     size_type find_last_of(const basic_string& __str, size_type __pos = npos) const _NOEXCEPT;
     _LIBCPP_INLINE_VISIBILITY
-    size_type find_last_of(__self_view __sv, size_type __pos = 0) const _NOEXCEPT;
+    size_type find_last_of(__self_view __sv, size_type __pos = npos) const _NOEXCEPT;
     size_type find_last_of(const value_type* __s, size_type __pos, size_type __n) const _NOEXCEPT;
     _LIBCPP_INLINE_VISIBILITY
     size_type find_last_of(const value_type* __s, size_type __pos = npos) const _NOEXCEPT;
@@ -1186,7 +1186,7 @@ public:
     _LIBCPP_INLINE_VISIBILITY
     size_type find_last_not_of(const basic_string& __str, size_type __pos = npos) const _NOEXCEPT;
     _LIBCPP_INLINE_VISIBILITY
-    size_type find_last_not_of(__self_view __sv, size_type __pos = 0) const _NOEXCEPT;
+    size_type find_last_not_of(__self_view __sv, size_type __pos = npos) const _NOEXCEPT;
     size_type find_last_not_of(const value_type* __s, size_type __pos, size_type __n) const _NOEXCEPT;
     _LIBCPP_INLINE_VISIBILITY
     size_type find_last_not_of(const value_type* __s, size_type __pos = npos) const _NOEXCEPT;

contrib/libc++/include/type_traits

@@ -4339,8 +4339,8 @@ struct __invokable_r
     using _Result = decltype(
         _VSTD::__invoke(_VSTD::declval<_Fp>(), _VSTD::declval<_Args>()...));
 
-    static const bool value =
+    using type =
-        conditional<
+        typename conditional<
             !is_same<_Result, __nat>::value,
             typename conditional<
                 is_void<_Ret>::value,
@@ -4348,7 +4348,8 @@ struct __invokable_r
                 is_convertible<_Result, _Ret>
             >::type,
             false_type
-        >::type::value;
+        >::type;
+    static const bool value = type::value;
 };
 
 template <class _Fp, class ..._Args>

contrib/libc++/include/vector

@@ -674,6 +674,17 @@ public:
     const value_type* data() const _NOEXCEPT
         {return _VSTD::__to_raw_pointer(this->__begin_);}
 
+#ifdef _LIBCPP_CXX03_LANG
+    _LIBCPP_INLINE_VISIBILITY
+    void __emplace_back(const value_type& __x) { push_back(__x); }
+#else
+    template <class _Arg>
+    _LIBCPP_INLINE_VISIBILITY
+    void __emplace_back(_Arg&& __arg) {
+      emplace_back(_VSTD::forward<_Arg>(__arg));
+    }
+#endif
+
     _LIBCPP_INLINE_VISIBILITY void push_back(const_reference __x);
 
 #ifndef _LIBCPP_CXX03_LANG
@@ -1128,7 +1139,7 @@ vector<_Tp, _Allocator>::vector(_InputIterator __first,
     __get_db()->__insert_c(this);
 #endif
     for (; __first != __last; ++__first)
-        push_back(*__first);
+        __emplace_back(*__first);
 }
 
 template <class _Tp, class _Allocator>
@@ -1145,7 +1156,7 @@ vector<_Tp, _Allocator>::vector(_InputIterator __first, _InputIterator __last, c
     __get_db()->__insert_c(this);
 #endif
     for (; __first != __last; ++__first)
-        push_back(*__first);
+        __emplace_back(*__first);
 }
 
 template <class _Tp, class _Allocator>
@@ -1365,7 +1376,7 @@ vector<_Tp, _Allocator>::assign(_InputIterator __first, _InputIterator __last)
 {
     clear();
     for (; __first != __last; ++__first)
-        push_back(*__first);
+        __emplace_back(*__first);
 }
 
 template <class _Tp, class _Allocator>

contrib/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

@@ -652,6 +652,12 @@ class TargetTransformInfoImplCRTPBase : public TargetTransformInfoImplBase {
 
     auto GTI = gep_type_begin(PointeeType, Operands);
     Type *TargetType;
+
+    // Handle the case where the GEP instruction has a single operand,
+    // the basis, therefore TargetType is a nullptr.
+    if (Operands.empty())
+      return !BaseGV ? TTI::TCC_Free : TTI::TCC_Basic;
+
     for (auto I = Operands.begin(); I != Operands.end(); ++I, ++GTI) {
       TargetType = GTI.getIndexedType();
       // We assume that the cost of Scalar GEP with constant index and the

contrib/llvm/include/llvm/CodeGen/MachineRegisterInfo.h

@@ -807,6 +807,14 @@ class MachineRegisterInfo {
     return getReservedRegs().test(PhysReg);
   }
 
+  /// Returns true when the given register unit is considered reserved.
+  ///
+  /// Register units are considered reserved when for at least one of their
+  /// root registers, the root register and all super registers are reserved.
+  /// This currently iterates the register hierarchy and may be slower than
+  /// expected.
+  bool isReservedRegUnit(unsigned Unit) const;
+
   /// isAllocatable - Returns true when PhysReg belongs to an allocatable
   /// register class and it hasn't been reserved.
   ///

contrib/llvm/include/llvm/IR/AutoUpgrade.h

@@ -51,6 +51,8 @@ namespace llvm {
   /// module is modified.
   bool UpgradeModuleFlags(Module &M);
 
+  void UpgradeSectionAttributes(Module &M);
+
   /// If the given TBAA tag uses the scalar TBAA format, create a new node
   /// corresponding to the upgrade to the struct-path aware TBAA format.
   /// Otherwise return the \p TBAANode itself.

contrib/llvm/include/llvm/Support/FormatVariadic.h

@@ -94,6 +94,15 @@ class formatv_object_base {
     Adapters.reserve(ParamCount);
   }
 
+  formatv_object_base(formatv_object_base const &rhs) = delete;
+
+  formatv_object_base(formatv_object_base &&rhs)
+      : Fmt(std::move(rhs.Fmt)),
+        Adapters(), // Adapters are initialized by formatv_object
+        Replacements(std::move(rhs.Replacements)) {
+    Adapters.reserve(rhs.Adapters.size());
+  };
+
   void format(raw_ostream &S) const {
     for (auto &R : Replacements) {
       if (R.Type == ReplacementType::Empty)
@@ -149,6 +158,14 @@ template <typename Tuple> class formatv_object : public formatv_object_base {
         Parameters(std::move(Params)) {
     Adapters = apply_tuple(create_adapters(), Parameters);
   }
+
+  formatv_object(formatv_object const &rhs) = delete;
+
+  formatv_object(formatv_object &&rhs)
+      : formatv_object_base(std::move(rhs)),
+        Parameters(std::move(rhs.Parameters)) {
+    Adapters = apply_tuple(create_adapters(), Parameters);
+  }
 };
 
 // \brief Format text given a format string and replacement parameters.

contrib/llvm/lib/AsmParser/LLParser.cpp

@@ -240,6 +240,7 @@ bool LLParser::ValidateEndOfModule() {
   UpgradeDebugInfo(*M);
 
   UpgradeModuleFlags(*M);
+  UpgradeSectionAttributes(*M);
 
   if (!Slots)
     return false;

contrib/llvm/lib/Bitcode/Reader/BitcodeReader.cpp

@@ -264,7 +264,7 @@ Expected<bool> hasObjCCategoryInModule(BitstreamCursor &Stream) {
       if (convertToString(Record, 0, S))
         return error("Invalid record");
       // Check for the i386 and other (x86_64, ARM) conventions
-      if (S.find("__DATA, __objc_catlist") != std::string::npos ||
+      if (S.find("__DATA,__objc_catlist") != std::string::npos ||
           S.find("__OBJC,__category") != std::string::npos)
         return true;
       break;

contrib/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp

@@ -621,6 +621,7 @@ void DwarfCompileUnit::constructAbstractSubprogramScopeDIE(
   auto *SP = cast<DISubprogram>(Scope->getScopeNode());
 
   DIE *ContextDIE;
+  DwarfCompileUnit *ContextCU = this;
 
   if (includeMinimalInlineScopes())
     ContextDIE = &getUnitDie();
@@ -631,18 +632,23 @@ void DwarfCompileUnit::constructAbstractSubprogramScopeDIE(
   else if (auto *SPDecl = SP->getDeclaration()) {
     ContextDIE = &getUnitDie();
     getOrCreateSubprogramDIE(SPDecl);
-  } else
+  } else {
     ContextDIE = getOrCreateContextDIE(resolve(SP->getScope()));
+    // The scope may be shared with a subprogram that has already been
+    // constructed in another CU, in which case we need to construct this
+    // subprogram in the same CU.
+    ContextCU = DD->lookupCU(ContextDIE->getUnitDie());
+  }
 
   // Passing null as the associated node because the abstract definition
   // shouldn't be found by lookup.
-  AbsDef = &createAndAddDIE(dwarf::DW_TAG_subprogram, *ContextDIE, nullptr);
+  AbsDef = &ContextCU->createAndAddDIE(dwarf::DW_TAG_subprogram, *ContextDIE, nullptr);
-  applySubprogramAttributesToDefinition(SP, *AbsDef);
+  ContextCU->applySubprogramAttributesToDefinition(SP, *AbsDef);
 
-  if (!includeMinimalInlineScopes())
+  if (!ContextCU->includeMinimalInlineScopes())
-    addUInt(*AbsDef, dwarf::DW_AT_inline, None, dwarf::DW_INL_inlined);
+    ContextCU->addUInt(*AbsDef, dwarf::DW_AT_inline, None, dwarf::DW_INL_inlined);
-  if (DIE *ObjectPointer = createAndAddScopeChildren(Scope, *AbsDef))
+  if (DIE *ObjectPointer = ContextCU->createAndAddScopeChildren(Scope, *AbsDef))
-    addDIEEntry(*AbsDef, dwarf::DW_AT_object_pointer, *ObjectPointer);
+    ContextCU->addDIEEntry(*AbsDef, dwarf::DW_AT_object_pointer, *ObjectPointer);
 }
 
 DIE *DwarfCompileUnit::constructImportedEntityDIE(

contrib/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h

@@ -283,7 +283,7 @@ class DwarfDebug : public DebugHandlerBase {
   // 0, referencing the comp_dir of all the type units that use it.
   MCDwarfDwoLineTable SplitTypeUnitFileTable;
   /// @}
-  
+
   /// True iff there are multiple CUs in this module.
   bool SingleCU;
   bool IsDarwin;
@@ -562,6 +562,9 @@ class DwarfDebug : public DebugHandlerBase {
   bool isLexicalScopeDIENull(LexicalScope *Scope);
 
   bool hasDwarfPubSections(bool includeMinimalInlineScopes) const;
+
+  /// Find the matching DwarfCompileUnit for the given CU DIE.
+  DwarfCompileUnit *lookupCU(const DIE *Die) { return CUDieMap.lookup(Die); }
 };
 } // End of namespace llvm
 

contrib/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp

@@ -131,13 +131,12 @@ bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
 
     // Intersection between the bits we already emitted and the bits
     // covered by this subregister.
-    SmallBitVector Intersection(RegSize, false);
+    SmallBitVector CurSubReg(RegSize, false);
-    Intersection.set(Offset, Offset + Size);
+    CurSubReg.set(Offset, Offset + Size);
-    Intersection ^= Coverage;
 
     // If this sub-register has a DWARF number and we haven't covered
     // its range, emit a DWARF piece for it.
-    if (Reg >= 0 && Intersection.any()) {
+    if (Reg >= 0 && CurSubReg.test(Coverage)) {
       // Emit a piece for any gap in the coverage.
       if (Offset > CurPos)
         DwarfRegs.push_back({-1, Offset - CurPos, nullptr});

contrib/llvm/lib/CodeGen/LiveIntervalAnalysis.cpp

@@ -269,8 +269,9 @@ void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
   // may share super-registers. That's OK because createDeadDefs() is
   // idempotent. It is very rare for a register unit to have multiple roots, so
   // uniquing super-registers is probably not worthwhile.
-  bool IsReserved = true;
+  bool IsReserved = false;
   for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
+    bool IsRootReserved = true;
     for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
          Super.isValid(); ++Super) {
       unsigned Reg = *Super;
@@ -279,9 +280,12 @@ void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
       // A register unit is considered reserved if all its roots and all their
       // super registers are reserved.
       if (!MRI->isReserved(Reg))
-        IsReserved = false;
+        IsRootReserved = false;
     }
+    IsReserved |= IsRootReserved;
   }
+  assert(IsReserved == MRI->isReservedRegUnit(Unit) &&
+         "reserved computation mismatch");
 
   // Now extend LR to reach all uses.
   // Ignore uses of reserved registers. We only track defs of those.
@@ -924,7 +928,7 @@ class LiveIntervals::HMEditor {
   // kill flags. This is wasteful. Eventually, LiveVariables will strip all kill
   // flags, and postRA passes will use a live register utility instead.
   LiveRange *getRegUnitLI(unsigned Unit) {
-    if (UpdateFlags)
+    if (UpdateFlags && !MRI.isReservedRegUnit(Unit))
       return &LIS.getRegUnit(Unit);
     return LIS.getCachedRegUnit(Unit);
   }

contrib/llvm/lib/CodeGen/MachineRegisterInfo.cpp

@@ -601,3 +601,21 @@ void MachineRegisterInfo::setCalleeSavedRegs(ArrayRef<MCPhysReg> CSRs) {
   UpdatedCSRs.push_back(0);
   IsUpdatedCSRsInitialized = true;
 }
+
+bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const {
+  const TargetRegisterInfo *TRI = getTargetRegisterInfo();
+  for (MCRegUnitRootIterator Root(Unit, TRI); Root.isValid(); ++Root) {
+    bool IsRootReserved = true;
+    for (MCSuperRegIterator Super(*Root, TRI, /*IncludeSelf=*/true);
+         Super.isValid(); ++Super) {
+      unsigned Reg = *Super;
+      if (!isReserved(Reg)) {
+        IsRootReserved = false;
+        break;
+      }
+    }
+    if (IsRootReserved)
+      return true;
+  }
+  return false;
+}

contrib/llvm/lib/CodeGen/MachineVerifier.cpp

@@ -1316,6 +1316,8 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
       // Check the cached regunit intervals.
       if (TargetRegisterInfo::isPhysicalRegister(Reg) && !isReserved(Reg)) {
         for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units) {
+          if (MRI->isReservedRegUnit(*Units))
+            continue;
           if (const LiveRange *LR = LiveInts->getCachedRegUnit(*Units))
             checkLivenessAtUse(MO, MONum, UseIdx, *LR, *Units);
         }

contrib/llvm/lib/IR/AutoUpgrade.cpp

@@ -2271,6 +2271,24 @@ bool llvm::UpgradeModuleFlags(Module &M) {
         }
       }
     }
+    // Upgrade Objective-C Image Info Section. Removed the whitespce in the
+    // section name so that llvm-lto will not complain about mismatching
+    // module flags that is functionally the same.
+    if (ID->getString() == "Objective-C Image Info Section") {
+      if (auto *Value = dyn_cast_or_null<MDString>(Op->getOperand(2))) {
+        SmallVector<StringRef, 4> ValueComp;
+        Value->getString().split(ValueComp, " ");
+        if (ValueComp.size() != 1) {
+          std::string NewValue;
+          for (auto &S : ValueComp)
+            NewValue += S.str();
+          Metadata *Ops[3] = {Op->getOperand(0), Op->getOperand(1),
+                              MDString::get(M.getContext(), NewValue)};
+          ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops));
+          Changed = true;
+        }
+      }
+    }
   }
 
   // "Objective-C Class Properties" is recently added for Objective-C. We
@@ -2287,6 +2305,35 @@ bool llvm::UpgradeModuleFlags(Module &M) {
   return Changed;
 }
 
+void llvm::UpgradeSectionAttributes(Module &M) {
+  auto TrimSpaces = [](StringRef Section) -> std::string {
+    SmallVector<StringRef, 5> Components;
+    Section.split(Components, ',');
+
+    SmallString<32> Buffer;
+    raw_svector_ostream OS(Buffer);
+
+    for (auto Component : Components)
+      OS << ',' << Component.trim();
+
+    return OS.str().substr(1);
+  };
+
+  for (auto &GV : M.globals()) {
+    if (!GV.hasSection())
+      continue;
+
+    StringRef Section = GV.getSection();
+
+    if (!Section.startswith("__DATA, __objc_catlist"))
+      continue;
+
+    // __DATA, __objc_catlist, regular, no_dead_strip
+    // __DATA,__objc_catlist,regular,no_dead_strip
+    GV.setSection(TrimSpaces(Section));
+  }
+}
+
 static bool isOldLoopArgument(Metadata *MD) {
   auto *T = dyn_cast_or_null<MDTuple>(MD);
   if (!T)

contrib/llvm/lib/IR/ConstantFold.cpp

@@ -2199,6 +2199,9 @@ Constant *llvm::ConstantFoldGetElementPtr(Type *PointeeTy, Constant *C,
       Unknown = true;
       continue;
     }
+    if (!isa<ConstantInt>(Idxs[i - 1]))
+      // FIXME: add the support of cosntant vector index.
+      continue;
     if (InRangeIndex && i == *InRangeIndex + 1) {
       // If an index is marked inrange, we cannot apply this canonicalization to
       // the following index, as that will cause the inrange index to point to

contrib/llvm/lib/Linker/IRMover.cpp

@@ -640,6 +640,10 @@ GlobalValue *IRLinker::copyGlobalValueProto(const GlobalValue *SGV,
   } else {
     if (ForDefinition)
       NewGV = copyGlobalAliasProto(cast<GlobalAlias>(SGV));
+    else if (SGV->getValueType()->isFunctionTy())
+      NewGV =
+          Function::Create(cast<FunctionType>(TypeMap.get(SGV->getValueType())),
+                           GlobalValue::ExternalLinkage, SGV->getName(), &DstM);
     else
       NewGV = new GlobalVariable(
           DstM, TypeMap.get(SGV->getValueType()),

contrib/llvm/lib/Linker/LinkModules.cpp

@@ -329,8 +329,18 @@ bool ModuleLinker::shouldLinkFromSource(bool &LinkFromSrc,
 bool ModuleLinker::linkIfNeeded(GlobalValue &GV) {
   GlobalValue *DGV = getLinkedToGlobal(&GV);
 
-  if (shouldLinkOnlyNeeded() && !(DGV && DGV->isDeclaration()))
+  if (shouldLinkOnlyNeeded()) {
-    return false;
+    // Always import variables with appending linkage.
+    if (!GV.hasAppendingLinkage()) {
+      // Don't import globals unless they are referenced by the destination
+      // module.
+      if (!DGV)
+        return false;
+      // Don't import globals that are already defined in the destination module
+      if (!DGV->isDeclaration())
+        return false;
+    }
+  }
 
   if (DGV && !GV.hasLocalLinkage() && !GV.hasAppendingLinkage()) {
     auto *DGVar = dyn_cast<GlobalVariable>(DGV);

contrib/llvm/lib/Support/Host.cpp

@@ -208,6 +208,7 @@ StringRef sys::detail::getHostCPUNameForARM(
             .Case("0x06f", "krait") // APQ8064
             .Case("0x201", "kryo")
             .Case("0x205", "kryo")
+            .Case("0xc00", "falkor")
             .Default("generic");
 
   return "generic";

contrib/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp

@@ -220,27 +220,27 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
   default:
     return None;
 
-  case AArch64::LD1i8:
-  case AArch64::LD1i16:
-  case AArch64::LD1i32:
   case AArch64::LD1i64:
-  case AArch64::LD2i8:
-  case AArch64::LD2i16:
-  case AArch64::LD2i32:
   case AArch64::LD2i64:
-  case AArch64::LD3i8:
-  case AArch64::LD3i16:
-  case AArch64::LD3i32:
-  case AArch64::LD4i8:
-  case AArch64::LD4i16:
-  case AArch64::LD4i32:
     DestRegIdx = 0;
     BaseRegIdx = 3;
     OffsetIdx = -1;
     IsPrePost = false;
     break;
 
+  case AArch64::LD1i8:
+  case AArch64::LD1i16:
+  case AArch64::LD1i32:
+  case AArch64::LD2i8:
+  case AArch64::LD2i16:
+  case AArch64::LD2i32:
+  case AArch64::LD3i8:
+  case AArch64::LD3i16:
+  case AArch64::LD3i32:
   case AArch64::LD3i64:
+  case AArch64::LD4i8:
+  case AArch64::LD4i16:
+  case AArch64::LD4i32:
   case AArch64::LD4i64:
     DestRegIdx = -1;
     BaseRegIdx = 3;
@@ -264,23 +264,16 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
   case AArch64::LD1Rv4s:
   case AArch64::LD1Rv8h:
   case AArch64::LD1Rv16b:
-  case AArch64::LD1Twov1d:
-  case AArch64::LD1Twov2s:
-  case AArch64::LD1Twov4h:
-  case AArch64::LD1Twov8b:
-  case AArch64::LD2Twov2s:
-  case AArch64::LD2Twov4s:
-  case AArch64::LD2Twov8b:
-  case AArch64::LD2Rv1d:
-  case AArch64::LD2Rv2s:
-  case AArch64::LD2Rv4s:
-  case AArch64::LD2Rv8b:
     DestRegIdx = 0;
     BaseRegIdx = 1;
     OffsetIdx = -1;
     IsPrePost = false;
     break;
 
+  case AArch64::LD1Twov1d:
+  case AArch64::LD1Twov2s:
+  case AArch64::LD1Twov4h:
+  case AArch64::LD1Twov8b:
   case AArch64::LD1Twov2d:
   case AArch64::LD1Twov4s:
   case AArch64::LD1Twov8h:
@@ -301,10 +294,17 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
   case AArch64::LD1Fourv4s:
   case AArch64::LD1Fourv8h:
   case AArch64::LD1Fourv16b:
+  case AArch64::LD2Twov2s:
+  case AArch64::LD2Twov4s:
+  case AArch64::LD2Twov8b:
   case AArch64::LD2Twov2d:
   case AArch64::LD2Twov4h:
   case AArch64::LD2Twov8h:
   case AArch64::LD2Twov16b:
+  case AArch64::LD2Rv1d:
+  case AArch64::LD2Rv2s:
+  case AArch64::LD2Rv4s:
+  case AArch64::LD2Rv8b:
   case AArch64::LD2Rv2d:
   case AArch64::LD2Rv4h:
   case AArch64::LD2Rv8h:
@@ -345,32 +345,32 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
     IsPrePost = false;
     break;
 
-  case AArch64::LD1i8_POST:
-  case AArch64::LD1i16_POST:
-  case AArch64::LD1i32_POST:
   case AArch64::LD1i64_POST:
-  case AArch64::LD2i8_POST:
-  case AArch64::LD2i16_POST:
-  case AArch64::LD2i32_POST:
   case AArch64::LD2i64_POST:
-  case AArch64::LD3i8_POST:
-  case AArch64::LD3i16_POST:
-  case AArch64::LD3i32_POST:
-  case AArch64::LD4i8_POST:
-  case AArch64::LD4i16_POST:
-  case AArch64::LD4i32_POST:
     DestRegIdx = 1;
     BaseRegIdx = 4;
     OffsetIdx = 5;
-    IsPrePost = false;
+    IsPrePost = true;
     break;
 
+  case AArch64::LD1i8_POST:
+  case AArch64::LD1i16_POST:
+  case AArch64::LD1i32_POST:
+  case AArch64::LD2i8_POST:
+  case AArch64::LD2i16_POST:
+  case AArch64::LD2i32_POST:
+  case AArch64::LD3i8_POST:
+  case AArch64::LD3i16_POST:
+  case AArch64::LD3i32_POST:
   case AArch64::LD3i64_POST:
+  case AArch64::LD4i8_POST:
+  case AArch64::LD4i16_POST:
+  case AArch64::LD4i32_POST:
   case AArch64::LD4i64_POST:
     DestRegIdx = -1;
     BaseRegIdx = 4;
     OffsetIdx = 5;
-    IsPrePost = false;
+    IsPrePost = true;
     break;
 
   case AArch64::LD1Onev1d_POST:
@@ -389,23 +389,16 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
   case AArch64::LD1Rv4s_POST:
   case AArch64::LD1Rv8h_POST:
   case AArch64::LD1Rv16b_POST:
+    DestRegIdx = 1;
+    BaseRegIdx = 2;
+    OffsetIdx = 3;
+    IsPrePost = true;
+    break;
+
   case AArch64::LD1Twov1d_POST:
   case AArch64::LD1Twov2s_POST:
   case AArch64::LD1Twov4h_POST:
   case AArch64::LD1Twov8b_POST:
-  case AArch64::LD2Twov2s_POST:
-  case AArch64::LD2Twov4s_POST:
-  case AArch64::LD2Twov8b_POST:
-  case AArch64::LD2Rv1d_POST:
-  case AArch64::LD2Rv2s_POST:
-  case AArch64::LD2Rv4s_POST:
-  case AArch64::LD2Rv8b_POST:
-    DestRegIdx = 1;
-    BaseRegIdx = 2;
-    OffsetIdx = 3;
-    IsPrePost = false;
-    break;
-
   case AArch64::LD1Twov2d_POST:
   case AArch64::LD1Twov4s_POST:
   case AArch64::LD1Twov8h_POST:
@@ -426,10 +419,17 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
   case AArch64::LD1Fourv4s_POST:
   case AArch64::LD1Fourv8h_POST:
   case AArch64::LD1Fourv16b_POST:
+  case AArch64::LD2Twov2s_POST:
+  case AArch64::LD2Twov4s_POST:
+  case AArch64::LD2Twov8b_POST:
   case AArch64::LD2Twov2d_POST:
   case AArch64::LD2Twov4h_POST:
   case AArch64::LD2Twov8h_POST:
   case AArch64::LD2Twov16b_POST:
+  case AArch64::LD2Rv1d_POST:
+  case AArch64::LD2Rv2s_POST:
+  case AArch64::LD2Rv4s_POST:
+  case AArch64::LD2Rv8b_POST:
   case AArch64::LD2Rv2d_POST:
   case AArch64::LD2Rv4h_POST:
   case AArch64::LD2Rv8h_POST:
@@ -467,7 +467,7 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
     DestRegIdx = -1;
     BaseRegIdx = 2;
     OffsetIdx = 3;
-    IsPrePost = false;
+    IsPrePost = true;
     break;
 
   case AArch64::LDRBBroW:
@@ -572,8 +572,12 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
     IsPrePost = true;
     break;
 
-  case AArch64::LDPDi:
+  case AArch64::LDNPDi:
+  case AArch64::LDNPQi:
+  case AArch64::LDNPSi:
   case AArch64::LDPQi:
+  case AArch64::LDPDi:
+  case AArch64::LDPSi:
     DestRegIdx = -1;
     BaseRegIdx = 2;
     OffsetIdx = 3;
@@ -581,7 +585,6 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
     break;
 
   case AArch64::LDPSWi:
-  case AArch64::LDPSi:
   case AArch64::LDPWi:
   case AArch64::LDPXi:
     DestRegIdx = 0;
@@ -592,18 +595,18 @@ static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
 
   case AArch64::LDPQpost:
   case AArch64::LDPQpre:
+  case AArch64::LDPDpost:
+  case AArch64::LDPDpre:
+  case AArch64::LDPSpost:
+  case AArch64::LDPSpre:
     DestRegIdx = -1;
     BaseRegIdx = 3;
     OffsetIdx = 4;
     IsPrePost = true;
     break;
 
-  case AArch64::LDPDpost:
-  case AArch64::LDPDpre:
   case AArch64::LDPSWpost:
   case AArch64::LDPSWpre:
-  case AArch64::LDPSpost:
-  case AArch64::LDPSpre:
   case AArch64::LDPWpost:
   case AArch64::LDPWpre:
   case AArch64::LDPXpost:
@@ -687,9 +690,14 @@ void FalkorHWPFFix::runOnLoop(MachineLoop &L, MachineFunction &Fn) {
       if (!TII->isStridedAccess(MI))
         continue;
 
-      LoadInfo LdI = *getLoadInfo(MI);
+      Optional<LoadInfo> OptLdI = getLoadInfo(MI);
-      unsigned OldTag = *getTag(TRI, MI, LdI);
+      if (!OptLdI)
-      auto &OldCollisions = TagMap[OldTag];
+        continue;
+      LoadInfo LdI = *OptLdI;
+      Optional<unsigned> OptOldTag = getTag(TRI, MI, LdI);
+      if (!OptOldTag)
+        continue;
+      auto &OldCollisions = TagMap[*OptOldTag];
       if (OldCollisions.size() <= 1)
         continue;
 

contrib/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -9347,11 +9347,20 @@ static SDValue replaceZeroVectorStore(SelectionDAG &DAG, StoreSDNode &St) {
       return SDValue();
   }
 
-  // Use WZR/XZR here to prevent DAGCombiner::MergeConsecutiveStores from
+  // Use a CopyFromReg WZR/XZR here to prevent
-  // undoing this transformation.
+  // DAGCombiner::MergeConsecutiveStores from undoing this transformation.
-  SDValue SplatVal = VT.getVectorElementType().getSizeInBits() == 32
+  SDLoc DL(&St);
-                         ? DAG.getRegister(AArch64::WZR, MVT::i32)
+  unsigned ZeroReg;
-                         : DAG.getRegister(AArch64::XZR, MVT::i64);
+  EVT ZeroVT;
+  if (VT.getVectorElementType().getSizeInBits() == 32) {
+    ZeroReg = AArch64::WZR;
+    ZeroVT = MVT::i32;
+  } else {
+    ZeroReg = AArch64::XZR;
+    ZeroVT = MVT::i64;
+  }
+  SDValue SplatVal =
+      DAG.getCopyFromReg(DAG.getEntryNode(), DL, ZeroReg, ZeroVT);
   return splitStoreSplat(DAG, St, SplatVal, NumVecElts);
 }
 

contrib/llvm/lib/Target/AArch64/AArch64InstrInfo.td

@@ -441,8 +441,7 @@ def MSRpstateImm1 : MSRpstateImm0_1;
 def MSRpstateImm4 : MSRpstateImm0_15;
 
 // The thread pointer (on Linux, at least, where this has been implemented) is
-// TPIDR_EL0.  Add pseudo op so we can mark it as not having any side effects.
+// TPIDR_EL0.
-let hasSideEffects = 0 in
 def MOVbaseTLS : Pseudo<(outs GPR64:$dst), (ins),
                        [(set GPR64:$dst, AArch64threadpointer)]>, Sched<[WriteSys]>;
 

contrib/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

@@ -218,12 +218,17 @@ void GCNHazardRecognizer::RecedeCycle() {
 
 int GCNHazardRecognizer::getWaitStatesSince(
     function_ref<bool(MachineInstr *)> IsHazard) {
-  int WaitStates = -1;
+  int WaitStates = 0;
   for (MachineInstr *MI : EmittedInstrs) {
+    if (MI) {
+      if (IsHazard(MI))
+        return WaitStates;
+
+      unsigned Opcode = MI->getOpcode();
+      if (Opcode == AMDGPU::DBG_VALUE || Opcode == AMDGPU::IMPLICIT_DEF)
+        continue;
+    }
     ++WaitStates;
-    if (!MI || !IsHazard(MI))
-      continue;
-    return WaitStates;
   }
   return std::numeric_limits<int>::max();
 }

contrib/llvm/lib/Target/ARM/ARMAsmPrinter.cpp

@@ -1276,6 +1276,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
       // Add 's' bit operand (always reg0 for this)
       .addReg(0));
 
+    assert(Subtarget->hasV4TOps());
     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
       .addReg(MI->getOperand(0).getReg()));
     return;
@@ -1896,6 +1897,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
       .addImm(ARMCC::AL)
       .addReg(0));
 
+    assert(Subtarget->hasV4TOps());
     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
       .addReg(ScratchReg)
       // Predicate.

contrib/llvm/lib/Target/ARM/ARMCallLowering.cpp

@@ -251,7 +251,9 @@ bool ARMCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
                                   const Value *Val, unsigned VReg) const {
   assert(!Val == !VReg && "Return value without a vreg");
 
-  auto Ret = MIRBuilder.buildInstrNoInsert(ARM::BX_RET).add(predOps(ARMCC::AL));
+  auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>();
+  unsigned Opcode = ST.getReturnOpcode();
+  auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL));
 
   if (!lowerReturnVal(MIRBuilder, Val, VReg, Ret))
     return false;

contrib/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

@@ -1030,8 +1030,11 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
         if (STI->isThumb())
           MIB.add(predOps(ARMCC::AL));
       } else if (RetOpcode == ARM::TCRETURNri) {
+        unsigned Opcode =
+          STI->isThumb() ? ARM::tTAILJMPr
+                         : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4);
         BuildMI(MBB, MBBI, dl,
-                TII.get(STI->isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr))
+                TII.get(Opcode))
             .addReg(JumpTarget.getReg(), RegState::Kill);
       }
 

contrib/llvm/lib/Target/ARM/ARMFastISel.cpp

@@ -1332,6 +1332,8 @@ bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
   if (AddrReg == 0) return false;
 
   unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
+  assert(isThumb2 || Subtarget->hasV4TOps());
+
   AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
                           TII.get(Opc)).addReg(AddrReg));
 
@@ -2168,9 +2170,8 @@ bool ARMFastISel::SelectRet(const Instruction *I) {
     RetRegs.push_back(VA.getLocReg());
   }
 
-  unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
   MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
-                                    TII.get(RetOpc));
+                                    TII.get(Subtarget->getReturnOpcode()));
   AddOptionalDefs(MIB);
   for (unsigned R : RetRegs)
     MIB.addReg(R, RegState::Implicit);

contrib/llvm/lib/Target/ARM/ARMFrameLowering.cpp

@@ -479,7 +479,7 @@ void ARMFrameLowering::emitPrologue(MachineFunction &MF,
   if (DPRCSSize > 0) {
     // Since vpush register list cannot have gaps, there may be multiple vpush
     // instructions in the prologue.
-    while (MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
+    while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::VSTMDDB_UPD) {
       DefCFAOffsetCandidates.addInst(MBBI, sizeOfSPAdjustment(*MBBI));
       LastPush = MBBI++;
     }
@@ -2397,9 +2397,8 @@ void ARMFrameLowering::adjustForSegmentedStacks(
   BuildMI(AllocMBB, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
       .addCFIIndex(CFIIndex);
 
-  // bx lr - Return from this function.
+  // Return from this function.
-  Opcode = Thumb ? ARM::tBX_RET : ARM::BX_RET;
+  BuildMI(AllocMBB, DL, TII.get(ST->getReturnOpcode())).add(predOps(ARMCC::AL));
-  BuildMI(AllocMBB, DL, TII.get(Opcode)).add(predOps(ARMCC::AL));
 
   // Restore SR0 and SR1 in case of __morestack() was not called.
   // pop {SR0, SR1}

contrib/llvm/lib/Target/ARM/ARMInstrInfo.td

@@ -2425,7 +2425,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
   def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
                                  4, IIC_Br, [],
                                  (BX GPR:$dst)>, Sched<[WriteBr]>,
-                                 Requires<[IsARM]>;
+                                 Requires<[IsARM, HasV4T]>;
 }
 
 // Secure Monitor Call is a system instruction.
@@ -5589,6 +5589,12 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
                     (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
                   Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
 
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in
+  def TAILJMPr4 : ARMPseudoExpand<(outs), (ins GPR:$dst),
+                    4, IIC_Br, [],
+                    (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
+                  Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
+
 // Large immediate handling.
 
 // 32-bit immediate using two piece mod_imms or movw + movt.

contrib/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

@@ -1909,6 +1909,7 @@ bool ARMLoadStoreOpt::CombineMovBx(MachineBasicBlock &MBB) {
 
   for (auto Use : Prev->uses())
     if (Use.isKill()) {
+      assert(STI->hasV4TOps());
       BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::tBX))
           .addReg(Use.getReg(), RegState::Kill)
           .add(predOps(ARMCC::AL))

contrib/llvm/lib/Target/ARM/ARMSubtarget.h

@@ -729,6 +729,17 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
 
   /// True if fast-isel is used.
   bool useFastISel() const;
+
+  /// Returns the correct return opcode for the current feature set.
+  /// Use BX if available to allow mixing thumb/arm code, but fall back
+  /// to plain mov pc,lr on ARMv4.
+  unsigned getReturnOpcode() const {
+    if (isThumb())
+      return ARM::tBX_RET;
+    if (hasV4TOps())
+      return ARM::BX_RET;
+    return ARM::MOVPCLR;
+  }
 };
 
 } // end namespace llvm

contrib/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp

@@ -142,9 +142,9 @@ std::string ARM_MC::ParseARMTriple(const Triple &TT, StringRef CPU) {
 
   if (isThumb) {
     if (ARMArchFeature.empty())
-      ARMArchFeature = "+thumb-mode";
+      ARMArchFeature = "+thumb-mode,+v4t";
     else
-      ARMArchFeature += ",+thumb-mode";
+      ARMArchFeature += ",+thumb-mode,+v4t";
   }
 
   if (TT.isOSNaCl()) {

contrib/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp

@@ -583,8 +583,8 @@ bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {
   unsigned TmpReg = 0; // 0 for no temporary register
   unsigned SrcReg = MI.getOperand(1).getReg();
   bool SrcIsKill = MI.getOperand(1).isKill();
-  OpLo = AVR::LDRdPtr;
+  OpLo = AVR::LDRdPtrPi;
-  OpHi = AVR::LDDRdPtrQ;
+  OpHi = AVR::LDRdPtr;
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
   // Use a temporary register if src and dst registers are the same.
@@ -597,6 +597,7 @@ bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {
   // Load low byte.
   auto MIBLO = buildMI(MBB, MBBI, OpLo)
     .addReg(CurDstLoReg, RegState::Define)
+    .addReg(SrcReg, RegState::Define)
     .addReg(SrcReg);
 
   // Push low byte onto stack if necessary.
@@ -606,8 +607,7 @@ bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {
   // Load high byte.
   auto MIBHI = buildMI(MBB, MBBI, OpHi)
     .addReg(CurDstHiReg, RegState::Define)
-    .addReg(SrcReg, getKillRegState(SrcIsKill))
+    .addReg(SrcReg, getKillRegState(SrcIsKill));
-    .addImm(1);
 
   if (TmpReg) {
     // Move the high byte into the final destination.
@@ -699,7 +699,9 @@ bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
   OpHi = AVR::LDDRdPtrQ;
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
-  assert(Imm <= 63 && "Offset is out of range");
+  // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
+  // allowed for the instruction, 62 is the limit here.
+  assert(Imm <= 62 && "Offset is out of range");
 
   // Use a temporary register if src and dst registers are the same.
   if (DstReg == SrcReg)
@@ -741,7 +743,50 @@ bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
 
 template <>
 bool AVRExpandPseudo::expand<AVR::LPMWRdZ>(Block &MBB, BlockIt MBBI) {
-  llvm_unreachable("wide LPM is unimplemented");
+  MachineInstr &MI = *MBBI;
+  unsigned OpLo, OpHi, DstLoReg, DstHiReg;
+  unsigned DstReg = MI.getOperand(0).getReg();
+  unsigned TmpReg = 0; // 0 for no temporary register
+  unsigned SrcReg = MI.getOperand(1).getReg();
+  bool SrcIsKill = MI.getOperand(1).isKill();
+  OpLo = AVR::LPMRdZPi;
+  OpHi = AVR::LPMRdZ;
+  TRI->splitReg(DstReg, DstLoReg, DstHiReg);
+
+  // Use a temporary register if src and dst registers are the same.
+  if (DstReg == SrcReg)
+    TmpReg = scavengeGPR8(MI);
+
+  unsigned CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;
+  unsigned CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;
+
+  // Load low byte.
+  auto MIBLO = buildMI(MBB, MBBI, OpLo)
+      .addReg(CurDstLoReg, RegState::Define)
+      .addReg(SrcReg);
+
+  // Push low byte onto stack if necessary.
+  if (TmpReg)
+    buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
+
+  // Load high byte.
+  auto MIBHI = buildMI(MBB, MBBI, OpHi)
+      .addReg(CurDstHiReg, RegState::Define)
+      .addReg(SrcReg, getKillRegState(SrcIsKill));
+
+  if (TmpReg) {
+    // Move the high byte into the final destination.
+    buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg);
+
+    // Move the low byte from the scratch space into the final destination.
+    buildMI(MBB, MBBI, AVR::POPRd).addReg(DstLoReg);
+  }
+
+  MIBLO->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
+  MIBHI->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
+
+  MI.eraseFromParent();
+  return true;
 }
 
 template <>
@@ -1074,7 +1119,9 @@ bool AVRExpandPseudo::expand<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
   OpHi = AVR::STDPtrQRr;
   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
 
-  assert(Imm <= 63 && "Offset is out of range");
+  // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
+  // allowed for the instruction, 62 is the limit here.
+  assert(Imm <= 62 && "Offset is out of range");
 
   auto MIBLO = buildMI(MBB, MBBI, OpLo)
     .addReg(DstReg)
@@ -1104,7 +1151,9 @@ bool AVRExpandPseudo::expand<AVR::INWRdA>(Block &MBB, BlockIt MBBI) {
   OpHi = AVR::INRdA;
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
-  assert(Imm <= 63 && "Address is out of range");
+  // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
+  // allowed for the instruction, 62 is the limit here.
+  assert(Imm <= 62 && "Address is out of range");
 
   auto MIBLO = buildMI(MBB, MBBI, OpLo)
     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
@@ -1132,7 +1181,9 @@ bool AVRExpandPseudo::expand<AVR::OUTWARr>(Block &MBB, BlockIt MBBI) {
   OpHi = AVR::OUTARr;
   TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
 
-  assert(Imm <= 63 && "Address is out of range");
+  // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
+  // allowed for the instruction, 62 is the limit here.
+  assert(Imm <= 62 && "Address is out of range");
 
   // 16 bit I/O writes need the high byte first
   auto MIBHI = buildMI(MBB, MBBI, OpHi)

contrib/llvm/lib/Target/AVR/AVRISelLowering.cpp

@@ -1469,8 +1469,10 @@ MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
   }
 
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
-  MachineFunction::iterator I = BB->getParent()->begin();
+
-  ++I;
+  MachineFunction::iterator I;
+  for (I = F->begin(); I != F->end() && &(*I) != BB; ++I);
+  if (I != F->end()) ++I;
 
   // Create loop block.
   MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);

contrib/llvm/lib/Target/AVR/AVRISelLowering.h

@@ -75,6 +75,11 @@ class AVRTargetLowering : public TargetLowering {
   MVT getScalarShiftAmountTy(const DataLayout &, EVT LHSTy) const override {
     return MVT::i8;
   }
+
+  MVT::SimpleValueType getCmpLibcallReturnType() const override {
+    return MVT::i8;
+  }
+
   const char *getTargetNodeName(unsigned Opcode) const override;
 
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;

contrib/llvm/lib/Target/AVR/AVRInstrInfo.cpp

@@ -537,8 +537,7 @@ bool AVRInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
     llvm_unreachable("unexpected opcode!");
   case AVR::JMPk:
   case AVR::CALLk:
-    assert(BrOffset >= 0 && "offset must be absolute address");
+    return true;
-    return isUIntN(16, BrOffset);
   case AVR::RCALLk:
   case AVR::RJMPk:
     return isIntN(13, BrOffset);
@@ -556,5 +555,20 @@ bool AVRInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
   }
 }
 
+unsigned AVRInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
+                                            MachineBasicBlock &NewDestBB,
+                                            const DebugLoc &DL,
+                                            int64_t BrOffset,
+                                            RegScavenger *RS) const {
+    // This method inserts a *direct* branch (JMP), despite its name.
+    // LLVM calls this method to fixup unconditional branches; it never calls
+    // insertBranch or some hypothetical "insertDirectBranch".
+    // See lib/CodeGen/RegisterRelaxation.cpp for details.
+    // We end up here when a jump is too long for a RJMP instruction.
+    auto &MI = *BuildMI(&MBB, DL, get(AVR::JMPk)).addMBB(&NewDestBB);
+
+    return getInstSizeInBytes(MI);
+}
+
 } // end of namespace llvm
 

contrib/llvm/lib/Target/AVR/AVRInstrInfo.h

@@ -107,6 +107,12 @@ class AVRInstrInfo : public AVRGenInstrInfo {
 
   bool isBranchOffsetInRange(unsigned BranchOpc,
                              int64_t BrOffset) const override;
+
+  unsigned insertIndirectBranch(MachineBasicBlock &MBB,
+                                MachineBasicBlock &NewDestBB,
+                                const DebugLoc &DL,
+                                int64_t BrOffset,
+                                RegScavenger *RS) const override;
 private:
   const AVRRegisterInfo RI;
 };

contrib/llvm/lib/Target/AVR/AVRInstrInfo.td

@@ -1152,10 +1152,10 @@ isReMaterializable = 1 in
   //
   // Expands to:
   // ld Rd,   P+
-  // ld Rd+1, P+
+  // ld Rd+1, P
   let Constraints = "@earlyclobber $reg" in
   def LDWRdPtr : Pseudo<(outs DREGS:$reg),
-                        (ins PTRDISPREGS:$ptrreg),
+                        (ins PTRREGS:$ptrreg),
                         "ldw\t$reg, $ptrreg",
                         [(set i16:$reg, (load i16:$ptrreg))]>,
                  Requires<[HasSRAM]>;
@@ -1164,7 +1164,7 @@ isReMaterializable = 1 in
 // Indirect loads (with postincrement or predecrement).
 let mayLoad = 1,
 hasSideEffects = 0,
-Constraints = "$ptrreg = $base_wb,@earlyclobber $reg,@earlyclobber $base_wb" in
+Constraints = "$ptrreg = $base_wb,@earlyclobber $reg" in
 {
   def LDRdPtrPi : FSTLD<0,
                         0b01,
@@ -1238,35 +1238,55 @@ isReMaterializable = 1 in
                  Requires<[HasSRAM]>;
 }
 
-class AtomicLoad<PatFrag Op, RegisterClass DRC> :
+class AtomicLoad<PatFrag Op, RegisterClass DRC,
-  Pseudo<(outs DRC:$rd), (ins PTRREGS:$rr), "atomic_op",
+                 RegisterClass PTRRC> :
+  Pseudo<(outs DRC:$rd), (ins PTRRC:$rr), "atomic_op",
          [(set DRC:$rd, (Op i16:$rr))]>;
 
-class AtomicStore<PatFrag Op, RegisterClass DRC> :
+class AtomicStore<PatFrag Op, RegisterClass DRC,
-  Pseudo<(outs), (ins PTRDISPREGS:$rd, DRC:$rr), "atomic_op",
+                  RegisterClass PTRRC> :
+  Pseudo<(outs), (ins PTRRC:$rd, DRC:$rr), "atomic_op",
          [(Op i16:$rd, DRC:$rr)]>;
 
-class AtomicLoadOp<PatFrag Op, RegisterClass DRC> :
+class AtomicLoadOp<PatFrag Op, RegisterClass DRC,
-  Pseudo<(outs DRC:$rd), (ins PTRREGS:$rr, DRC:$operand),
+                   RegisterClass PTRRC> :
+  Pseudo<(outs DRC:$rd), (ins PTRRC:$rr, DRC:$operand),
          "atomic_op",
          [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>;
 
-def AtomicLoad8   : AtomicLoad<atomic_load_8, GPR8>;
+// FIXME: I think 16-bit atomic binary ops need to mark
-def AtomicLoad16  : AtomicLoad<atomic_load_16, DREGS>;
+// r0 as clobbered.
 
-def AtomicStore8  : AtomicStore<atomic_store_8, GPR8>;
+// Atomic instructions
-def AtomicStore16 : AtomicStore<atomic_store_16, DREGS>;
+// ===================
+//
+// These are all expanded by AVRExpandPseudoInsts
+//
+// 8-bit operations can use any pointer register because
+// they are expanded directly into an LD/ST instruction.
+//
+// 16-bit operations use 16-bit load/store postincrement instructions,
+// which require PTRDISPREGS.
 
-def AtomicLoadAdd8  : AtomicLoadOp<atomic_load_add_8, GPR8>;
+def AtomicLoad8   : AtomicLoad<atomic_load_8, GPR8, PTRREGS>;
-def AtomicLoadAdd16 : AtomicLoadOp<atomic_load_add_16, DREGS>;
+def AtomicLoad16  : AtomicLoad<atomic_load_16, DREGS, PTRDISPREGS>;
-def AtomicLoadSub8  : AtomicLoadOp<atomic_load_sub_8, GPR8>;
+
-def AtomicLoadSub16 : AtomicLoadOp<atomic_load_sub_16, DREGS>;
+def AtomicStore8  : AtomicStore<atomic_store_8, GPR8, PTRREGS>;
-def AtomicLoadAnd8  : AtomicLoadOp<atomic_load_and_8, GPR8>;
+def AtomicStore16 : AtomicStore<atomic_store_16, DREGS, PTRDISPREGS>;
-def AtomicLoadAnd16 : AtomicLoadOp<atomic_load_and_16, DREGS>;
+
-def AtomicLoadOr8   : AtomicLoadOp<atomic_load_or_8, GPR8>;
+class AtomicLoadOp8<PatFrag Op> : AtomicLoadOp<Op, GPR8, PTRREGS>;
-def AtomicLoadOr16  : AtomicLoadOp<atomic_load_or_16, DREGS>;
+class AtomicLoadOp16<PatFrag Op> : AtomicLoadOp<Op, DREGS, PTRDISPREGS>;
-def AtomicLoadXor8  : AtomicLoadOp<atomic_load_xor_8, GPR8>;
+
-def AtomicLoadXor16 : AtomicLoadOp<atomic_load_xor_16, DREGS>;
+def AtomicLoadAdd8  : AtomicLoadOp8<atomic_load_add_8>;
+def AtomicLoadAdd16 : AtomicLoadOp16<atomic_load_add_16>;
+def AtomicLoadSub8  : AtomicLoadOp8<atomic_load_sub_8>;
+def AtomicLoadSub16 : AtomicLoadOp16<atomic_load_sub_16>;
+def AtomicLoadAnd8  : AtomicLoadOp8<atomic_load_and_8>;
+def AtomicLoadAnd16 : AtomicLoadOp16<atomic_load_and_16>;
+def AtomicLoadOr8   : AtomicLoadOp8<atomic_load_or_8>;
+def AtomicLoadOr16  : AtomicLoadOp16<atomic_load_or_16>;
+def AtomicLoadXor8  : AtomicLoadOp8<atomic_load_xor_8>;
+def AtomicLoadXor16 : AtomicLoadOp16<atomic_load_xor_16>;
 def AtomicFence     : Pseudo<(outs), (ins), "atomic_fence",
                              [(atomic_fence imm, imm)]>;
 
@@ -1397,6 +1417,7 @@ def STDWPtrQRr : Pseudo<(outs),
 // Load program memory operations.
 let canFoldAsLoad = 1,
 isReMaterializable = 1,
+mayLoad = 1,
 hasSideEffects = 0 in
 {
   let Defs = [R0],
@@ -1417,8 +1438,7 @@ hasSideEffects = 0 in
                Requires<[HasLPMX]>;
 
   // Load program memory, while postincrementing the Z register.
-  let mayLoad = 1,
+  let Defs = [R31R30] in
-  Defs = [R31R30] in
   {
     def LPMRdZPi : FLPMX<0,
                          1,

contrib/llvm/lib/Target/AVR/AVRRegisterInfo.cpp

@@ -203,7 +203,7 @@ void AVRRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   // If the offset is too big we have to adjust and restore the frame pointer
   // to materialize a valid load/store with displacement.
   //:TODO: consider using only one adiw/sbiw chain for more than one frame index
-  if (Offset > 63) {
+  if (Offset > 62) {
     unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK;
     int AddOffset = Offset - 63 + 1;
 

contrib/llvm/lib/Target/AVR/AVRTargetMachine.cpp

@@ -25,7 +25,7 @@
 
 namespace llvm {
 
-static const char *AVRDataLayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-n8";
+static const char *AVRDataLayout = "e-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8";
 
 /// Processes a CPU name.
 static StringRef getCPU(StringRef CPU) {

contrib/llvm/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.cpp

@@ -13,6 +13,8 @@
 
 #include "AVRTargetStreamer.h"
 
+#include "llvm/MC/MCContext.h"
+
 namespace llvm {
 
 AVRTargetStreamer::AVRTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
@@ -20,5 +22,23 @@ AVRTargetStreamer::AVRTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
 AVRTargetAsmStreamer::AVRTargetAsmStreamer(MCStreamer &S)
     : AVRTargetStreamer(S) {}
 
+void AVRTargetStreamer::finish() {
+  MCStreamer &OS = getStreamer();
+  MCContext &Context = OS.getContext();
+
+  MCSymbol *DoCopyData = Context.getOrCreateSymbol("__do_copy_data");
+  MCSymbol *DoClearBss = Context.getOrCreateSymbol("__do_clear_bss");
+
+  // FIXME: We can disable __do_copy_data if there are no static RAM variables.
+
+  OS.emitRawComment(" Declaring this symbol tells the CRT that it should");
+  OS.emitRawComment("copy all variables from program memory to RAM on startup");
+  OS.EmitSymbolAttribute(DoCopyData, MCSA_Global);
+
+  OS.emitRawComment(" Declaring this symbol tells the CRT that it should");
+  OS.emitRawComment("clear the zeroed data section on startup");
+  OS.EmitSymbolAttribute(DoClearBss, MCSA_Global);
+}
+
 } // end namespace llvm
 

contrib/llvm/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.h

@@ -19,6 +19,8 @@ class MCStreamer;
 class AVRTargetStreamer : public MCTargetStreamer {
 public:
   explicit AVRTargetStreamer(MCStreamer &S);
+
+  void finish() override;
 };
 
 /// A target streamer for textual AVR assembly code.

contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

@@ -304,6 +304,9 @@ class MipsAsmParser : public MCTargetAsmParser {
   bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
                   const MCSubtargetInfo *STI);
 
+  bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+                       const MCSubtargetInfo *STI);
+
   bool reportParseError(Twine ErrorMsg);
   bool reportParseError(SMLoc Loc, Twine ErrorMsg);
 
@@ -2511,6 +2514,16 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
     return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
   case Mips::SEQIMacro:
     return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
+  case Mips::MFTC0:   case Mips::MTTC0:
+  case Mips::MFTGPR:  case Mips::MTTGPR:
+  case Mips::MFTLO:   case Mips::MTTLO:
+  case Mips::MFTHI:   case Mips::MTTHI:
+  case Mips::MFTACX:  case Mips::MTTACX:
+  case Mips::MFTDSP:  case Mips::MTTDSP:
+  case Mips::MFTC1:   case Mips::MTTC1:
+  case Mips::MFTHC1:  case Mips::MTTHC1:
+  case Mips::CFTC1:   case Mips::CTTC1:
+    return expandMXTRAlias(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
   }
 }
 
@@ -4882,6 +4895,212 @@ bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
   return false;
 }
 
+// Map the DSP accumulator and control register to the corresponding gpr
+// operand. Unlike the other alias, the m(f|t)t(lo|hi|acx) instructions
+// do not map the DSP registers contigously to gpr registers.
+static unsigned getRegisterForMxtrDSP(MCInst &Inst, bool IsMFDSP) {
+  switch (Inst.getOpcode()) {
+    case Mips::MFTLO:
+    case Mips::MTTLO:
+      switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
+        case Mips::AC0:
+          return Mips::ZERO;
+        case Mips::AC1:
+          return Mips::A0;
+        case Mips::AC2:
+          return Mips::T0;
+        case Mips::AC3:
+          return Mips::T4;
+        default:
+          llvm_unreachable("Unknown register for 'mttr' alias!");
+    }
+    case Mips::MFTHI:
+    case Mips::MTTHI:
+      switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
+        case Mips::AC0:
+          return Mips::AT;
+        case Mips::AC1:
+          return Mips::A1;
+        case Mips::AC2:
+          return Mips::T1;
+        case Mips::AC3:
+          return Mips::T5;
+        default:
+          llvm_unreachable("Unknown register for 'mttr' alias!");
+    }
+    case Mips::MFTACX:
+    case Mips::MTTACX:
+      switch (Inst.getOperand(IsMFDSP ? 1 : 0).getReg()) {
+        case Mips::AC0:
+          return Mips::V0;
+        case Mips::AC1:
+          return Mips::A2;
+        case Mips::AC2:
+          return Mips::T2;
+        case Mips::AC3:
+          return Mips::T6;
+        default:
+          llvm_unreachable("Unknown register for 'mttr' alias!");
+    }
+    case Mips::MFTDSP:
+    case Mips::MTTDSP:
+      return Mips::S0;
+    default:
+      llvm_unreachable("Unknown instruction for 'mttr' dsp alias!");
+  }
+}
+
+// Map the floating point register operand to the corresponding register
+// operand.
+static unsigned getRegisterForMxtrFP(MCInst &Inst, bool IsMFTC1) {
+  switch (Inst.getOperand(IsMFTC1 ? 1 : 0).getReg()) {
+    case Mips::F0:  return Mips::ZERO;
+    case Mips::F1:  return Mips::AT;
+    case Mips::F2:  return Mips::V0;
+    case Mips::F3:  return Mips::V1;
+    case Mips::F4:  return Mips::A0;
+    case Mips::F5:  return Mips::A1;
+    case Mips::F6:  return Mips::A2;
+    case Mips::F7:  return Mips::A3;
+    case Mips::F8:  return Mips::T0;
+    case Mips::F9:  return Mips::T1;
+    case Mips::F10: return Mips::T2;
+    case Mips::F11: return Mips::T3;
+    case Mips::F12: return Mips::T4;
+    case Mips::F13: return Mips::T5;
+    case Mips::F14: return Mips::T6;
+    case Mips::F15: return Mips::T7;
+    case Mips::F16: return Mips::S0;
+    case Mips::F17: return Mips::S1;
+    case Mips::F18: return Mips::S2;
+    case Mips::F19: return Mips::S3;
+    case Mips::F20: return Mips::S4;
+    case Mips::F21: return Mips::S5;
+    case Mips::F22: return Mips::S6;
+    case Mips::F23: return Mips::S7;
+    case Mips::F24: return Mips::T8;
+    case Mips::F25: return Mips::T9;
+    case Mips::F26: return Mips::K0;
+    case Mips::F27: return Mips::K1;
+    case Mips::F28: return Mips::GP;
+    case Mips::F29: return Mips::SP;
+    case Mips::F30: return Mips::FP;
+    case Mips::F31: return Mips::RA;
+    default: llvm_unreachable("Unknown register for mttc1 alias!");
+  }
+}
+
+// Map the coprocessor operand the corresponding gpr register operand.
+static unsigned getRegisterForMxtrC0(MCInst &Inst, bool IsMFTC0) {
+  switch (Inst.getOperand(IsMFTC0 ? 1 : 0).getReg()) {
+    case Mips::COP00:  return Mips::ZERO;
+    case Mips::COP01:  return Mips::AT;
+    case Mips::COP02:  return Mips::V0;
+    case Mips::COP03:  return Mips::V1;
+    case Mips::COP04:  return Mips::A0;
+    case Mips::COP05:  return Mips::A1;
+    case Mips::COP06:  return Mips::A2;
+    case Mips::COP07:  return Mips::A3;
+    case Mips::COP08:  return Mips::T0;
+    case Mips::COP09:  return Mips::T1;
+    case Mips::COP010: return Mips::T2;
+    case Mips::COP011: return Mips::T3;
+    case Mips::COP012: return Mips::T4;
+    case Mips::COP013: return Mips::T5;
+    case Mips::COP014: return Mips::T6;
+    case Mips::COP015: return Mips::T7;
+    case Mips::COP016: return Mips::S0;
+    case Mips::COP017: return Mips::S1;
+    case Mips::COP018: return Mips::S2;
+    case Mips::COP019: return Mips::S3;
+    case Mips::COP020: return Mips::S4;
+    case Mips::COP021: return Mips::S5;
+    case Mips::COP022: return Mips::S6;
+    case Mips::COP023: return Mips::S7;
+    case Mips::COP024: return Mips::T8;
+    case Mips::COP025: return Mips::T9;
+    case Mips::COP026: return Mips::K0;
+    case Mips::COP027: return Mips::K1;
+    case Mips::COP028: return Mips::GP;
+    case Mips::COP029: return Mips::SP;
+    case Mips::COP030: return Mips::FP;
+    case Mips::COP031: return Mips::RA;
+    default: llvm_unreachable("Unknown register for mttc0 alias!");
+  }
+}
+
+/// Expand an alias of 'mftr' or 'mttr' into the full instruction, by producing
+/// an mftr or mttr with the correctly mapped gpr register, u, sel and h bits.
+bool MipsAsmParser::expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
+                                    const MCSubtargetInfo *STI) {
+  MipsTargetStreamer &TOut = getTargetStreamer();
+  unsigned rd = 0;
+  unsigned u = 1;
+  unsigned sel = 0;
+  unsigned h = 0;
+  bool IsMFTR = false;
+  switch (Inst.getOpcode()) {
+    case Mips::MFTC0:
+      IsMFTR = true;
+      LLVM_FALLTHROUGH;
+    case Mips::MTTC0:
+      u = 0;
+      rd = getRegisterForMxtrC0(Inst, IsMFTR);
+      sel = Inst.getOperand(2).getImm();
+      break;
+    case Mips::MFTGPR:
+      IsMFTR = true;
+      LLVM_FALLTHROUGH;
+    case Mips::MTTGPR:
+      rd = Inst.getOperand(IsMFTR ? 1 : 0).getReg();
+      break;
+    case Mips::MFTLO:
+    case Mips::MFTHI:
+    case Mips::MFTACX:
+    case Mips::MFTDSP:
+      IsMFTR = true;
+      LLVM_FALLTHROUGH;
+    case Mips::MTTLO:
+    case Mips::MTTHI:
+    case Mips::MTTACX:
+    case Mips::MTTDSP:
+      rd = getRegisterForMxtrDSP(Inst, IsMFTR);
+      sel = 1;
+      break;
+    case Mips::MFTHC1:
+      h = 1;
+      LLVM_FALLTHROUGH;
+    case Mips::MFTC1:
+      IsMFTR = true;
+      rd = getRegisterForMxtrFP(Inst, IsMFTR);
+      sel = 2;
+      break;
+    case Mips::MTTHC1:
+      h = 1;
+      LLVM_FALLTHROUGH;
+    case Mips::MTTC1:
+      rd = getRegisterForMxtrFP(Inst, IsMFTR);
+      sel = 2;
+      break;
+    case Mips::CFTC1:
+      IsMFTR = true;
+      LLVM_FALLTHROUGH;
+    case Mips::CTTC1:
+      rd = getRegisterForMxtrFP(Inst, IsMFTR);
+      sel = 3;
+      break;
+  }
+  unsigned Op0 = IsMFTR ? Inst.getOperand(0).getReg() : rd;
+  unsigned Op1 =
+      IsMFTR ? rd
+             : (Inst.getOpcode() != Mips::MTTDSP ? Inst.getOperand(1).getReg()
+                                                 : Inst.getOperand(0).getReg());
+
+  TOut.emitRRIII(IsMFTR ? Mips::MFTR : Mips::MTTR, Op0, Op1, u, sel, h, IDLoc,
+                 STI);
+  return false;
+}
+
 unsigned
 MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst,
                                               const OperandVector &Operands) {
@@ -5793,14 +6012,21 @@ OperandMatchResultTy
 MipsAsmParser::parseInvNum(OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
   const MCExpr *IdVal;
-  // If the first token is '$' we may have register operand.
+  // If the first token is '$' we may have register operand. We have to reject
-  if (Parser.getTok().is(AsmToken::Dollar))
+  // cases where it is not a register. Complicating the matter is that
-    return MatchOperand_NoMatch;
+  // register names are not reserved across all ABIs.
+  // Peek past the dollar to see if it's a register name for this ABI.
   SMLoc S = Parser.getTok().getLoc();
+  if (Parser.getTok().is(AsmToken::Dollar)) {
+    return matchCPURegisterName(Parser.getLexer().peekTok().getString()) == -1
+               ? MatchOperand_ParseFail
+               : MatchOperand_NoMatch;
+  }
   if (getParser().parseExpression(IdVal))
     return MatchOperand_ParseFail;
   const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal);
-  assert(MCE && "Unexpected MCExpr type.");
+  if (!MCE)
+    return MatchOperand_NoMatch;
   int64_t Val = MCE->getValue();
   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
   Operands.push_back(MipsOperand::CreateImm(

contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp

@@ -246,8 +246,6 @@ void MipsMCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {
     break;
   case MEK_CALL_HI16:
   case MEK_CALL_LO16:
-  case MEK_DTPREL_HI:
-  case MEK_DTPREL_LO:
   case MEK_GOT:
   case MEK_GOT_CALL:
   case MEK_GOT_DISP:
@@ -263,14 +261,16 @@ void MipsMCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {
   case MEK_NEG:
   case MEK_PCREL_HI16:
   case MEK_PCREL_LO16:
-  case MEK_TLSLDM:
     // If we do have nested target-specific expressions, they will be in
     // a consecutive chain.
     if (const MipsMCExpr *E = dyn_cast<const MipsMCExpr>(getSubExpr()))
       E->fixELFSymbolsInTLSFixups(Asm);
     break;
-  case MEK_GOTTPREL:
+  case MEK_DTPREL_HI:
+  case MEK_DTPREL_LO:
+  case MEK_TLSLDM:
   case MEK_TLSGD:
+  case MEK_GOTTPREL:
   case MEK_TPREL_HI:
   case MEK_TPREL_LO:
     fixELFSymbolsInTLSFixupsImpl(getSubExpr(), Asm);

contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

@@ -193,6 +193,21 @@ void MipsTargetStreamer::emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1,
   emitRRX(Opcode, Reg0, Reg1, MCOperand::createImm(Imm), IDLoc, STI);
 }
 
+void MipsTargetStreamer::emitRRIII(unsigned Opcode, unsigned Reg0,
+                                   unsigned Reg1, int16_t Imm0, int16_t Imm1,
+                                   int16_t Imm2, SMLoc IDLoc,
+                                   const MCSubtargetInfo *STI) {
+  MCInst TmpInst;
+  TmpInst.setOpcode(Opcode);
+  TmpInst.addOperand(MCOperand::createReg(Reg0));
+  TmpInst.addOperand(MCOperand::createReg(Reg1));
+  TmpInst.addOperand(MCOperand::createImm(Imm0));
+  TmpInst.addOperand(MCOperand::createImm(Imm1));
+  TmpInst.addOperand(MCOperand::createImm(Imm2));
+  TmpInst.setLoc(IDLoc);
+  getStreamer().EmitInstruction(TmpInst, *STI);
+}
+
 void MipsTargetStreamer::emitAddu(unsigned DstReg, unsigned SrcReg,
                                   unsigned TrgReg, bool Is64Bit,
                                   const MCSubtargetInfo *STI) {

contrib/llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td

@@ -415,6 +415,13 @@ class BITREV_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<"bitrev", int_mips_bitrev,
 class BPOSGE32_MM_DESC : BPOSGE32_DESC_BASE<"bposge32", brtarget_mm,
                                             NoItinerary>;
 
+let DecoderNamespace = "MicroMipsDSP", Arch = "mmdsp",
+    AdditionalPredicates = [HasDSP, InMicroMips] in {
+    def LWDSP_MM : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel,
+                   LW_FM_MM<0x3f>;
+    def SWDSP_MM : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel,
+                   LW_FM_MM<0x3e>;
+}
 // Instruction defs.
 // microMIPS DSP Rev 1
 def ADDQ_PH_MM : DspMMRel, ADDQ_PH_MM_ENC, ADDQ_PH_DESC;

contrib/llvm/lib/Target/Mips/MipsDSPInstrInfo.td

@@ -1284,6 +1284,12 @@ let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
   def STORE_CCOND_DSP : Store<"store_ccond_dsp", DSPCC>;
 }
 
+let DecoderNamespace = "MipsDSP", Arch = "dsp",
+    AdditionalPredicates = [HasDSP] in {
+  def LWDSP : Load<"lw", DSPROpnd, null_frag, II_LW>, DspMMRel, LW_FM<0x23>;
+  def SWDSP : Store<"sw", DSPROpnd, null_frag, II_SW>, DspMMRel, LW_FM<0x2b>;
+}
+
 // Pseudo CMP and PICK instructions.
 class PseudoCMP<Instruction RealInst> :
   PseudoDSP<(outs DSPCC:$cmp), (ins DSPROpnd:$rs, DSPROpnd:$rt), []>,

contrib/llvm/lib/Target/Mips/MipsFrameLowering.cpp

@@ -107,38 +107,31 @@ bool MipsFrameLowering::hasBP(const MachineFunction &MF) const {
   return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF);
 }
 
+// Estimate the size of the stack, including the incoming arguments. We need to
+// account for register spills, local objects, reserved call frame and incoming
+// arguments. This is required to determine the largest possible positive offset
+// from $sp so that it can be determined if an emergency spill slot for stack
+// addresses is required.
 uint64_t MipsFrameLowering::estimateStackSize(const MachineFunction &MF) const {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
 
-  int64_t Offset = 0;
+  int64_t Size = 0;
 
-  // Iterate over fixed sized objects.
+  // Iterate over fixed sized objects which are incoming arguments.
   for (int I = MFI.getObjectIndexBegin(); I != 0; ++I)
-    Offset = std::max(Offset, -MFI.getObjectOffset(I));
+    if (MFI.getObjectOffset(I) > 0)
+      Size += MFI.getObjectSize(I);
 
   // Conservatively assume all callee-saved registers will be saved.
   for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
-    unsigned Size = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R));
+    unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R));
-    Offset = alignTo(Offset + Size, Size);
+    Size = alignTo(Size + RegSize, RegSize);
   }
 
-  unsigned MaxAlign = MFI.getMaxAlignment();
+  // Get the size of the rest of the frame objects and any possible reserved
-
+  // call frame, accounting for alignment.
-  // Check that MaxAlign is not zero if there is a stack object that is not a
+  return Size + MFI.estimateStackSize(MF);
-  // callee-saved spill.
-  assert(!MFI.getObjectIndexEnd() || MaxAlign);
-
-  // Iterate over other objects.
-  for (unsigned I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I)
-    Offset = alignTo(Offset + MFI.getObjectSize(I), MaxAlign);
-
-  // Call frame.
-  if (MFI.adjustsStack() && hasReservedCallFrame(MF))
-    Offset = alignTo(Offset + MFI.getMaxCallFrameSize(),
-                     std::max(MaxAlign, getStackAlignment()));
-
-  return alignTo(Offset, getStackAlignment());
 }
 
 // Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions

contrib/llvm/lib/Target/Mips/MipsMTInstrFormats.td

@@ -35,6 +35,8 @@ class FIELD5<bits<5> Val> {
 def FIELD5_1_DMT_EMT  : FIELD5<0b00001>;
 def FIELD5_2_DMT_EMT  : FIELD5<0b01111>;
 def FIELD5_1_2_DVPE_EVPE : FIELD5<0b00000>;
+def FIELD5_MFTR : FIELD5<0b01000>;
+def FIELD5_MTTR : FIELD5<0b01100>;
 
 class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
   bits<32> Inst;
@@ -50,6 +52,25 @@ class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
   let Inst{2-0}   = 0b001;
 }
 
+class COP0_MFTTR_MT<FIELD5 Op> : MipsMTInst {
+  bits<32> Inst;
+
+  bits<5> rt;
+  bits<5> rd;
+  bits<1> u;
+  bits<1> h;
+  bits<3> sel;
+  let Inst{31-26} = 0b010000; // COP0
+  let Inst{25-21} = Op.Value; // MFMC0
+  let Inst{20-16} = rt;
+  let Inst{15-11} = rd;
+  let Inst{10-6}  = 0b00000;  // rx - currently unsupported.
+  let Inst{5}     = u;
+  let Inst{4}     = h;
+  let Inst{3}     = 0b0;
+  let Inst{2-0}   = sel;
+}
+
 class SPECIAL3_MT_FORK : MipsMTInst {
   bits<32> Inst;
 

contrib/llvm/lib/Target/Mips/MipsMTInstrInfo.td

@@ -6,6 +6,13 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+//
+// This file describes the MIPS MT ASE as defined by MD00378 1.12.
+//
+// TODO: Add support for the microMIPS encodings for the MT ASE and add the
+//       instruction mappings.
+//
+//===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // MIPS MT Instruction Encodings
@@ -27,6 +34,10 @@ class FORK_ENC : SPECIAL3_MT_FORK;
 
 class YIELD_ENC : SPECIAL3_MT_YIELD;
 
+class MFTR_ENC : COP0_MFTTR_MT<FIELD5_MFTR>;
+
+class MTTR_ENC : COP0_MFTTR_MT<FIELD5_MTTR>;
+
 //===----------------------------------------------------------------------===//
 // MIPS MT Instruction Descriptions
 //===----------------------------------------------------------------------===//
@@ -39,6 +50,22 @@ class MT_1R_DESC_BASE<string instr_asm, InstrItinClass Itin = NoItinerary> {
   InstrItinClass Itinerary = Itin;
 }
 
+class MFTR_DESC {
+  dag OutOperandList = (outs GPR32Opnd:$rd);
+  dag InOperandList = (ins GPR32Opnd:$rt, uimm1:$u, uimm3:$sel, uimm1:$h);
+  string AsmString = "mftr\t$rd, $rt, $u, $sel, $h";
+  list<dag> Pattern = [];
+  InstrItinClass Itinerary = II_MFTR;
+}
+
+class MTTR_DESC {
+  dag OutOperandList = (outs GPR32Opnd:$rd);
+  dag InOperandList = (ins GPR32Opnd:$rt, uimm1:$u, uimm3:$sel, uimm1:$h);
+  string AsmString = "mttr\t$rt, $rd, $u, $sel, $h";
+  list<dag> Pattern = [];
+  InstrItinClass Itinerary = II_MTTR;
+}
+
 class FORK_DESC {
   dag OutOperandList = (outs GPR32Opnd:$rs, GPR32Opnd:$rd);
   dag InOperandList = (ins GPR32Opnd:$rt);
@@ -79,8 +106,73 @@ let hasSideEffects = 1, isNotDuplicable = 1,
   def FORK : FORK_ENC, FORK_DESC, ASE_MT;
 
   def YIELD : YIELD_ENC, YIELD_DESC, ASE_MT;
+
+  def MFTR : MFTR_ENC, MFTR_DESC, ASE_MT;
+
+  def MTTR : MTTR_ENC, MTTR_DESC, ASE_MT;
 }
 
+//===----------------------------------------------------------------------===//
+// MIPS MT Pseudo Instructions - used to support mtfr & mttr aliases.
+//===----------------------------------------------------------------------===//
+def MFTC0 : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins COP0Opnd:$rt,
+                                                        uimm3:$sel),
+                              "mftc0 $rd, $rt, $sel">, ASE_MT;
+
+def MFTGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rt,
+                                                          uimm3:$sel),
+                               "mftgpr $rd, $rt">, ASE_MT;
+
+def MFTLO : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),
+                              "mftlo $rt, $ac">, ASE_MT;
+
+def MFTHI : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),
+                              "mfthi $rt, $ac">, ASE_MT;
+
+def MFTACX : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins ACC64DSPOpnd:$ac),
+                               "mftacx $rt, $ac">, ASE_MT;
+
+def MFTDSP : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins),
+                               "mftdsp $rt">, ASE_MT;
+
+def MFTC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGR32Opnd:$ft),
+                              "mftc1 $rt, $ft">, ASE_MT;
+
+def MFTHC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGR32Opnd:$ft),
+                               "mfthc1 $rt, $ft">, ASE_MT;
+
+def CFTC1 : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins FGRCCOpnd:$ft),
+                              "cftc1 $rt, $ft">, ASE_MT;
+
+
+def MTTC0 : MipsAsmPseudoInst<(outs COP0Opnd:$rd), (ins GPR32Opnd:$rt,
+                                                        uimm3:$sel),
+                              "mttc0 $rt, $rd, $sel">, ASE_MT;
+
+def MTTGPR : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins GPR32Opnd:$rd),
+                               "mttgpr $rd, $rt">, ASE_MT;
+
+def MTTLO : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),
+                              "mttlo $rt, $ac">, ASE_MT;
+
+def MTTHI : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),
+                              "mtthi $rt, $ac">, ASE_MT;
+
+def MTTACX : MipsAsmPseudoInst<(outs ACC64DSPOpnd:$ac), (ins GPR32Opnd:$rt),
+                               "mttacx $rt, $ac">, ASE_MT;
+
+def MTTDSP : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rt),
+                               "mttdsp $rt">, ASE_MT;
+
+def MTTC1 : MipsAsmPseudoInst<(outs FGR32Opnd:$ft), (ins GPR32Opnd:$rt),
+                              "mttc1 $rt, $ft">, ASE_MT;
+
+def MTTHC1 : MipsAsmPseudoInst<(outs FGR32Opnd:$ft), (ins GPR32Opnd:$rt),
+                               "mtthc1 $rt, $ft">, ASE_MT;
+
+def CTTC1 : MipsAsmPseudoInst<(outs FGRCCOpnd:$ft), (ins GPR32Opnd:$rt),
+                              "cttc1 $rt, $ft">, ASE_MT;
+
 //===----------------------------------------------------------------------===//
 // MIPS MT Instruction Definitions
 //===----------------------------------------------------------------------===//
@@ -95,4 +187,22 @@ let AdditionalPredicates = [NotInMicroMips] in {
   def : MipsInstAlias<"evpe", (EVPE ZERO), 1>, ASE_MT;
 
   def : MipsInstAlias<"yield $rs", (YIELD ZERO, GPR32Opnd:$rs), 1>, ASE_MT;
+
+  def : MipsInstAlias<"mftc0 $rd, $rt", (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0),
+                      1>, ASE_MT;
+
+  def : MipsInstAlias<"mftlo $rt", (MFTLO GPR32Opnd:$rt, AC0), 1>, ASE_MT;
+
+  def : MipsInstAlias<"mfthi $rt", (MFTHI GPR32Opnd:$rt, AC0), 1>, ASE_MT;
+
+  def : MipsInstAlias<"mftacx $rt", (MFTACX GPR32Opnd:$rt, AC0), 1>, ASE_MT;
+
+  def : MipsInstAlias<"mttc0 $rd, $rt", (MTTC0 COP0Opnd:$rt, GPR32Opnd:$rd, 0),
+                      1>, ASE_MT;
+
+  def : MipsInstAlias<"mttlo $rt", (MTTLO AC0, GPR32Opnd:$rt), 1>, ASE_MT;
+
+  def : MipsInstAlias<"mtthi $rt", (MTTHI AC0, GPR32Opnd:$rt), 1>, ASE_MT;
+
+  def : MipsInstAlias<"mttacx $rt", (MTTACX AC0, GPR32Opnd:$rt), 1>, ASE_MT;
 }

contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp

@@ -894,10 +894,12 @@ void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF,
   }
 
   // Set scavenging frame index if necessary.
-  uint64_t MaxSPOffset = MF.getInfo<MipsFunctionInfo>()->getIncomingArgSize() +
+  uint64_t MaxSPOffset = estimateStackSize(MF);
-    estimateStackSize(MF);
 
-  if (isInt<16>(MaxSPOffset))
+  // MSA has a minimum offset of 10 bits signed. If there is a variable
+  // sized object on the stack, the estimation cannot account for it.
+  if (isIntN(STI.hasMSA() ? 10 : 16, MaxSPOffset) &&
+      !MF.getFrameInfo().hasVarSizedObjects())
     return;
 
   const TargetRegisterClass &RC =

contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp

@@ -226,6 +226,8 @@ storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
     Opc = Mips::SW;
   else if (Mips::HI64RegClass.hasSubClassEq(RC))
     Opc = Mips::SD;
+  else if (Mips::DSPRRegClass.hasSubClassEq(RC))
+    Opc = Mips::SWDSP;
 
   // Hi, Lo are normally caller save but they are callee save
   // for interrupt handling.
@@ -302,6 +304,8 @@ loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
     Opc = Mips::LW;
   else if (Mips::LO64RegClass.hasSubClassEq(RC))
     Opc = Mips::LD;
+  else if (Mips::DSPRRegClass.hasSubClassEq(RC))
+    Opc = Mips::LWDSP;
 
   assert(Opc && "Register class not handled!");
 

contrib/llvm/lib/Target/Mips/MipsSchedule.td

@@ -226,6 +226,7 @@ def II_MFC1             : InstrItinClass;
 def II_MFHC1            : InstrItinClass;
 def II_MFC2             : InstrItinClass;
 def II_MFHI_MFLO        : InstrItinClass; // mfhi and mflo
+def II_MFTR             : InstrItinClass;
 def II_MOD              : InstrItinClass;
 def II_MODU             : InstrItinClass;
 def II_MOVE             : InstrItinClass;
@@ -255,6 +256,7 @@ def II_MTC1             : InstrItinClass;
 def II_MTHC1            : InstrItinClass;
 def II_MTC2             : InstrItinClass;
 def II_MTHI_MTLO        : InstrItinClass; // mthi and mtlo
+def II_MTTR             : InstrItinClass;
 def II_MUL              : InstrItinClass;
 def II_MUH              : InstrItinClass;
 def II_MUHU             : InstrItinClass;
@@ -664,12 +666,14 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
   InstrItinData<II_MFHC0           , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_MFC1            , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_MFC2            , [InstrStage<2,  [ALU]>]>,
+  InstrItinData<II_MFTR            , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_MTC0            , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_MTHC0           , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_MTC1            , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_MTC2            , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_MFHC1           , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_MTHC1           , [InstrStage<2,  [ALU]>]>,
+  InstrItinData<II_MTTR            , [InstrStage<2,  [ALU]>]>,
   InstrItinData<II_CACHE           , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_PREF            , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_CACHEE          , [InstrStage<1,  [ALU]>]>,

contrib/llvm/lib/Target/Mips/MipsScheduleGeneric.td

@@ -268,9 +268,11 @@ def : ItinRW<[GenericWriteLoad], [II_LWLE, II_LWRE]>;
 // MIPS MT instructions
 // ====================
 
-def : ItinRW<[GenericWriteMove], [II_DMT, II_DVPE, II_EMT, II_EVPE]>;
+def : ItinRW<[GenericWriteMove], [II_DMT, II_DVPE, II_EMT, II_EVPE, II_MFTR,
+                                  II_MTTR]>;
 
 def : ItinRW<[GenericReadWriteCOP0Long], [II_YIELD]>;
+
 def : ItinRW<[GenericWriteCOP0Short], [II_FORK]>;
 
 // MIPS32R6 and MIPS16e

contrib/llvm/lib/Target/Mips/MipsTargetStreamer.h

@@ -119,6 +119,9 @@ class MipsTargetStreamer : public MCTargetStreamer {
                SMLoc IDLoc, const MCSubtargetInfo *STI);
   void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
                SMLoc IDLoc, const MCSubtargetInfo *STI);
+  void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
+                 int16_t Imm1, int16_t Imm2, SMLoc IDLoc,
+                 const MCSubtargetInfo *STI);
   void emitAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, bool Is64Bit,
                 const MCSubtargetInfo *STI);
   void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,

contrib/llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -7026,6 +7026,18 @@ X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
     return DAG.getTargetConstant(1, dl, VT);
 
   if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
+    if (VT == MVT::v64i1 && !Subtarget.is64Bit()) {
+      // Split the pieces.
+      SDValue Lower =
+          DAG.getBuildVector(MVT::v32i1, dl, Op.getNode()->ops().slice(0, 32));
+      SDValue Upper =
+          DAG.getBuildVector(MVT::v32i1, dl, Op.getNode()->ops().slice(32, 32));
+      // We have to manually lower both halves so getNode doesn't try to
+      // reassemble the build_vector.
+      Lower = LowerBUILD_VECTORvXi1(Lower, DAG);
+      Upper = LowerBUILD_VECTORvXi1(Upper, DAG);
+      return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lower, Upper);
+    }
     SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
     if (Imm.getValueSizeInBits() == VT.getSizeInBits())
       return DAG.getBitcast(VT, Imm);
@@ -34733,6 +34745,11 @@ static SDValue combineVectorSizedSetCCEquality(SDNode *SetCC, SelectionDAG &DAG,
   if (!OpVT.isScalarInteger() || OpSize < 128 || isNullConstant(Y))
     return SDValue();
 
+  // Bail out if we know that this is not really just an oversized integer.
+  if (peekThroughBitcasts(X).getValueType() == MVT::f128 ||
+      peekThroughBitcasts(Y).getValueType() == MVT::f128)
+    return SDValue();
+
   // TODO: Use PXOR + PTEST for SSE4.1 or later?
   // TODO: Add support for AVX-512.
   EVT VT = SetCC->getValueType(0);

contrib/llvm/tools/clang/include/clang/Basic/Attr.td

@@ -2459,9 +2459,9 @@ def DLLImport : InheritableAttr, TargetSpecificAttr<TargetWindows> {
   let Documentation = [DLLImportDocs];
 }
 
-def SelectAny : InheritableAttr, TargetSpecificAttr<TargetWindows> {
+def SelectAny : InheritableAttr {
   let Spellings = [Declspec<"selectany">, GCC<"selectany">];
-  let Documentation = [Undocumented];
+  let Documentation = [SelectAnyDocs];
 }
 
 def Thread : Attr {

contrib/llvm/tools/clang/include/clang/Basic/AttrDocs.td

@@ -3106,3 +3106,18 @@ This attribute can be added to an Objective-C ``@interface`` declaration to
 ensure that this class cannot be subclassed.
   }];
 }
+
+
+def SelectAnyDocs : Documentation {
+  let Category = DocCatType;
+  let Content = [{
+This attribute appertains to a global symbol, causing it to have a weak
+definition (
+`linkonce <https://llvm.org/docs/LangRef.html#linkage-types>`_
+), allowing the linker to select any definition.
+
+For more information see
+`gcc documentation <https://gcc.gnu.org/onlinedocs/gcc-7.2.0/gcc/Microsoft-Windows-Variable-Attributes.html>`_
+or `msvc documentation <https://docs.microsoft.com/pl-pl/cpp/cpp/selectany>`_.
+}];
+}

contrib/llvm/tools/clang/include/clang/Basic/BuiltinsX86.def

@@ -976,7 +976,6 @@ TARGET_BUILTIN(__builtin_ia32_pmuludq512, "V8LLiV16iV16i", "", "avx512f")
 TARGET_BUILTIN(__builtin_ia32_ptestmd512, "UsV16iV16iUs", "", "avx512f")
 TARGET_BUILTIN(__builtin_ia32_ptestmq512, "UcV8LLiV8LLiUc", "", "avx512f")
 TARGET_BUILTIN(__builtin_ia32_pbroadcastd512_gpr_mask, "V16iiV16iUs", "", "avx512f")
-TARGET_BUILTIN(__builtin_ia32_pbroadcastq512_mem_mask, "V8LLiLLiV8LLiUc", "", "avx512f")
 TARGET_BUILTIN(__builtin_ia32_loaddqusi512_mask, "V16iiC*V16iUs", "", "avx512f")
 TARGET_BUILTIN(__builtin_ia32_loaddqudi512_mask, "V8LLiLLiC*V8LLiUc", "", "avx512f")
 TARGET_BUILTIN(__builtin_ia32_loadups512_mask, "V16ffC*V16fUs", "", "avx512f")

contrib/llvm/tools/clang/include/clang/Basic/DiagnosticSemaKinds.td

@@ -8830,7 +8830,7 @@ def err_omp_firstprivate_distribute_in_teams_reduction : Error<
 def err_omp_depend_clause_thread_simd : Error<
   "'depend' clauses cannot be mixed with '%0' clause">;
 def err_omp_depend_sink_expected_loop_iteration : Error<
-  "expected %0 loop iteration variable">;
+  "expected%select{| %1}0 loop iteration variable">;
 def err_omp_depend_sink_unexpected_expr : Error<
   "unexpected expression: number of expressions is larger than the number of associated loops">;
 def err_omp_depend_sink_expected_plus_minus : Error<

contrib/llvm/tools/clang/lib/AST/ExprConstant.cpp

@@ -537,7 +537,7 @@ namespace {
   /// rules.  For example, the RHS of (0 && foo()) is not evaluated.  We can
   /// evaluate the expression regardless of what the RHS is, but C only allows
   /// certain things in certain situations.
-  struct LLVM_ALIGNAS(/*alignof(uint64_t)*/ 8) EvalInfo {
+  struct EvalInfo {
     ASTContext &Ctx;
 
     /// EvalStatus - Contains information about the evaluation.
@@ -977,24 +977,22 @@ namespace {
   /// RAII object used to optionally suppress diagnostics and side-effects from
   /// a speculative evaluation.
   class SpeculativeEvaluationRAII {
-    /// Pair of EvalInfo, and a bit that stores whether or not we were
+    EvalInfo *Info = nullptr;
-    /// speculatively evaluating when we created this RAII.
+    Expr::EvalStatus OldStatus;
-    llvm::PointerIntPair<EvalInfo *, 1, bool> InfoAndOldSpecEval;
+    bool OldIsSpeculativelyEvaluating;
-    Expr::EvalStatus Old;
 
     void moveFromAndCancel(SpeculativeEvaluationRAII &&Other) {
-      InfoAndOldSpecEval = Other.InfoAndOldSpecEval;
+      Info = Other.Info;
-      Old = Other.Old;
+      OldStatus = Other.OldStatus;
-      Other.InfoAndOldSpecEval.setPointer(nullptr);
+      Other.Info = nullptr;
     }
 
     void maybeRestoreState() {
-      EvalInfo *Info = InfoAndOldSpecEval.getPointer();
       if (!Info)
         return;
 
-      Info->EvalStatus = Old;
+      Info->EvalStatus = OldStatus;
-      Info->IsSpeculativelyEvaluating = InfoAndOldSpecEval.getInt();
+      Info->IsSpeculativelyEvaluating = OldIsSpeculativelyEvaluating;
     }
 
   public:
@@ -1002,8 +1000,8 @@ namespace {
 
     SpeculativeEvaluationRAII(
         EvalInfo &Info, SmallVectorImpl<PartialDiagnosticAt> *NewDiag = nullptr)
-        : InfoAndOldSpecEval(&Info, Info.IsSpeculativelyEvaluating),
+        : Info(&Info), OldStatus(Info.EvalStatus),
-          Old(Info.EvalStatus) {
+          OldIsSpeculativelyEvaluating(Info.IsSpeculativelyEvaluating) {
       Info.EvalStatus.Diag = NewDiag;
       Info.IsSpeculativelyEvaluating = true;
     }

contrib/llvm/tools/clang/lib/Basic/Targets.cpp

@@ -2169,7 +2169,7 @@ class AMDGPUTargetInfo final : public TargetInfo {
 public:
   AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts)
     : TargetInfo(Triple) ,
-      GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600),
+      GPU(isAMDGCN(Triple) ? GK_GFX6 : parseR600Name(Opts.CPU)),
       hasFP64(false),
       hasFMAF(false),
       hasLDEXPF(false),
@@ -2179,6 +2179,12 @@ class AMDGPUTargetInfo final : public TargetInfo {
       hasFMAF = true;
       hasLDEXPF = true;
     }
+    if (getTriple().getArch() == llvm::Triple::r600) {
+      if (GPU == GK_EVERGREEN_DOUBLE_OPS || GPU == GK_CAYMAN) {
+        hasFMAF = true;
+      }
+    }
+
     auto IsGenericZero = isGenericZero(Triple);
     resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ?
                     (IsGenericZero ? DataLayoutStringSIGenericIsZero :
@@ -9350,8 +9356,7 @@ class AVRTargetInfo : public TargetInfo {
     WIntType = SignedInt;
     Char32Type = UnsignedLong;
     SigAtomicType = SignedChar;
-    resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64"
+    resetDataLayout("e-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8");
-		    "-f32:32:32-f64:64:64-n8");
   }
 
   void getTargetDefines(const LangOptions &Opts,

contrib/llvm/tools/clang/lib/Basic/Version.cpp

@@ -36,7 +36,7 @@ std::string getClangRepositoryPath() {
 
   // If the SVN_REPOSITORY is empty, try to use the SVN keyword. This helps us
   // pick up a tag in an SVN export, for example.
-  StringRef SVNRepository("$URL: https://llvm.org/svn/llvm-project/cfe/tags/RELEASE_500/final/lib/Basic/Version.cpp $");
+  StringRef SVNRepository("$URL: https://llvm.org/svn/llvm-project/cfe/branches/release_50/lib/Basic/Version.cpp $");
   if (URL.empty()) {
     URL = SVNRepository.slice(SVNRepository.find(':'),
                               SVNRepository.find("/lib/Basic"));

contrib/llvm/tools/clang/lib/CodeGen/CGExpr.cpp

@@ -3309,12 +3309,7 @@ static Address emitOMPArraySectionBase(CodeGenFunction &CGF, const Expr *Base,
 
 LValue CodeGenFunction::EmitOMPArraySectionExpr(const OMPArraySectionExpr *E,
                                                 bool IsLowerBound) {
-  QualType BaseTy;
+  QualType BaseTy = OMPArraySectionExpr::getBaseOriginalType(E->getBase());
-  if (auto *ASE =
-          dyn_cast<OMPArraySectionExpr>(E->getBase()->IgnoreParenImpCasts()))
-    BaseTy = OMPArraySectionExpr::getBaseOriginalType(ASE);
-  else
-    BaseTy = E->getBase()->getType();
   QualType ResultExprTy;
   if (auto *AT = getContext().getAsArrayType(BaseTy))
     ResultExprTy = AT->getElementType();
@@ -3619,8 +3614,9 @@ LValue CodeGenFunction::EmitLValueForField(LValue base,
     getFieldAlignmentSource(BaseInfo.getAlignmentSource());
   LValueBaseInfo FieldBaseInfo(fieldAlignSource, BaseInfo.getMayAlias());
 
+  QualType type = field->getType();
   const RecordDecl *rec = field->getParent();
-  if (rec->isUnion() || rec->hasAttr<MayAliasAttr>())
+  if (rec->isUnion() || rec->hasAttr<MayAliasAttr>() || type->isVectorType())
     FieldBaseInfo.setMayAlias(true);
   bool mayAlias = FieldBaseInfo.getMayAlias();
 
@@ -3645,7 +3641,6 @@ LValue CodeGenFunction::EmitLValueForField(LValue base,
     return LValue::MakeBitfield(Addr, Info, fieldType, FieldBaseInfo);
   }
 
-  QualType type = field->getType();
   Address addr = base.getAddress();
   unsigned cvr = base.getVRQualifiers();
   bool TBAAPath = CGM.getCodeGenOpts().StructPathTBAA;

contrib/llvm/tools/clang/lib/CodeGen/CGOpenMPRuntime.cpp

@@ -264,6 +264,13 @@ class CGOpenMPInlinedRegionInfo : public CGOpenMPRegionInfo {
     return nullptr;
   }
 
+  /// \brief Get an LValue for the current ThreadID variable.
+  LValue getThreadIDVariableLValue(CodeGenFunction &CGF) override {
+    if (OuterRegionInfo)
+      return OuterRegionInfo->getThreadIDVariableLValue(CGF);
+    llvm_unreachable("No LValue for inlined OpenMP construct");
+  }
+
   /// \brief Get the name of the capture helper.
   StringRef getHelperName() const override {
     if (auto *OuterRegionInfo = getOldCSI())
@@ -771,7 +778,8 @@ static void emitInitWithReductionInitializer(CodeGenFunction &CGF,
 /// \param Init Initial expression of array.
 /// \param SrcAddr Address of the original array.
 static void EmitOMPAggregateInit(CodeGenFunction &CGF, Address DestAddr,
-                                 QualType Type, const Expr *Init,
+                                 QualType Type, bool EmitDeclareReductionInit,
+                                 const Expr *Init,
                                  const OMPDeclareReductionDecl *DRD,
                                  Address SrcAddr = Address::invalid()) {
   // Perform element-by-element initialization.
@@ -825,7 +833,7 @@ static void EmitOMPAggregateInit(CodeGenFunction &CGF, Address DestAddr,
   // Emit copy.
   {
     CodeGenFunction::RunCleanupsScope InitScope(CGF);
-    if (DRD && (DRD->getInitializer() || !Init)) {
+    if (EmitDeclareReductionInit) {
       emitInitWithReductionInitializer(CGF, DRD, Init, DestElementCurrent,
                                        SrcElementCurrent, ElementTy);
     } else
@@ -883,8 +891,12 @@ void ReductionCodeGen::emitAggregateInitialization(
   // captured region.
   auto *PrivateVD =
       cast<VarDecl>(cast<DeclRefExpr>(ClausesData[N].Private)->getDecl());
+  bool EmitDeclareReductionInit =
+      DRD && (DRD->getInitializer() || !PrivateVD->hasInit());
   EmitOMPAggregateInit(CGF, PrivateAddr, PrivateVD->getType(),
-                       DRD ? ClausesData[N].ReductionOp : PrivateVD->getInit(),
+                       EmitDeclareReductionInit,
+                       EmitDeclareReductionInit ? ClausesData[N].ReductionOp
+                                                : PrivateVD->getInit(),
                        DRD, SharedLVal.getAddress());
 }
 
@@ -4244,9 +4256,20 @@ CGOpenMPRuntime::emitTaskInit(CodeGenFunction &CGF, SourceLocation Loc,
   // Build type kmp_routine_entry_t (if not built yet).
   emitKmpRoutineEntryT(KmpInt32Ty);
   // Build type kmp_task_t (if not built yet).
-  if (KmpTaskTQTy.isNull()) {
+  if (isOpenMPTaskLoopDirective(D.getDirectiveKind())) {
-    KmpTaskTQTy = C.getRecordType(createKmpTaskTRecordDecl(
+    if (SavedKmpTaskloopTQTy.isNull()) {
-        CGM, D.getDirectiveKind(), KmpInt32Ty, KmpRoutineEntryPtrQTy));
+      SavedKmpTaskloopTQTy = C.getRecordType(createKmpTaskTRecordDecl(
+          CGM, D.getDirectiveKind(), KmpInt32Ty, KmpRoutineEntryPtrQTy));
+    }
+    KmpTaskTQTy = SavedKmpTaskloopTQTy;
+  } else if (D.getDirectiveKind() == OMPD_task) {
+    assert(D.getDirectiveKind() == OMPD_task &&
+           "Expected taskloop or task directive");
+    if (SavedKmpTaskTQTy.isNull()) {
+      SavedKmpTaskTQTy = C.getRecordType(createKmpTaskTRecordDecl(
+          CGM, D.getDirectiveKind(), KmpInt32Ty, KmpRoutineEntryPtrQTy));
+    }
+    KmpTaskTQTy = SavedKmpTaskTQTy;
   }
   auto *KmpTaskTQTyRD = cast<RecordDecl>(KmpTaskTQTy->getAsTagDecl());
   // Build particular struct kmp_task_t for the given task.

contrib/llvm/tools/clang/lib/CodeGen/CGOpenMPRuntime.h

@@ -313,6 +313,10 @@ class CGOpenMPRuntime {
   ///    deconstructors of firstprivate C++ objects */
   /// } kmp_task_t;
   QualType KmpTaskTQTy;
+  /// Saved kmp_task_t for task directive.
+  QualType SavedKmpTaskTQTy;
+  /// Saved kmp_task_t for taskloop-based directive.
+  QualType SavedKmpTaskloopTQTy;
   /// \brief Type typedef struct kmp_depend_info {
   ///    kmp_intptr_t               base_addr;
   ///    size_t                     len;

contrib/llvm/tools/clang/lib/CodeGen/CGStmtOpenMP.cpp

@@ -1210,12 +1210,14 @@ void CodeGenFunction::EmitOMPInnerLoop(
   EmitBlock(LoopExit.getBlock());
 }
 
-void CodeGenFunction::EmitOMPLinearClauseInit(const OMPLoopDirective &D) {
+bool CodeGenFunction::EmitOMPLinearClauseInit(const OMPLoopDirective &D) {
   if (!HaveInsertPoint())
-    return;
+    return false;
   // Emit inits for the linear variables.
+  bool HasLinears = false;
   for (const auto *C : D.getClausesOfKind<OMPLinearClause>()) {
     for (auto *Init : C->inits()) {
+      HasLinears = true;
       auto *VD = cast<VarDecl>(cast<DeclRefExpr>(Init)->getDecl());
       if (auto *Ref = dyn_cast<DeclRefExpr>(VD->getInit()->IgnoreImpCasts())) {
         AutoVarEmission Emission = EmitAutoVarAlloca(*VD);
@@ -1240,6 +1242,7 @@ void CodeGenFunction::EmitOMPLinearClauseInit(const OMPLoopDirective &D) {
         EmitIgnoredExpr(CS);
       }
   }
+  return HasLinears;
 }
 
 void CodeGenFunction::EmitOMPLinearClauseFinal(
@@ -1529,7 +1532,7 @@ void CodeGenFunction::EmitOMPSimdDirective(const OMPSimdDirective &S) {
     CGF.EmitOMPSimdInit(S);
 
     emitAlignedClause(CGF, S);
-    CGF.EmitOMPLinearClauseInit(S);
+    (void)CGF.EmitOMPLinearClauseInit(S);
     {
       OMPPrivateScope LoopScope(CGF);
       CGF.EmitOMPPrivateLoopCounters(S, LoopScope);
@@ -2147,7 +2150,7 @@ bool CodeGenFunction::EmitOMPWorksharingLoop(
 
     llvm::DenseSet<const Expr *> EmittedFinals;
     emitAlignedClause(*this, S);
-    EmitOMPLinearClauseInit(S);
+    bool HasLinears = EmitOMPLinearClauseInit(S);
     // Emit helper vars inits.
 
     std::pair<LValue, LValue> Bounds = CodeGenLoopBounds(*this, S);
@@ -2161,7 +2164,7 @@ bool CodeGenFunction::EmitOMPWorksharingLoop(
     // Emit 'then' code.
     {
       OMPPrivateScope LoopScope(*this);
-      if (EmitOMPFirstprivateClause(S, LoopScope)) {
+      if (EmitOMPFirstprivateClause(S, LoopScope) || HasLinears) {
         // Emit implicit barrier to synchronize threads and avoid data races on
         // initialization of firstprivate variables and post-update of
         // lastprivate variables.

contrib/llvm/tools/clang/lib/CodeGen/CodeGenFunction.h

@@ -1116,7 +1116,7 @@ class CodeGenFunction : public CodeGenTypeCache {
         auto IP = CGF.Builder.saveAndClearIP();
         CGF.EmitBlock(Stack.back().ExitBlock.getBlock());
         CodeGen(CGF);
-        CGF.EmitBranchThroughCleanup(Stack.back().ContBlock);
+        CGF.EmitBranch(Stack.back().ContBlock.getBlock());
         CGF.Builder.restoreIP(IP);
         Stack.back().HasBeenEmitted = true;
       }
@@ -2761,7 +2761,9 @@ class CodeGenFunction : public CodeGenTypeCache {
   /// and initializes them with the values according to OpenMP standard.
   ///
   /// \param D Directive (possibly) with the 'linear' clause.
-  void EmitOMPLinearClauseInit(const OMPLoopDirective &D);
+  /// \return true if at least one linear variable is found that should be
+  /// initialized with the value of the original variable, false otherwise.
+  bool EmitOMPLinearClauseInit(const OMPLoopDirective &D);
 
   typedef const llvm::function_ref<void(CodeGenFunction & /*CGF*/,
                                         llvm::Value * /*OutlinedFn*/,

contrib/llvm/tools/clang/lib/Driver/ToolChain.cpp

@@ -74,11 +74,6 @@ ToolChain::ToolChain(const Driver &D, const llvm::Triple &T,
     : D(D), Triple(T), Args(Args), CachedRTTIArg(GetRTTIArgument(Args)),
       CachedRTTIMode(CalculateRTTIMode(Args, Triple, CachedRTTIArg)),
       EffectiveTriple() {
-  if (Arg *A = Args.getLastArg(options::OPT_mthread_model))
-    if (!isThreadModelSupported(A->getValue()))
-      D.Diag(diag::err_drv_invalid_thread_model_for_target)
-          << A->getValue() << A->getAsString(Args);
-
   std::string CandidateLibPath = getArchSpecificLibPath();
   if (getVFS().exists(CandidateLibPath))
     getFilePaths().push_back(CandidateLibPath);

contrib/llvm/tools/clang/lib/Driver/ToolChains/BareMetal.cpp

@@ -65,14 +65,6 @@ Tool *BareMetal::buildLinker() const {
   return new tools::baremetal::Linker(*this);
 }
 
-std::string BareMetal::getThreadModel() const {
-  return "single";
-}
-
-bool BareMetal::isThreadModelSupported(const StringRef Model) const {
-  return Model == "single";
-}
-
 std::string BareMetal::getRuntimesDir() const {
   SmallString<128> Dir(getDriver().ResourceDir);
   llvm::sys::path::append(Dir, "lib", "baremetal");

contrib/llvm/tools/clang/lib/Driver/ToolChains/BareMetal.h

@@ -38,8 +38,6 @@ class LLVM_LIBRARY_VISIBILITY BareMetal : public ToolChain {
   bool isPICDefaultForced() const override { return false; }
   bool SupportsProfiling() const override { return false; }
   bool SupportsObjCGC() const override { return false; }
-  std::string getThreadModel() const override;
-  bool isThreadModelSupported(const StringRef Model) const override;
 
   RuntimeLibType GetDefaultRuntimeLibType() const override {
     return ToolChain::RLT_CompilerRT;

contrib/llvm/tools/clang/lib/Driver/ToolChains/Clang.cpp

@@ -2227,8 +2227,12 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA,
   }
 
   CmdArgs.push_back("-mthread-model");
-  if (Arg *A = Args.getLastArg(options::OPT_mthread_model))
+  if (Arg *A = Args.getLastArg(options::OPT_mthread_model)) {
+    if (!getToolChain().isThreadModelSupported(A->getValue()))
+      D.Diag(diag::err_drv_invalid_thread_model_for_target)
+          << A->getValue() << A->getAsString(Args);
     CmdArgs.push_back(A->getValue());
+  }
   else
     CmdArgs.push_back(Args.MakeArgString(getToolChain().getThreadModel()));
 

contrib/llvm/tools/clang/lib/Format/Format.cpp

@@ -506,7 +506,7 @@ static FormatStyle expandPresets(const FormatStyle &Style) {
     Expanded.BraceWrapping.AfterFunction = true;
     Expanded.BraceWrapping.AfterStruct = true;
     Expanded.BraceWrapping.AfterUnion = true;
-    Expanded.BraceWrapping.SplitEmptyFunction = false;
+    Expanded.BraceWrapping.SplitEmptyFunction = true;
     Expanded.BraceWrapping.SplitEmptyRecord = false;
     break;
   case FormatStyle::BS_Stroustrup:

contrib/llvm/tools/clang/lib/Headers/avx512fintrin.h

@@ -267,21 +267,16 @@ _mm512_maskz_set1_epi32(__mmask16 __M, int __A)
                  __M);
 }
 
+#ifdef __x86_64__
 static __inline __m512i __DEFAULT_FN_ATTRS
 _mm512_maskz_set1_epi64(__mmask8 __M, long long __A)
 {
-#ifdef __x86_64__
   return (__m512i) __builtin_ia32_pbroadcastq512_gpr_mask (__A,
                  (__v8di)
                  _mm512_setzero_si512 (),
                  __M);
-#else
-  return (__m512i) __builtin_ia32_pbroadcastq512_mem_mask (__A,
-                 (__v8di)
-                 _mm512_setzero_si512 (),
-                 __M);
-#endif
 }
+#endif
 
 static __inline __m512 __DEFAULT_FN_ATTRS
 _mm512_setzero_ps(void)

contrib/llvm/tools/clang/lib/Sema/SemaOpenMP.cpp

@@ -3111,8 +3111,8 @@ bool OpenMPIterationSpaceChecker::SetStep(Expr *NewStep, bool Subtract) {
   if (!NewStep->isValueDependent()) {
     // Check that the step is integer expression.
     SourceLocation StepLoc = NewStep->getLocStart();
-    ExprResult Val =
+    ExprResult Val = SemaRef.PerformOpenMPImplicitIntegerConversion(
-        SemaRef.PerformOpenMPImplicitIntegerConversion(StepLoc, NewStep);
+        StepLoc, getExprAsWritten(NewStep));
     if (Val.isInvalid())
       return true;
     NewStep = Val.get();
@@ -8858,7 +8858,8 @@ buildDeclareReductionRef(Sema &SemaRef, SourceLocation Loc, SourceRange Range,
       PrevD = D;
     }
   }
-  if (Ty->isDependentType() || Ty->isInstantiationDependentType() ||
+  if (SemaRef.CurContext->isDependentContext() || Ty->isDependentType() ||
+      Ty->isInstantiationDependentType() ||
       Ty->containsUnexpandedParameterPack() ||
       filterLookupForUDR<bool>(Lookups, [](ValueDecl *D) -> bool {
         return !D->isInvalidDecl() &&
@@ -10226,9 +10227,14 @@ Sema::ActOnOpenMPDependClause(OpenMPDependClauseKind DepKind,
         if (!CurContext->isDependentContext() &&
             DSAStack->getParentOrderedRegionParam() &&
             DepCounter != DSAStack->isParentLoopControlVariable(D).first) {
-          Diag(ELoc, diag::err_omp_depend_sink_expected_loop_iteration)
+          ValueDecl* VD = DSAStack->getParentLoopControlVariable(
-              << DSAStack->getParentLoopControlVariable(
+              DepCounter.getZExtValue());
-                     DepCounter.getZExtValue());
+          if (VD) {
+            Diag(ELoc, diag::err_omp_depend_sink_expected_loop_iteration)
+                << 1 << VD;
+          } else {
+             Diag(ELoc, diag::err_omp_depend_sink_expected_loop_iteration) << 0;
+          }
           continue;
         }
         OpsOffs.push_back({RHS, OOK});
@@ -10258,8 +10264,9 @@ Sema::ActOnOpenMPDependClause(OpenMPDependClauseKind DepKind,
 
     if (!CurContext->isDependentContext() && DepKind == OMPC_DEPEND_sink &&
         TotalDepCount > VarList.size() &&
-        DSAStack->getParentOrderedRegionParam()) {
+        DSAStack->getParentOrderedRegionParam() &&
-      Diag(EndLoc, diag::err_omp_depend_sink_expected_loop_iteration)
+        DSAStack->getParentLoopControlVariable(VarList.size() + 1)) {
+      Diag(EndLoc, diag::err_omp_depend_sink_expected_loop_iteration) << 1
           << DSAStack->getParentLoopControlVariable(VarList.size() + 1);
     }
     if (DepKind != OMPC_DEPEND_source && DepKind != OMPC_DEPEND_sink &&

contrib/llvm/tools/lld/ELF/SyntheticSections.cpp

@@ -427,10 +427,11 @@ CieRecord *EhFrameSection<ELFT>::addCie(EhSectionPiece &Piece,
         &Sec->template getFile<ELFT>()->getRelocTargetSym(Rels[FirstRelI]);
 
   // Search for an existing CIE by CIE contents/relocation target pair.
-  CieRecord *Cie = &CieMap[{Piece.data(), Personality}];
+  CieRecord *&Cie = CieMap[{Piece.data(), Personality}];
 
   // If not found, create a new one.
-  if (Cie->Piece == nullptr) {
+  if (!Cie) {
+    Cie = make<CieRecord>();
     Cie->Piece = &Piece;
     Cies.push_back(Cie);
   }
@@ -522,9 +523,14 @@ template <class ELFT>
 static void writeCieFde(uint8_t *Buf, ArrayRef<uint8_t> D) {
   memcpy(Buf, D.data(), D.size());
 
+  size_t Aligned = alignTo(D.size(), sizeof(typename ELFT::uint));
+
+  // Zero-clear trailing padding if it exists.
+  memset(Buf + D.size(), 0, Aligned - D.size());
+
   // Fix the size field. -4 since size does not include the size field itself.
   const endianness E = ELFT::TargetEndianness;
-  write32<E>(Buf, alignTo(D.size(), sizeof(typename ELFT::uint)) - 4);
+  write32<E>(Buf, Aligned - 4);
 }
 
 template <class ELFT> void EhFrameSection<ELFT>::finalizeContents() {

contrib/llvm/tools/lld/ELF/SyntheticSections.h

@@ -103,7 +103,8 @@ template <class ELFT> class EhFrameSection final : public SyntheticSection {
   std::vector<CieRecord *> Cies;
 
   // CIE records are uniquified by their contents and personality functions.
-  llvm::DenseMap<std::pair<ArrayRef<uint8_t>, SymbolBody *>, CieRecord> CieMap;
+  llvm::DenseMap<std::pair<ArrayRef<uint8_t>, SymbolBody *>, CieRecord *>
+      CieMap;
 };
 
 class GotSection : public SyntheticSection {

contrib/llvm/tools/lldb/source/Expression/IRExecutionUnit.cpp

@@ -282,8 +282,7 @@ void IRExecutionUnit::GetRunnableInfo(Status &error, lldb::addr_t &func_addr,
       .setMCJITMemoryManager(
           std::unique_ptr<MemoryManager>(new MemoryManager(*this)))
       .setCodeModel(codeModel)
-      .setOptLevel(llvm::CodeGenOpt::Less)
+      .setOptLevel(llvm::CodeGenOpt::Less);
-      .setUseOrcMCJITReplacement(true);
 
   llvm::StringRef mArch;
   llvm::StringRef mCPU;

etc/mtree/BSD.debug.dist

@@ -29,7 +29,7 @@
             ..
             lib
                 clang
-                    5.0.0
+                    5.0.1
                         lib
                             freebsd
                             ..

etc/mtree/BSD.usr.dist

@@ -25,7 +25,7 @@
         aout
         ..
         clang
-            5.0.0
+            5.0.1
                 include
                     sanitizer
                     ..

lib/clang/headers/Makefile

@@ -4,7 +4,7 @@
 
 .PATH:		${CLANG_SRCS}/lib/Headers
 
-INCSDIR=	${LIBDIR}/clang/5.0.0/include
+INCSDIR=	${LIBDIR}/clang/5.0.1/include
 
 GENINCS+=	arm_neon.h
 

lib/clang/include/clang/Basic/Version.inc

@@ -1,11 +1,11 @@
 /* $FreeBSD$ */
 
-#define	CLANG_VERSION			5.0.0
+#define	CLANG_VERSION			5.0.1
-#define	CLANG_VERSION_STRING		"5.0.0"
+#define	CLANG_VERSION_STRING		"5.0.1"
 #define	CLANG_VERSION_MAJOR		5
 #define	CLANG_VERSION_MINOR		0
-#define	CLANG_VERSION_PATCHLEVEL	0
+#define	CLANG_VERSION_PATCHLEVEL	1
 
 #define	CLANG_VENDOR			"FreeBSD "
 
-#define	SVN_REVISION			"312559"
+#define	SVN_REVISION			"319231"

lib/clang/include/clang/Config/config.h

@@ -46,7 +46,7 @@
 #define CLANG_HAVE_RLIMITS 1
 
 /* The LLVM product name and version */
-#define BACKEND_PACKAGE_STRING "LLVM 5.0.0svn"
+#define BACKEND_PACKAGE_STRING "LLVM 5.0.1"
 
 /* Linker version detected at compile time. */
 /* #undef HOST_LINK_VERSION */

lib/clang/include/lld/Config/Version.inc

@@ -1,8 +1,8 @@
 // $FreeBSD$
 
-#define LLD_VERSION 5.0.0
+#define LLD_VERSION 5.0.1
-#define LLD_VERSION_STRING "5.0.0"
+#define LLD_VERSION_STRING "5.0.1"
 #define LLD_VERSION_MAJOR 5
 #define LLD_VERSION_MINOR 0
-#define LLD_REVISION_STRING "312559"
+#define LLD_REVISION_STRING "319231"
 #define LLD_REPOSITORY_STRING "FreeBSD"

lib/clang/include/llvm/Config/config.h

@@ -386,10 +386,10 @@
 #define LLVM_VERSION_MINOR 0
 
 /* Patch version of the LLVM API */
-#define LLVM_VERSION_PATCH 0
+#define LLVM_VERSION_PATCH 1
 
 /* LLVM version string */
-#define LLVM_VERSION_STRING "5.0.0svn"
+#define LLVM_VERSION_STRING "5.0.1"
 
 /* Define to the extension used for shared libraries, say, ".so". */
 #define LTDL_SHLIB_EXT ".so"
@@ -401,13 +401,13 @@
 #define PACKAGE_NAME "LLVM"
 
 /* Define to the full name and version of this package. */
-#define PACKAGE_STRING "LLVM 5.0.0svn"
+#define PACKAGE_STRING "LLVM 5.0.1"
 
 /* Define to the one symbol short name of this package. */
 #undef PACKAGE_TARNAME
 
 /* Define to the version of this package. */
-#define PACKAGE_VERSION "5.0.0svn"
+#define PACKAGE_VERSION "5.0.1"
 
 /* Define to the vendor of this package. */
 /* #undef PACKAGE_VENDOR */

lib/clang/include/llvm/Config/llvm-config.h

@@ -70,9 +70,9 @@
 #define LLVM_VERSION_MINOR 0
 
 /* Patch version of the LLVM API */
-#define LLVM_VERSION_PATCH 0
+#define LLVM_VERSION_PATCH 1
 
 /* LLVM version string */
-#define LLVM_VERSION_STRING "5.0.0svn"
+#define LLVM_VERSION_STRING "5.0.1"
 
 #endif

lib/clang/include/llvm/Support/VCSRevision.h

@@ -1,2 +1,2 @@
 /* $FreeBSD$ */
-#define LLVM_REVISION "svn-r312559"
+#define LLVM_REVISION "svn-r319231"

lib/libclang_rt/Makefile.inc

@@ -14,7 +14,7 @@ CRTSRC=		${SRCTOP}/contrib/compiler-rt
 
 .PATH:		${CRTSRC}/lib
 
-CLANGDIR=	/usr/lib/clang/5.0.0
+CLANGDIR=	/usr/lib/clang/5.0.1
 LIBDIR=		${CLANGDIR}/lib/freebsd
 
 NO_PIC=

tools/build/mk/OptionalObsoleteFiles.inc

@@ -1328,119 +1328,122 @@ OLD_FILES+=usr/bin/clang-cpp
 OLD_FILES+=usr/bin/clang-tblgen
 OLD_FILES+=usr/bin/llvm-objdump
 OLD_FILES+=usr/bin/llvm-tblgen
-OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/allocator_interface.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/sanitizer/allocator_interface.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/asan_interface.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/sanitizer/asan_interface.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/common_interface_defs.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/sanitizer/common_interface_defs.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/coverage_interface.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/sanitizer/coverage_interface.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/dfsan_interface.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/sanitizer/dfsan_interface.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/esan_interface.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/sanitizer/esan_interface.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/linux_syscall_hooks.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/sanitizer/linux_syscall_hooks.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/lsan_interface.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/sanitizer/lsan_interface.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/msan_interface.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/sanitizer/msan_interface.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/sanitizer/tsan_interface_atomic.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/sanitizer/tsan_interface.h
-OLD_DIRS+=usr/lib/clang/5.0.0/include/sanitizer
+OLD_FILES+=usr/lib/clang/5.0.1/include/sanitizer/tsan_interface_atomic.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/__clang_cuda_builtin_vars.h
+OLD_DIRS+=usr/lib/clang/5.0.1/include/sanitizer
-OLD_FILES+=usr/lib/clang/5.0.0/include/__clang_cuda_cmath.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/__clang_cuda_builtin_vars.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/__clang_cuda_complex_builtins.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/__clang_cuda_cmath.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/__clang_cuda_intrinsics.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/__clang_cuda_complex_builtins.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/__clang_cuda_math_forward_declares.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/__clang_cuda_intrinsics.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/__clang_cuda_runtime_wrapper.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/__clang_cuda_math_forward_declares.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/__stddef_max_align_t.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/__clang_cuda_runtime_wrapper.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/__wmmintrin_aes.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/__stddef_max_align_t.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/__wmmintrin_pclmul.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/__wmmintrin_aes.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/adxintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/__wmmintrin_pclmul.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/altivec.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/adxintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/ammintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/altivec.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/arm_acle.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/ammintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/arm_neon.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/arm_acle.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/armintr.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/arm_neon.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/avx2intrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/armintr.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/avx512bwintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/avx2intrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/avx512cdintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/avx512bwintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/avx512dqintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/avx512cdintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/avx512erintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/avx512dqintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/avx512fintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/avx512erintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/avx512ifmaintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/avx512fintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/avx512ifmavlintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/avx512ifmaintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/avx512pfintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/avx512ifmavlintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/avx512vbmiintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/avx512pfintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/avx512vbmivlintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/avx512vbmiintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/avx512vlbwintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/avx512vbmivlintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/avx512vlcdintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/avx512vlbwintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/avx512vldqintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/avx512vlcdintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/avx512vlintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/avx512vldqintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/avxintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/avx512vlintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/bmi2intrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/avx512vpopcntdqintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/bmiintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/avxintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/clflushoptintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/bmi2intrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/clzerointrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/bmiintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/cpuid.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/clflushoptintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/emmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/clzerointrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/f16cintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/cpuid.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/fma4intrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/emmintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/fmaintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/f16cintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/fxsrintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/fma4intrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/htmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/fmaintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/htmxlintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/fxsrintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/ia32intrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/htmintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/immintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/htmxlintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/lwpintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/ia32intrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/lzcntintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/immintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/mm3dnow.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/lwpintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/mm_malloc.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/lzcntintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/mmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/mm3dnow.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/module.modulemap
+OLD_FILES+=usr/lib/clang/5.0.1/include/mm_malloc.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/msa.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/mmintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/mwaitxintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/module.modulemap
-OLD_FILES+=usr/lib/clang/5.0.0/include/nmmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/msa.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/opencl-c.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/mwaitxintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/pkuintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/nmmintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/pmmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/opencl-c.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/popcntintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/pkuintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/prfchwintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/pmmintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/rdseedintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/popcntintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/rtmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/prfchwintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/s390intrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/rdseedintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/shaintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/rtmintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/smmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/s390intrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/tbmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/shaintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/tmmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/smmintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/vadefs.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/tbmintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/vecintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/tmmintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/wmmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/vadefs.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/x86intrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/vecintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/xmmintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/wmmintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/xopintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/x86intrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/xsavecintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/xmmintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/xsaveintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/xopintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/xsaveoptintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/xsavecintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/xsavesintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/xsaveintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/include/xtestintrin.h
+OLD_FILES+=usr/lib/clang/5.0.1/include/xsaveoptintrin.h
-OLD_DIRS+=usr/lib/clang/5.0.0/include
+OLD_FILES+=usr/lib/clang/5.0.1/include/xsavesintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.asan-i386.a
+OLD_FILES+=usr/lib/clang/5.0.1/include/xtestintrin.h
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.asan-i386.so
+OLD_DIRS+=usr/lib/clang/5.0.1/include
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.asan-preinit-i386.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.asan-i386.a
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.asan-preinit-x86_64.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.asan-i386.so
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.asan-x86_64.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.asan-preinit-i386.a
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.asan-x86_64.so
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.asan-preinit-x86_64.a
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.asan_cxx-i386.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.asan-x86_64.a
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.asan_cxx-x86_64.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.asan-x86_64.so
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.profile-arm.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.asan_cxx-i386.a
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.profile-i386.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.asan_cxx-x86_64.a
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.profile-x86_64.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.profile-arm.a
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.safestack-i386.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.profile-armhf.a
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.safestack-x86_64.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.profile-i386.a
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.stats-i386.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.profile-x86_64.a
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.stats-x86_64.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.safestack-i386.a
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.stats_client-i386.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.safestack-x86_64.a
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.stats_client-x86_64.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.stats-i386.a
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.ubsan_standalone-i386.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.stats-x86_64.a
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.ubsan_standalone-x86_64.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.stats_client-i386.a
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.ubsan_standalone_cxx-i386.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.stats_client-x86_64.a
-OLD_FILES+=usr/lib/clang/5.0.0/lib/freebsd/libclang_rt.ubsan_standalone_cxx-x86_64.a
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.ubsan_standalone-i386.a
-OLD_DIRS+=usr/lib/clang/5.0.0/lib/freebsd
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.ubsan_standalone-x86_64.a
-OLD_DIRS+=usr/lib/clang/5.0.0/lib
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.ubsan_standalone_cxx-i386.a
-OLD_DIRS+=usr/lib/clang/5.0.0
+OLD_FILES+=usr/lib/clang/5.0.1/lib/freebsd/libclang_rt.ubsan_standalone_cxx-x86_64.a
+OLD_DIRS+=usr/lib/clang/5.0.1/lib/freebsd
+OLD_DIRS+=usr/lib/clang/5.0.1/lib
+OLD_DIRS+=usr/lib/clang/5.0.1
 OLD_DIRS+=usr/lib/clang
 OLD_FILES+=usr/share/doc/llvm/clang/LICENSE.TXT
 OLD_DIRS+=usr/share/doc/llvm/clang