mirror of
https://github.com/freebsd/freebsd-src
synced 2024-09-23 02:04:46 +00:00
Sync with sys/i386/isa/clock.c revision 1.116.
This commit is contained in:
KATO Takenori
parent
42fce6372e
commit
d16238bcdd
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=34594
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.47 1998/03/01 05:22:25 kato Exp $
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* $Id: clock.c,v 1.48 1998/03/07 15:43:43 kato Exp $
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*/
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/*
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@ -98,8 +98,13 @@
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#define disable_intr() CLOCK_DISABLE_INTR()
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#define enable_intr() CLOCK_ENABLE_INTR()
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#ifdef APIC_IO
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#include <i386/isa/intr_machdep.h>
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/* The interrupt triggered by the 8254 (timer) chip */
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int apic_8254_intr;
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static u_long read_intr_count __P((int vec));
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static void setup_8254_mixed_mode __P((void));
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#endif
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#endif /* SMP */
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/*
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@ -1191,7 +1196,7 @@ void
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cpu_initclocks()
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{
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#ifdef APIC_IO
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int x;
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int apic_8254_trial;
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#endif /* APIC_IO */
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#ifndef PC98
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int diag;
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@ -1215,46 +1220,25 @@ cpu_initclocks()
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/* Finish initializing 8253 timer 0. */
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#ifdef APIC_IO
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/* 1st look for ExtInt on pin 0 */
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if (apic_int_type(0, 0) == 3) {
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/*
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* Allow 8254 timer to INTerrupt 8259:
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* re-initialize master 8259:
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* reset; prog 4 bytes, single ICU, edge triggered
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*/
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outb(IO_ICU1, 0x13);
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outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
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outb(IO_ICU1 + 1, 0x00); /* ignore slave */
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outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
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outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
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/* program IO APIC for type 3 INT on INT0 */
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if (ext_int_setup(0, 0) < 0)
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panic("8254 redirect via APIC pin0 impossible!");
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x = 0;
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/* XXX if (bootverbose) */
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printf("APIC_IO: routing 8254 via 8259 on pin 0\n");
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apic_8254_intr = isa_apic_pin(0);
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apic_8254_trial = 0;
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if (apic_8254_intr >= 0 ) {
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if (apic_int_type(0, 0) == 3)
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apic_8254_trial = 1;
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} else {
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/* look for ExtInt on pin 0 */
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if (apic_int_type(0, 0) == 3) {
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apic_8254_intr = 0;
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setup_8254_mixed_mode();
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} else
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panic("APIC_IO: Cannot route 8254 interrupt to CPU");
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}
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/* failing that, look for 8254 on pin 2 */
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else if (isa_apic_pin(0) == 2) {
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x = 2;
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/* XXX if (bootverbose) */
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printf("APIC_IO: routing 8254 via pin 2\n");
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}
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/* better write that 8254 INT discover code... */
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else
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panic("neither pin 0 or pin 2 works for 8254");
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apic_8254_intr = x;
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register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0,
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register_intr(/* irq */ apic_8254_intr, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(1 << x);
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INTREN(1 << apic_8254_intr);
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#else /* APIC_IO */
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register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0,
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@ -1293,8 +1277,82 @@ cpu_initclocks()
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writertc(RTC_STATUSB, rtc_statusb);
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#endif /* !PC98 */
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#ifdef APIC_IO
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if (apic_8254_trial) {
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printf("APIC_IO: Testing 8254 interrupt delivery\n");
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__asm __volatile("sti" : : : "memory");
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while (read_intr_count(8) < 6)
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__asm __volatile("sti" : : : "memory");
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if (read_intr_count(apic_8254_intr) < 3) {
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/*
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* The MP table is broken.
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* The 8254 was not connected to the specified pin
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* on the IO APIC.
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* Workaround: Limited variant of mixed mode.
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*/
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INTRDIS(1 << apic_8254_intr);
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unregister_intr(apic_8254_intr,
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/* XXX */ (inthand2_t *) clkintr);
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printf("APIC_IO: Broken MP table detected: "
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"8254 is not connected to IO APIC int pin %d\n",
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apic_8254_intr);
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apic_8254_intr = 0;
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setup_8254_mixed_mode();
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register_intr(/* irq */ apic_8254_intr, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(1 << apic_8254_intr);
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}
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}
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if (apic_8254_intr)
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printf("APIC_IO: routing 8254 via pin %d\n",apic_8254_intr);
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else
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printf("APIC_IO: routing 8254 via 8259 on pin 0\n");
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#endif
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}
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#ifdef APIC_IO
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static u_long
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read_intr_count(int vec)
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{
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u_long *up;
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up = intr_countp[vec];
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if (up)
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return *up;
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return 0UL;
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}
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static void
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setup_8254_mixed_mode()
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{
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/*
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* Allow 8254 timer to INTerrupt 8259:
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* re-initialize master 8259:
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* reset; prog 4 bytes, single ICU, edge triggered
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*/
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outb(IO_ICU1, 0x13);
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#ifdef PC98
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outb(IO_ICU1 + 2, NRSVIDT); /* start vector (unused) */
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outb(IO_ICU1 + 2, 0x00); /* ignore slave */
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outb(IO_ICU1 + 2, 0x03); /* auto EOI, 8086 */
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outb(IO_ICU1 + 2, 0xfe); /* unmask INT0 */
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#else
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outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
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outb(IO_ICU1 + 1, 0x00); /* ignore slave */
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outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
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outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
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#endif
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/* program IO APIC for type 3 INT on INT0 */
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if (ext_int_setup(0, 0) < 0)
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panic("8254 redirect via APIC pin0 impossible!");
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}
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#endif
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void
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setstatclockrate(int newhz)
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{
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@ -34,7 +34,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
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* $Id: clock.c,v 1.47 1998/03/01 05:22:25 kato Exp $
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* $Id: clock.c,v 1.48 1998/03/07 15:43:43 kato Exp $
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*/
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/*
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@ -98,8 +98,13 @@
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#define disable_intr() CLOCK_DISABLE_INTR()
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#define enable_intr() CLOCK_ENABLE_INTR()
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#ifdef APIC_IO
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#include <i386/isa/intr_machdep.h>
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/* The interrupt triggered by the 8254 (timer) chip */
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int apic_8254_intr;
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static u_long read_intr_count __P((int vec));
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static void setup_8254_mixed_mode __P((void));
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#endif
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#endif /* SMP */
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/*
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@ -1191,7 +1196,7 @@ void
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cpu_initclocks()
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{
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#ifdef APIC_IO
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int x;
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int apic_8254_trial;
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#endif /* APIC_IO */
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#ifndef PC98
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int diag;
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@ -1215,46 +1220,25 @@ cpu_initclocks()
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/* Finish initializing 8253 timer 0. */
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#ifdef APIC_IO
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/* 1st look for ExtInt on pin 0 */
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if (apic_int_type(0, 0) == 3) {
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/*
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* Allow 8254 timer to INTerrupt 8259:
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* re-initialize master 8259:
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* reset; prog 4 bytes, single ICU, edge triggered
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*/
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outb(IO_ICU1, 0x13);
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outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
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outb(IO_ICU1 + 1, 0x00); /* ignore slave */
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outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
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outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
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/* program IO APIC for type 3 INT on INT0 */
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if (ext_int_setup(0, 0) < 0)
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panic("8254 redirect via APIC pin0 impossible!");
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x = 0;
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/* XXX if (bootverbose) */
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printf("APIC_IO: routing 8254 via 8259 on pin 0\n");
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apic_8254_intr = isa_apic_pin(0);
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apic_8254_trial = 0;
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if (apic_8254_intr >= 0 ) {
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if (apic_int_type(0, 0) == 3)
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apic_8254_trial = 1;
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} else {
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/* look for ExtInt on pin 0 */
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if (apic_int_type(0, 0) == 3) {
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apic_8254_intr = 0;
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setup_8254_mixed_mode();
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} else
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panic("APIC_IO: Cannot route 8254 interrupt to CPU");
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}
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/* failing that, look for 8254 on pin 2 */
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else if (isa_apic_pin(0) == 2) {
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x = 2;
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/* XXX if (bootverbose) */
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printf("APIC_IO: routing 8254 via pin 2\n");
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}
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/* better write that 8254 INT discover code... */
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else
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panic("neither pin 0 or pin 2 works for 8254");
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apic_8254_intr = x;
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register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0,
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register_intr(/* irq */ apic_8254_intr, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(1 << x);
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INTREN(1 << apic_8254_intr);
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#else /* APIC_IO */
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register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0,
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@ -1293,8 +1277,82 @@ cpu_initclocks()
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writertc(RTC_STATUSB, rtc_statusb);
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#endif /* !PC98 */
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#ifdef APIC_IO
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if (apic_8254_trial) {
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printf("APIC_IO: Testing 8254 interrupt delivery\n");
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__asm __volatile("sti" : : : "memory");
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while (read_intr_count(8) < 6)
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__asm __volatile("sti" : : : "memory");
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if (read_intr_count(apic_8254_intr) < 3) {
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/*
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* The MP table is broken.
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* The 8254 was not connected to the specified pin
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* on the IO APIC.
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* Workaround: Limited variant of mixed mode.
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*/
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INTRDIS(1 << apic_8254_intr);
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unregister_intr(apic_8254_intr,
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/* XXX */ (inthand2_t *) clkintr);
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printf("APIC_IO: Broken MP table detected: "
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"8254 is not connected to IO APIC int pin %d\n",
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apic_8254_intr);
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apic_8254_intr = 0;
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setup_8254_mixed_mode();
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register_intr(/* irq */ apic_8254_intr, /* XXX id */ 0, /* flags */ 0,
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/* XXX */ (inthand2_t *)clkintr, &clk_imask,
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/* unit */ 0);
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INTREN(1 << apic_8254_intr);
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}
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}
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if (apic_8254_intr)
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printf("APIC_IO: routing 8254 via pin %d\n",apic_8254_intr);
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else
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printf("APIC_IO: routing 8254 via 8259 on pin 0\n");
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#endif
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}
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#ifdef APIC_IO
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static u_long
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read_intr_count(int vec)
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{
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u_long *up;
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up = intr_countp[vec];
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if (up)
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return *up;
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return 0UL;
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}
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static void
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setup_8254_mixed_mode()
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{
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/*
|
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* Allow 8254 timer to INTerrupt 8259:
|
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* re-initialize master 8259:
|
||||
* reset; prog 4 bytes, single ICU, edge triggered
|
||||
*/
|
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outb(IO_ICU1, 0x13);
|
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#ifdef PC98
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outb(IO_ICU1 + 2, NRSVIDT); /* start vector (unused) */
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outb(IO_ICU1 + 2, 0x00); /* ignore slave */
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outb(IO_ICU1 + 2, 0x03); /* auto EOI, 8086 */
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outb(IO_ICU1 + 2, 0xfe); /* unmask INT0 */
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#else
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outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
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outb(IO_ICU1 + 1, 0x00); /* ignore slave */
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outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
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outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
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#endif
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/* program IO APIC for type 3 INT on INT0 */
|
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if (ext_int_setup(0, 0) < 0)
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panic("8254 redirect via APIC pin0 impossible!");
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}
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#endif
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void
|
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setstatclockrate(int newhz)
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{
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|
|
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|
|
@ -34,7 +34,7 @@
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* SUCH DAMAGE.
|
||||
*
|
||||
* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
|
||||
* $Id: clock.c,v 1.47 1998/03/01 05:22:25 kato Exp $
|
||||
* $Id: clock.c,v 1.48 1998/03/07 15:43:43 kato Exp $
|
||||
*/
|
||||
|
||||
/*
|
||||
|
|
@ -98,8 +98,13 @@
|
|||
#define disable_intr() CLOCK_DISABLE_INTR()
|
||||
#define enable_intr() CLOCK_ENABLE_INTR()
|
||||
|
||||
#ifdef APIC_IO
|
||||
#include <i386/isa/intr_machdep.h>
|
||||
/* The interrupt triggered by the 8254 (timer) chip */
|
||||
int apic_8254_intr;
|
||||
static u_long read_intr_count __P((int vec));
|
||||
static void setup_8254_mixed_mode __P((void));
|
||||
#endif
|
||||
#endif /* SMP */
|
||||
|
||||
/*
|
||||
|
|
@ -1191,7 +1196,7 @@ void
|
|||
cpu_initclocks()
|
||||
{
|
||||
#ifdef APIC_IO
|
||||
int x;
|
||||
int apic_8254_trial;
|
||||
#endif /* APIC_IO */
|
||||
#ifndef PC98
|
||||
int diag;
|
||||
|
|
@ -1215,46 +1220,25 @@ cpu_initclocks()
|
|||
/* Finish initializing 8253 timer 0. */
|
||||
#ifdef APIC_IO
|
||||
|
||||
/* 1st look for ExtInt on pin 0 */
|
||||
if (apic_int_type(0, 0) == 3) {
|
||||
/*
|
||||
* Allow 8254 timer to INTerrupt 8259:
|
||||
* re-initialize master 8259:
|
||||
* reset; prog 4 bytes, single ICU, edge triggered
|
||||
*/
|
||||
outb(IO_ICU1, 0x13);
|
||||
outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
|
||||
outb(IO_ICU1 + 1, 0x00); /* ignore slave */
|
||||
outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
|
||||
outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
|
||||
|
||||
/* program IO APIC for type 3 INT on INT0 */
|
||||
if (ext_int_setup(0, 0) < 0)
|
||||
panic("8254 redirect via APIC pin0 impossible!");
|
||||
|
||||
x = 0;
|
||||
/* XXX if (bootverbose) */
|
||||
printf("APIC_IO: routing 8254 via 8259 on pin 0\n");
|
||||
apic_8254_intr = isa_apic_pin(0);
|
||||
apic_8254_trial = 0;
|
||||
if (apic_8254_intr >= 0 ) {
|
||||
if (apic_int_type(0, 0) == 3)
|
||||
apic_8254_trial = 1;
|
||||
} else {
|
||||
/* look for ExtInt on pin 0 */
|
||||
if (apic_int_type(0, 0) == 3) {
|
||||
apic_8254_intr = 0;
|
||||
setup_8254_mixed_mode();
|
||||
} else
|
||||
panic("APIC_IO: Cannot route 8254 interrupt to CPU");
|
||||
}
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||||
|
||||
/* failing that, look for 8254 on pin 2 */
|
||||
else if (isa_apic_pin(0) == 2) {
|
||||
x = 2;
|
||||
/* XXX if (bootverbose) */
|
||||
printf("APIC_IO: routing 8254 via pin 2\n");
|
||||
}
|
||||
|
||||
/* better write that 8254 INT discover code... */
|
||||
else
|
||||
panic("neither pin 0 or pin 2 works for 8254");
|
||||
|
||||
apic_8254_intr = x;
|
||||
|
||||
register_intr(/* irq */ x, /* XXX id */ 0, /* flags */ 0,
|
||||
register_intr(/* irq */ apic_8254_intr, /* XXX id */ 0, /* flags */ 0,
|
||||
/* XXX */ (inthand2_t *)clkintr, &clk_imask,
|
||||
/* unit */ 0);
|
||||
INTREN(1 << x);
|
||||
|
||||
INTREN(1 << apic_8254_intr);
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||||
|
||||
#else /* APIC_IO */
|
||||
|
||||
register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0,
|
||||
|
|
@ -1293,8 +1277,82 @@ cpu_initclocks()
|
|||
|
||||
writertc(RTC_STATUSB, rtc_statusb);
|
||||
#endif /* !PC98 */
|
||||
|
||||
#ifdef APIC_IO
|
||||
if (apic_8254_trial) {
|
||||
|
||||
printf("APIC_IO: Testing 8254 interrupt delivery\n");
|
||||
__asm __volatile("sti" : : : "memory");
|
||||
while (read_intr_count(8) < 6)
|
||||
__asm __volatile("sti" : : : "memory");
|
||||
if (read_intr_count(apic_8254_intr) < 3) {
|
||||
/*
|
||||
* The MP table is broken.
|
||||
* The 8254 was not connected to the specified pin
|
||||
* on the IO APIC.
|
||||
* Workaround: Limited variant of mixed mode.
|
||||
*/
|
||||
INTRDIS(1 << apic_8254_intr);
|
||||
unregister_intr(apic_8254_intr,
|
||||
/* XXX */ (inthand2_t *) clkintr);
|
||||
printf("APIC_IO: Broken MP table detected: "
|
||||
"8254 is not connected to IO APIC int pin %d\n",
|
||||
apic_8254_intr);
|
||||
|
||||
apic_8254_intr = 0;
|
||||
setup_8254_mixed_mode();
|
||||
register_intr(/* irq */ apic_8254_intr, /* XXX id */ 0, /* flags */ 0,
|
||||
/* XXX */ (inthand2_t *)clkintr, &clk_imask,
|
||||
/* unit */ 0);
|
||||
INTREN(1 << apic_8254_intr);
|
||||
}
|
||||
|
||||
}
|
||||
if (apic_8254_intr)
|
||||
printf("APIC_IO: routing 8254 via pin %d\n",apic_8254_intr);
|
||||
else
|
||||
printf("APIC_IO: routing 8254 via 8259 on pin 0\n");
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#ifdef APIC_IO
|
||||
static u_long
|
||||
read_intr_count(int vec)
|
||||
{
|
||||
u_long *up;
|
||||
up = intr_countp[vec];
|
||||
if (up)
|
||||
return *up;
|
||||
return 0UL;
|
||||
}
|
||||
|
||||
static void
|
||||
setup_8254_mixed_mode()
|
||||
{
|
||||
/*
|
||||
* Allow 8254 timer to INTerrupt 8259:
|
||||
* re-initialize master 8259:
|
||||
* reset; prog 4 bytes, single ICU, edge triggered
|
||||
*/
|
||||
outb(IO_ICU1, 0x13);
|
||||
#ifdef PC98
|
||||
outb(IO_ICU1 + 2, NRSVIDT); /* start vector (unused) */
|
||||
outb(IO_ICU1 + 2, 0x00); /* ignore slave */
|
||||
outb(IO_ICU1 + 2, 0x03); /* auto EOI, 8086 */
|
||||
outb(IO_ICU1 + 2, 0xfe); /* unmask INT0 */
|
||||
#else
|
||||
outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
|
||||
outb(IO_ICU1 + 1, 0x00); /* ignore slave */
|
||||
outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
|
||||
outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
|
||||
#endif
|
||||
/* program IO APIC for type 3 INT on INT0 */
|
||||
if (ext_int_setup(0, 0) < 0)
|
||||
panic("8254 redirect via APIC pin0 impossible!");
|
||||
}
|
||||
#endif
|
||||
|
||||
void
|
||||
setstatclockrate(int newhz)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in a new issue