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Opt for performance over power-saving on Intel CPUs that have a
P-state but not C-state invariant TSC by changing the default behavior to leaving the TSC enabled as the timecounter and disabling C2+ instead of disabling the TSC by default. Discussed with: jkim Tested by: Jan Kokemuller <jan.kokemueller@gmail.com>
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=277900
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@ -522,17 +522,22 @@ init_TSC_tc(void)
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}
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/*
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* We cannot use the TSC if it stops incrementing while idle.
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* Intel CPUs without a C-state invariant TSC can stop the TSC
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* in either C2 or C3.
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* in either C2 or C3. Disable use of C2 and C3 while using
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* the TSC as the timecounter. The timecounter can be changed
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* to enable C2 and C3.
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*
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* Note that the TSC is used as the cputicker for computing
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* thread runtime regardless of the timecounter setting, so
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* using an alternate timecounter and enabling C2 or C3 can
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* result incorrect runtimes for kernel idle threads (but not
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* for any non-idle threads).
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*/
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if (cpu_deepest_sleep >= 2 && cpu_vendor_id == CPU_VENDOR_INTEL &&
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(amd_pminfo & AMDPM_TSC_INVARIANT) == 0) {
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tsc_timecounter.tc_quality = -1000;
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tsc_timecounter.tc_flags |= TC_FLAGS_C2STOP;
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if (bootverbose)
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printf("TSC timecounter disabled: C2/C3 may halt it.\n");
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goto init;
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printf("TSC timecounter disables C2 and C3.\n");
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}
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/*
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