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It seems that enabling Tx and Rx before setting descriptor DMA
addresses shall access invalid descriptor DMA addresses on PCIe hardwares and then panicked the system. To fix it set descriptor DMA addresses before enabling Tx and Rx such that hardware can see valid descriptor DMA addresses. Also set RL_EARLY_TX_THRESH before starting Tx and Rx. Reported by: steve.tell AT crashmail DOT de Tested by: steve.tell AT crashmail DOT de Obtained from: NetBSD MFC after: 1 week
This commit is contained in:
parent
f9734398e3
commit
d01fac16ac
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=166178
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@ -2318,6 +2318,20 @@ re_init_locked(sc)
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re_rx_list_init(sc);
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re_rx_list_init(sc);
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re_tx_list_init(sc);
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re_tx_list_init(sc);
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/*
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* Load the addresses of the RX and TX lists into the chip.
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*/
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CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
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RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
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CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
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RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
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CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
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RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
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CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
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RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
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/*
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/*
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* Enable transmit and receive.
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* Enable transmit and receive.
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*/
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*/
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@ -2335,6 +2349,9 @@ re_init_locked(sc)
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RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
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RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
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} else
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} else
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CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
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CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
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CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
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CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
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CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
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/* Set the individual bit to receive frames for this host only. */
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/* Set the individual bit to receive frames for this host only. */
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@ -2389,21 +2406,6 @@ re_init_locked(sc)
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/* Enable receiver and transmitter. */
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/* Enable receiver and transmitter. */
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CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
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CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
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#endif
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#endif
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/*
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* Load the addresses of the RX and TX lists into the chip.
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*/
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CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
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RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
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CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
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RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
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CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
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RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
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CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
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RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
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CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
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#ifdef RE_TX_MODERATION
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#ifdef RE_TX_MODERATION
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/*
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/*
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