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Ensure the I-Cache is correctly handled in arm64_icache_sync_range
The cache_handle_range macro to handle the arm64 instruction and data cache operations would return when it was complete. This causes problems for arm64_icache_sync_range and arm64_icache_sync_range_checked as they assume they can execute the i-cache handling instruction after it has been called. Fix this by making this assumption correct. While here add missing instruction barriers and adjust the style to match the rest of the assembly. Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D18838
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=343042
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@ -77,7 +77,6 @@ __FBSDID("$FreeBSD$");
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.if \ic != 0
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isb
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.endif
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ret
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.endm
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ENTRY(arm64_nullop)
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@ -112,6 +111,7 @@ END(arm64_tlb_flushID)
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*/
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ENTRY(arm64_dcache_wb_range)
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cache_handle_range dcop = cvac
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ret
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END(arm64_dcache_wb_range)
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/*
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@ -119,6 +119,7 @@ END(arm64_dcache_wb_range)
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*/
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ENTRY(arm64_dcache_wbinv_range)
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cache_handle_range dcop = civac
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ret
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END(arm64_dcache_wbinv_range)
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/*
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@ -129,6 +130,7 @@ END(arm64_dcache_wbinv_range)
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*/
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ENTRY(arm64_dcache_inv_range)
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cache_handle_range dcop = ivac
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ret
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END(arm64_dcache_inv_range)
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/*
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@ -136,6 +138,7 @@ END(arm64_dcache_inv_range)
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*/
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ENTRY(arm64_idcache_wbinv_range)
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cache_handle_range dcop = civac, ic = 1, icop = ivau
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ret
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END(arm64_idcache_wbinv_range)
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/*
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@ -150,6 +153,8 @@ ENTRY(arm64_icache_sync_range)
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cache_handle_range dcop = cvau
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ic ialluis
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dsb ish
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isb
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ret
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END(arm64_icache_sync_range)
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/*
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@ -161,7 +166,8 @@ ENTRY(arm64_icache_sync_range_checked)
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/* XXX: See comment in arm64_icache_sync_range */
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cache_handle_range dcop = cvau
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ic ialluis
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dsb ish
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dsb ish
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isb
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SET_FAULT_HANDLER(xzr, x6)
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mov x0, #0
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ret
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