mirror of
https://github.com/freebsd/freebsd-src
synced 2024-09-24 18:54:52 +00:00
Reinstate AUTO_EOI_1. This did break suspend/resume on some portables.
In particular mine. We may want to make it a negative option to keep GENERIC sane, ie NO_AUTO_EOI_1.
This commit is contained in:
Poul-Henning Kamp
parent
5327442589
commit
c92a064d21
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=13505
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@ -560,7 +560,11 @@ isa_defaultirq()
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outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
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outb(IO_ICU1+1, NRSVIDT); /* starting at this vector index */
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outb(IO_ICU1+1, 1<<2); /* slave on line 2 */
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outb(IO_ICU1+1, 2 | 1); /* (master) auto EOI, 8086 mode */
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#ifdef AUTO_EOI_1
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outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */
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#else
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outb(IO_ICU1+1, 1); /* 8086 mode */
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#endif
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outb(IO_ICU1+1, 0xff); /* leave interrupts masked */
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outb(IO_ICU1, 0x0a); /* default to IRR on read */
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outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
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@ -809,8 +813,6 @@ isa_strayintr(d)
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* testing that the in-service bit is _not_ set. The test
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* must be done before sending an EOI so it can't be done if
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* we are using AUTO_EOI_1.
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*
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* XXX AUTO_EOI_1 is now standard.
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*/
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if (intrcnt[NR_DEVICES + d] <= 5)
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log(LOG_ERR, "stray irq %d\n", d);
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@ -1,6 +1,6 @@
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/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $Id: vector.s,v 1.15 1995/12/23 16:53:57 davidg Exp $
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* $Id: vector.s,v 1.16 1995/12/27 11:22:05 markm Exp $
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*/
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#include <i386/isa/icu.h>
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@ -11,15 +11,29 @@
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#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
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#define IRQ_BYTE(irq_num) ((irq_num) / 8)
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#ifdef AUTO_EOI_1
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#define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
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#define OUTB_ICU1
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#else
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#define ENABLE_ICU1 \
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movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
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OUTB_ICU1 /* ... to clear in service bit */
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#define OUTB_ICU1 \
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FASTER_NOP ; \
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outb %al,$IO_ICU1
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#endif
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#ifdef AUTO_EOI_2
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/*
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* The data sheet says no auto-EOI on slave, but it sometimes works.
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*/
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#define ENABLE_ICU2
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#define ENABLE_ICU1_AND_2 ENABLE_ICU1
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#else
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#define ENABLE_ICU2 \
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movb $ICU_EOI,%al ; \
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outb %al,$IO_ICU2 ;
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#define ENABLE_ICU1_AND_2 \
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movb $ICU_EOI,%al ; /* as above */ \
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FASTER_NOP ; \
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outb %al,$IO_ICU2 ; /* but do second icu first ... */ \
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OUTB_ICU1 /* ... then first icu (if !AUTO_EOI_1) */
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#endif
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#ifdef FAST_INTR_HANDLER_USES_ES
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@ -154,6 +168,7 @@ IDTVEC(intr/**/irq_num) ; \
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movb _imen + IRQ_BYTE(irq_num),%al ; \
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orb $IRQ_BIT(irq_num),%al ; \
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movb %al,_imen + IRQ_BYTE(irq_num) ; \
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FASTER_NOP ; \
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outb %al,$icu+1 ; \
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enable_icus ; \
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incl _cnt+V_INTR ; /* tally interrupts */ \
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@ -176,6 +191,7 @@ Xresume/**/irq_num: ; \
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movb _imen + IRQ_BYTE(irq_num),%al ; \
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andb $~IRQ_BIT(irq_num),%al ; \
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movb %al,_imen + IRQ_BYTE(irq_num) ; \
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FASTER_NOP ; \
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outb %al,$icu+1 ; \
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sti ; /* XXX _doreti repeats the cli/sti */ \
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MEXITCOUNT ; \
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@ -194,38 +210,38 @@ Xresume/**/irq_num: ; \
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iret
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MCOUNT_LABEL(bintr)
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FAST_INTR(0,)
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FAST_INTR(1,)
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FAST_INTR(2,)
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FAST_INTR(3,)
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FAST_INTR(4,)
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FAST_INTR(5,)
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FAST_INTR(6,)
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FAST_INTR(7,)
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FAST_INTR(8, ENABLE_ICU2)
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FAST_INTR(9, ENABLE_ICU2)
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FAST_INTR(10, ENABLE_ICU2)
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FAST_INTR(11, ENABLE_ICU2)
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FAST_INTR(12, ENABLE_ICU2)
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FAST_INTR(13, ENABLE_ICU2)
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FAST_INTR(14, ENABLE_ICU2)
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FAST_INTR(15, ENABLE_ICU2)
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INTR(0, IO_ICU1,, al)
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INTR(1, IO_ICU1,, al)
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INTR(2, IO_ICU1,, al)
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INTR(3, IO_ICU1,, al)
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INTR(4, IO_ICU1,, al)
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INTR(5, IO_ICU1,, al)
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INTR(6, IO_ICU1,, al)
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INTR(7, IO_ICU1,, al)
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INTR(8, IO_ICU2, ENABLE_ICU2, ah)
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INTR(9, IO_ICU2, ENABLE_ICU2, ah)
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INTR(10, IO_ICU2, ENABLE_ICU2, ah)
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INTR(11, IO_ICU2, ENABLE_ICU2, ah)
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INTR(12, IO_ICU2, ENABLE_ICU2, ah)
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INTR(13, IO_ICU2, ENABLE_ICU2, ah)
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INTR(14, IO_ICU2, ENABLE_ICU2, ah)
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INTR(15, IO_ICU2, ENABLE_ICU2, ah)
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FAST_INTR(0, ENABLE_ICU1)
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FAST_INTR(1, ENABLE_ICU1)
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FAST_INTR(2, ENABLE_ICU1)
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FAST_INTR(3, ENABLE_ICU1)
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FAST_INTR(4, ENABLE_ICU1)
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FAST_INTR(5, ENABLE_ICU1)
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FAST_INTR(6, ENABLE_ICU1)
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FAST_INTR(7, ENABLE_ICU1)
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FAST_INTR(8, ENABLE_ICU1_AND_2)
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FAST_INTR(9, ENABLE_ICU1_AND_2)
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FAST_INTR(10, ENABLE_ICU1_AND_2)
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FAST_INTR(11, ENABLE_ICU1_AND_2)
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FAST_INTR(12, ENABLE_ICU1_AND_2)
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FAST_INTR(13, ENABLE_ICU1_AND_2)
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FAST_INTR(14, ENABLE_ICU1_AND_2)
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FAST_INTR(15, ENABLE_ICU1_AND_2)
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INTR(0, IO_ICU1, ENABLE_ICU1, al)
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INTR(1, IO_ICU1, ENABLE_ICU1, al)
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INTR(2, IO_ICU1, ENABLE_ICU1, al)
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INTR(3, IO_ICU1, ENABLE_ICU1, al)
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INTR(4, IO_ICU1, ENABLE_ICU1, al)
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INTR(5, IO_ICU1, ENABLE_ICU1, al)
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INTR(6, IO_ICU1, ENABLE_ICU1, al)
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INTR(7, IO_ICU1, ENABLE_ICU1, al)
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INTR(8, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(9, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(10, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(11, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(12, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(13, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(14, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(15, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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MCOUNT_LABEL(eintr)
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.data
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@ -1,6 +1,6 @@
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/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $Id: vector.s,v 1.15 1995/12/23 16:53:57 davidg Exp $
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* $Id: vector.s,v 1.16 1995/12/27 11:22:05 markm Exp $
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*/
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#include <i386/isa/icu.h>
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@ -11,15 +11,29 @@
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#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
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#define IRQ_BYTE(irq_num) ((irq_num) / 8)
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#ifdef AUTO_EOI_1
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#define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
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#define OUTB_ICU1
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#else
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#define ENABLE_ICU1 \
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movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
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OUTB_ICU1 /* ... to clear in service bit */
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#define OUTB_ICU1 \
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FASTER_NOP ; \
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outb %al,$IO_ICU1
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#endif
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#ifdef AUTO_EOI_2
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/*
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* The data sheet says no auto-EOI on slave, but it sometimes works.
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*/
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#define ENABLE_ICU2
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#define ENABLE_ICU1_AND_2 ENABLE_ICU1
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#else
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#define ENABLE_ICU2 \
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movb $ICU_EOI,%al ; \
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outb %al,$IO_ICU2 ;
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#define ENABLE_ICU1_AND_2 \
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movb $ICU_EOI,%al ; /* as above */ \
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FASTER_NOP ; \
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outb %al,$IO_ICU2 ; /* but do second icu first ... */ \
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OUTB_ICU1 /* ... then first icu (if !AUTO_EOI_1) */
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#endif
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#ifdef FAST_INTR_HANDLER_USES_ES
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@ -154,6 +168,7 @@ IDTVEC(intr/**/irq_num) ; \
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movb _imen + IRQ_BYTE(irq_num),%al ; \
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orb $IRQ_BIT(irq_num),%al ; \
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movb %al,_imen + IRQ_BYTE(irq_num) ; \
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FASTER_NOP ; \
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outb %al,$icu+1 ; \
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enable_icus ; \
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incl _cnt+V_INTR ; /* tally interrupts */ \
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@ -176,6 +191,7 @@ Xresume/**/irq_num: ; \
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movb _imen + IRQ_BYTE(irq_num),%al ; \
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andb $~IRQ_BIT(irq_num),%al ; \
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movb %al,_imen + IRQ_BYTE(irq_num) ; \
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FASTER_NOP ; \
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outb %al,$icu+1 ; \
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sti ; /* XXX _doreti repeats the cli/sti */ \
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MEXITCOUNT ; \
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@ -194,38 +210,38 @@ Xresume/**/irq_num: ; \
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iret
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MCOUNT_LABEL(bintr)
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FAST_INTR(0,)
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FAST_INTR(1,)
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FAST_INTR(2,)
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FAST_INTR(3,)
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FAST_INTR(4,)
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FAST_INTR(5,)
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FAST_INTR(6,)
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FAST_INTR(7,)
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FAST_INTR(8, ENABLE_ICU2)
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FAST_INTR(9, ENABLE_ICU2)
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FAST_INTR(10, ENABLE_ICU2)
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FAST_INTR(11, ENABLE_ICU2)
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FAST_INTR(12, ENABLE_ICU2)
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FAST_INTR(13, ENABLE_ICU2)
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FAST_INTR(14, ENABLE_ICU2)
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FAST_INTR(15, ENABLE_ICU2)
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INTR(0, IO_ICU1,, al)
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INTR(1, IO_ICU1,, al)
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INTR(2, IO_ICU1,, al)
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INTR(3, IO_ICU1,, al)
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INTR(4, IO_ICU1,, al)
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INTR(5, IO_ICU1,, al)
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INTR(6, IO_ICU1,, al)
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INTR(7, IO_ICU1,, al)
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INTR(8, IO_ICU2, ENABLE_ICU2, ah)
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INTR(9, IO_ICU2, ENABLE_ICU2, ah)
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INTR(10, IO_ICU2, ENABLE_ICU2, ah)
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INTR(11, IO_ICU2, ENABLE_ICU2, ah)
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INTR(12, IO_ICU2, ENABLE_ICU2, ah)
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INTR(13, IO_ICU2, ENABLE_ICU2, ah)
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INTR(14, IO_ICU2, ENABLE_ICU2, ah)
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INTR(15, IO_ICU2, ENABLE_ICU2, ah)
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FAST_INTR(0, ENABLE_ICU1)
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FAST_INTR(1, ENABLE_ICU1)
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FAST_INTR(2, ENABLE_ICU1)
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FAST_INTR(3, ENABLE_ICU1)
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FAST_INTR(4, ENABLE_ICU1)
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FAST_INTR(5, ENABLE_ICU1)
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FAST_INTR(6, ENABLE_ICU1)
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FAST_INTR(7, ENABLE_ICU1)
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FAST_INTR(8, ENABLE_ICU1_AND_2)
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FAST_INTR(9, ENABLE_ICU1_AND_2)
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FAST_INTR(10, ENABLE_ICU1_AND_2)
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FAST_INTR(11, ENABLE_ICU1_AND_2)
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FAST_INTR(12, ENABLE_ICU1_AND_2)
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FAST_INTR(13, ENABLE_ICU1_AND_2)
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FAST_INTR(14, ENABLE_ICU1_AND_2)
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FAST_INTR(15, ENABLE_ICU1_AND_2)
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INTR(0, IO_ICU1, ENABLE_ICU1, al)
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INTR(1, IO_ICU1, ENABLE_ICU1, al)
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INTR(2, IO_ICU1, ENABLE_ICU1, al)
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INTR(3, IO_ICU1, ENABLE_ICU1, al)
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INTR(4, IO_ICU1, ENABLE_ICU1, al)
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INTR(5, IO_ICU1, ENABLE_ICU1, al)
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INTR(6, IO_ICU1, ENABLE_ICU1, al)
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INTR(7, IO_ICU1, ENABLE_ICU1, al)
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INTR(8, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(9, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(10, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(11, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(12, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(13, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(14, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(15, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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MCOUNT_LABEL(eintr)
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.data
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@ -560,7 +560,11 @@ isa_defaultirq()
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outb(IO_ICU1, 0x11); /* reset; program device, four bytes */
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outb(IO_ICU1+1, NRSVIDT); /* starting at this vector index */
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outb(IO_ICU1+1, 1<<2); /* slave on line 2 */
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outb(IO_ICU1+1, 2 | 1); /* (master) auto EOI, 8086 mode */
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#ifdef AUTO_EOI_1
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outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */
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#else
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outb(IO_ICU1+1, 1); /* 8086 mode */
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#endif
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outb(IO_ICU1+1, 0xff); /* leave interrupts masked */
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outb(IO_ICU1, 0x0a); /* default to IRR on read */
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outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */
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@ -809,8 +813,6 @@ isa_strayintr(d)
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* testing that the in-service bit is _not_ set. The test
|
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* must be done before sending an EOI so it can't be done if
|
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* we are using AUTO_EOI_1.
|
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*
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* XXX AUTO_EOI_1 is now standard.
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*/
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if (intrcnt[NR_DEVICES + d] <= 5)
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log(LOG_ERR, "stray irq %d\n", d);
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@ -1,6 +1,6 @@
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/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $Id: vector.s,v 1.15 1995/12/23 16:53:57 davidg Exp $
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* $Id: vector.s,v 1.16 1995/12/27 11:22:05 markm Exp $
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*/
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#include <i386/isa/icu.h>
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@ -11,15 +11,29 @@
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#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
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#define IRQ_BYTE(irq_num) ((irq_num) / 8)
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#ifdef AUTO_EOI_1
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#define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
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#define OUTB_ICU1
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#else
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#define ENABLE_ICU1 \
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movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
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OUTB_ICU1 /* ... to clear in service bit */
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#define OUTB_ICU1 \
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FASTER_NOP ; \
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outb %al,$IO_ICU1
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#endif
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#ifdef AUTO_EOI_2
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/*
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* The data sheet says no auto-EOI on slave, but it sometimes works.
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*/
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#define ENABLE_ICU2
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#define ENABLE_ICU1_AND_2 ENABLE_ICU1
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#else
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#define ENABLE_ICU2 \
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movb $ICU_EOI,%al ; \
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outb %al,$IO_ICU2 ;
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#define ENABLE_ICU1_AND_2 \
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movb $ICU_EOI,%al ; /* as above */ \
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FASTER_NOP ; \
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outb %al,$IO_ICU2 ; /* but do second icu first ... */ \
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OUTB_ICU1 /* ... then first icu (if !AUTO_EOI_1) */
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#endif
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#ifdef FAST_INTR_HANDLER_USES_ES
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@ -154,6 +168,7 @@ IDTVEC(intr/**/irq_num) ; \
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movb _imen + IRQ_BYTE(irq_num),%al ; \
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orb $IRQ_BIT(irq_num),%al ; \
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movb %al,_imen + IRQ_BYTE(irq_num) ; \
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FASTER_NOP ; \
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outb %al,$icu+1 ; \
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enable_icus ; \
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incl _cnt+V_INTR ; /* tally interrupts */ \
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@ -176,6 +191,7 @@ Xresume/**/irq_num: ; \
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movb _imen + IRQ_BYTE(irq_num),%al ; \
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andb $~IRQ_BIT(irq_num),%al ; \
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||||
movb %al,_imen + IRQ_BYTE(irq_num) ; \
|
||||
FASTER_NOP ; \
|
||||
outb %al,$icu+1 ; \
|
||||
sti ; /* XXX _doreti repeats the cli/sti */ \
|
||||
MEXITCOUNT ; \
|
||||
|
|
@ -194,38 +210,38 @@ Xresume/**/irq_num: ; \
|
|||
iret
|
||||
|
||||
MCOUNT_LABEL(bintr)
|
||||
FAST_INTR(0,)
|
||||
FAST_INTR(1,)
|
||||
FAST_INTR(2,)
|
||||
FAST_INTR(3,)
|
||||
FAST_INTR(4,)
|
||||
FAST_INTR(5,)
|
||||
FAST_INTR(6,)
|
||||
FAST_INTR(7,)
|
||||
FAST_INTR(8, ENABLE_ICU2)
|
||||
FAST_INTR(9, ENABLE_ICU2)
|
||||
FAST_INTR(10, ENABLE_ICU2)
|
||||
FAST_INTR(11, ENABLE_ICU2)
|
||||
FAST_INTR(12, ENABLE_ICU2)
|
||||
FAST_INTR(13, ENABLE_ICU2)
|
||||
FAST_INTR(14, ENABLE_ICU2)
|
||||
FAST_INTR(15, ENABLE_ICU2)
|
||||
INTR(0, IO_ICU1,, al)
|
||||
INTR(1, IO_ICU1,, al)
|
||||
INTR(2, IO_ICU1,, al)
|
||||
INTR(3, IO_ICU1,, al)
|
||||
INTR(4, IO_ICU1,, al)
|
||||
INTR(5, IO_ICU1,, al)
|
||||
INTR(6, IO_ICU1,, al)
|
||||
INTR(7, IO_ICU1,, al)
|
||||
INTR(8, IO_ICU2, ENABLE_ICU2, ah)
|
||||
INTR(9, IO_ICU2, ENABLE_ICU2, ah)
|
||||
INTR(10, IO_ICU2, ENABLE_ICU2, ah)
|
||||
INTR(11, IO_ICU2, ENABLE_ICU2, ah)
|
||||
INTR(12, IO_ICU2, ENABLE_ICU2, ah)
|
||||
INTR(13, IO_ICU2, ENABLE_ICU2, ah)
|
||||
INTR(14, IO_ICU2, ENABLE_ICU2, ah)
|
||||
INTR(15, IO_ICU2, ENABLE_ICU2, ah)
|
||||
FAST_INTR(0, ENABLE_ICU1)
|
||||
FAST_INTR(1, ENABLE_ICU1)
|
||||
FAST_INTR(2, ENABLE_ICU1)
|
||||
FAST_INTR(3, ENABLE_ICU1)
|
||||
FAST_INTR(4, ENABLE_ICU1)
|
||||
FAST_INTR(5, ENABLE_ICU1)
|
||||
FAST_INTR(6, ENABLE_ICU1)
|
||||
FAST_INTR(7, ENABLE_ICU1)
|
||||
FAST_INTR(8, ENABLE_ICU1_AND_2)
|
||||
FAST_INTR(9, ENABLE_ICU1_AND_2)
|
||||
FAST_INTR(10, ENABLE_ICU1_AND_2)
|
||||
FAST_INTR(11, ENABLE_ICU1_AND_2)
|
||||
FAST_INTR(12, ENABLE_ICU1_AND_2)
|
||||
FAST_INTR(13, ENABLE_ICU1_AND_2)
|
||||
FAST_INTR(14, ENABLE_ICU1_AND_2)
|
||||
FAST_INTR(15, ENABLE_ICU1_AND_2)
|
||||
INTR(0, IO_ICU1, ENABLE_ICU1, al)
|
||||
INTR(1, IO_ICU1, ENABLE_ICU1, al)
|
||||
INTR(2, IO_ICU1, ENABLE_ICU1, al)
|
||||
INTR(3, IO_ICU1, ENABLE_ICU1, al)
|
||||
INTR(4, IO_ICU1, ENABLE_ICU1, al)
|
||||
INTR(5, IO_ICU1, ENABLE_ICU1, al)
|
||||
INTR(6, IO_ICU1, ENABLE_ICU1, al)
|
||||
INTR(7, IO_ICU1, ENABLE_ICU1, al)
|
||||
INTR(8, IO_ICU2, ENABLE_ICU1_AND_2, ah)
|
||||
INTR(9, IO_ICU2, ENABLE_ICU1_AND_2, ah)
|
||||
INTR(10, IO_ICU2, ENABLE_ICU1_AND_2, ah)
|
||||
INTR(11, IO_ICU2, ENABLE_ICU1_AND_2, ah)
|
||||
INTR(12, IO_ICU2, ENABLE_ICU1_AND_2, ah)
|
||||
INTR(13, IO_ICU2, ENABLE_ICU1_AND_2, ah)
|
||||
INTR(14, IO_ICU2, ENABLE_ICU1_AND_2, ah)
|
||||
INTR(15, IO_ICU2, ENABLE_ICU1_AND_2, ah)
|
||||
MCOUNT_LABEL(eintr)
|
||||
|
||||
.data
|
||||
|
|
|
|||
Loading…
Reference in a new issue