From c55baa23d828309038f8e14d0eef029c17216bac Mon Sep 17 00:00:00 2001 From: Adrian Chadd Date: Sun, 13 Mar 2011 08:36:57 +0000 Subject: [PATCH] Add the missing AR724x DDR flush routines for if_arge0. Submitted by: Luiz Otavio O Souza --- sys/mips/atheros/ar724x_chip.c | 2 ++ sys/mips/atheros/ar724xreg.h | 3 +++ 2 files changed, 5 insertions(+) diff --git a/sys/mips/atheros/ar724x_chip.c b/sys/mips/atheros/ar724x_chip.c index 450dd19e942f..63a8ffb13f37 100644 --- a/sys/mips/atheros/ar724x_chip.c +++ b/sys/mips/atheros/ar724x_chip.c @@ -136,11 +136,13 @@ ar724x_chip_set_pll_ge1(int speed) static void ar724x_chip_ddr_flush_ge0(void) { + ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0); } static void ar724x_chip_ddr_flush_ge1(void) { + ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1); } static uint32_t diff --git a/sys/mips/atheros/ar724xreg.h b/sys/mips/atheros/ar724xreg.h index ec7ef1552c0d..ad3fa789476a 100644 --- a/sys/mips/atheros/ar724xreg.h +++ b/sys/mips/atheros/ar724xreg.h @@ -47,6 +47,9 @@ #define AR724X_BASE_FREQ 5000000 +#define AR724X_DDR_REG_FLUSH_GE0 (AR71XX_DDR_CONFIG + 0x7c) +#define AR724X_DDR_REG_FLUSH_GE1 (AR71XX_DDR_CONFIG + 0x80) + #define AR724X_RESET_REG_RESET_MODULE AR71XX_RST_BLOCK_BASE + 0x1c #define AR724X_RESET_MODULE_USB_OHCI_DLL (1 << 3)