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Cleanup old stop_cpus/restart_cpus() cruft.

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new code for handling mixed-mode 8259/APIC programming without 'ExtInt'
new code to control other CPUs: stop_cpus()/restart_cpus()/_Xstopcpu
This commit is contained in:
Steve Passe 1997-07-13 01:18:51 +00:00
parent c5f838abdb
commit c064ef9175
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=27352
10 changed files with 384 additions and 198 deletions
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84
sys/amd64/amd64/apic_vector.S
View file

@ -1,6 +1,6 @@
/*
* from: vector.s, 386BSD 0.1 unknown origin
* $Id: apic_vector.s,v 1.3 1997/07/06 23:29:00 smp Exp smp $
* $Id: apic_vector.s,v 1.9 1997/07/13 00:18:33 smp Exp smp $
*/
@ -168,6 +168,27 @@ __CONCAT(Xresume,irq_num): ; \
iret
/*
* Handle "spurious INTerrupts".
* Notes:
* This is different than the "spurious INTerrupt" generated by an
* 8259 PIC for missing INTs. See the APIC documentation for details.
* This routine should NOT do an 'EOI' cycle.
*/
.text
SUPERALIGN_TEXT
.globl _Xspuriousint
_Xspuriousint:
#ifdef COUNT_SPURIOUS_INTS
ss
incl _sihits
#endif
/* No EOI cycle used here */
iret
/*
* Handle TLB shootdowns.
*/
@ -195,38 +216,9 @@ _Xinvltlb:
iret
/*
* Handle "spurious INTerrupts".
* Notes:
* This is different than the "spurious INTerrupt" generated by an
* 8259 PIC for missing INTs. See the APIC documentation for details.
* This routine should NOT do an 'EOI' cycle.
*/
.text
SUPERALIGN_TEXT
.globl _Xspuriousint
_Xspuriousint:
pushl %eax
pushl %ds /* save current data segment */
#ifdef TEST_CPUSTOP
movl $KDSEL, %eax
movl %ax, %ds /* use KERNEL data segment */
#if 1
ASMPOSTCODE_HI(0xc0)
#endif
#ifdef COUNT_SPURIOUS_INTS
incl _sihits
#endif
/* No EOI cycle used here */
popl %ds /* restore previous data segment */
popl %eax
iret
#ifdef TEST_CPUSTOP
#include "i386/isa/intr_machdep.h"
/*
* Executed by a CPU when it receives an Xcpustop IPI from another CPU,
@ -246,15 +238,13 @@ _Xcpustop:
movl $KDSEL, %eax
movl %ax, %ds /* use KERNEL data segment */
#if 1
/** XXX still trying to make this !^#$#% thing work... */
movl _cpuid, %eax
incl _cshits(,%eax,4)
#else /** !^#$#% */
ASMPOSTCODE_HI(0x10)
movl _cpuid, %eax /* id */
#ifdef COUNT_CSHITS
incl _cshits(,%eax,4)
#endif /* COUNT_CSHITS */
ASMPOSTCODE_HI(0x10)
lock
btsl %eax, _stopped_cpus /* stopped_cpus |= (1<<id) */
@ -270,7 +260,6 @@ _Xcpustop:
btrl %eax, _started_cpus /* started_cpus &= ~(1<<id) */
ASMPOSTCODE_HI(0x40)
#endif /** !^#$#% */
movl $lapic_eoi, %eax
movl $0, (%eax) /* End Of Interrupt to APIC */
@ -366,6 +355,11 @@ _ivectors:
iactive:
.long 0
#ifdef COUNT_SPURIOUS_INTS
.globl _sihits
_sihits:
.long 0
#endif /* COUNT_SPURIOUS_INTS */
#ifdef COUNT_XINVLTLB_HITS
.globl _xhits
@ -376,13 +370,8 @@ _xhits:
.long 0
#endif /* COUNT_XINVLTLB_HITS */
#ifdef COUNT_SPURIOUS_INTS
.globl _sihits
_sihits:
.long 0
#endif /* COUNT_SPURIOUS_INTS */
#ifdef TEST_CPUSTOP
.globl _stopped_cpus
_stopped_cpus:
.long 0
@ -391,12 +380,15 @@ _stopped_cpus:
_started_cpus:
.long 0
#ifdef COUNT_CSHITS
.globl _cshits
_cshits:
.long 0
.long 0
.long 0
.long 0
#endif /* COUNT_CSHITS */
#endif /* TEST_CPUSTOP */

28
sys/amd64/amd64/tsc.c
View file

@ -34,7 +34,7 @@
* SUCH DAMAGE.
*
* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
* $Id: clock.c,v 1.3 1997/06/25 20:37:29 smp Exp smp $
* $Id: clock.c,v 1.88 1997/06/25 20:59:58 fsmp Exp $
*/
/*
@ -66,6 +66,7 @@
#include <machine/ipl.h>
#ifdef APIC_IO
#include <machine/smp.h>
#include <machine/smptests.h> /** TEST_ALTTIMER */
#endif /* APIC_IO */
#include <i386/isa/icu.h>
@ -871,9 +872,11 @@ cpu_initclocks()
/* Finish initializing 8253 timer 0. */
#ifdef APIC_IO
#if 0
#ifndef IO_ICU1
#define IO_ICU1 0x20
#define IO_ICU1 0x20
#endif /* IO_ICU1 */
#endif /** 0 */
/* 8254 is traditionally on ISA IRQ0 */
if ((x = isa_apic_pin(0)) < 0) {
@ -882,14 +885,27 @@ cpu_initclocks()
printf("APIC missing 8254 connection\n");
/* allow 8254 timer to INTerrupt 8259 */
x = inb(IO_ICU1 + 1); /* current mask in 8259 */
x &= ~1; /* clear 8254 timer mask */
outb(IO_ICU1 + 1, x); /* write new mask */
#ifdef TEST_ALTTIMER
/*
* re-initialize master 8259:
* reset; prog 4 bytes, single ICU, edge triggered
*/
outb(IO_ICU1, 0x13);
outb(IO_ICU1 + 1, NRSVIDT); /* start vector */
outb(IO_ICU1 + 1, 0x00); /* ignore slave */
outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
#else
x = inb(IO_ICU1 + 1); /* current mask in 8259 */
x &= ~1; /* clear 8254 timer mask */
outb(IO_ICU1 + 1, x); /* write new mask */
#endif /* TEST_ALTTIMER */
/* program IO APIC for type 3 INT on INT0 */
if (ext_int_setup(0, 0) < 0)
panic("8254 redirect impossible!");
x = 0; /* 8259 is on 0 */
x = 0; /* 8259 is on 0 */
}
vec[x] = (u_int)vec8254;

28
sys/amd64/isa/clock.c
View file

@ -34,7 +34,7 @@
* SUCH DAMAGE.
*
* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
* $Id: clock.c,v 1.3 1997/06/25 20:37:29 smp Exp smp $
* $Id: clock.c,v 1.88 1997/06/25 20:59:58 fsmp Exp $
*/
/*
@ -66,6 +66,7 @@
#include <machine/ipl.h>
#ifdef APIC_IO
#include <machine/smp.h>
#include <machine/smptests.h> /** TEST_ALTTIMER */
#endif /* APIC_IO */
#include <i386/isa/icu.h>
@ -871,9 +872,11 @@ cpu_initclocks()
/* Finish initializing 8253 timer 0. */
#ifdef APIC_IO
#if 0
#ifndef IO_ICU1
#define IO_ICU1 0x20
#define IO_ICU1 0x20
#endif /* IO_ICU1 */
#endif /** 0 */
/* 8254 is traditionally on ISA IRQ0 */
if ((x = isa_apic_pin(0)) < 0) {
@ -882,14 +885,27 @@ cpu_initclocks()
printf("APIC missing 8254 connection\n");
/* allow 8254 timer to INTerrupt 8259 */
x = inb(IO_ICU1 + 1); /* current mask in 8259 */
x &= ~1; /* clear 8254 timer mask */
outb(IO_ICU1 + 1, x); /* write new mask */
#ifdef TEST_ALTTIMER
/*
* re-initialize master 8259:
* reset; prog 4 bytes, single ICU, edge triggered
*/
outb(IO_ICU1, 0x13);
outb(IO_ICU1 + 1, NRSVIDT); /* start vector */
outb(IO_ICU1 + 1, 0x00); /* ignore slave */
outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
#else
x = inb(IO_ICU1 + 1); /* current mask in 8259 */
x &= ~1; /* clear 8254 timer mask */
outb(IO_ICU1 + 1, x); /* write new mask */
#endif /* TEST_ALTTIMER */
/* program IO APIC for type 3 INT on INT0 */
if (ext_int_setup(0, 0) < 0)
panic("8254 redirect impossible!");
x = 0; /* 8259 is on 0 */
x = 0; /* 8259 is on 0 */
}
vec[x] = (u_int)vec8254;

95
sys/amd64/isa/intr_machdep.h
View file

@ -31,7 +31,7 @@
* SUCH DAMAGE.
*
* from: @(#)isa_device.h 7.1 (Berkeley) 5/9/91
* $Id: intr_machdep.h,v 1.2 1997/06/27 23:48:05 fsmp Exp $
* $Id: intr_machdep.h,v 1.6 1997/07/13 00:18:33 smp Exp smp $
*/
#ifndef _I386_ISA_INTR_MACHDEP_H_
@ -43,6 +43,74 @@
#ifdef KERNEL
/*
* XXX FIXME: rethink location for all IPI vectors.
*/
/*
APIC TPR priority vector levels:
0xff (255) +------------+
| | 15 (highest)
0xf0 (240) +------------+
| | 14
0xe0 (224) +------------+
| | 13
0xd0 (208) +------------+
| | 12
0xc0 (192) +------------+
| | 11
0xb0 (176) +------------+
| | 10
0xa0 (160) +------------+
| | 9
0x90 (144) +------------+
| | 8
0x80 (128) +------------+
| | 7
0x70 (112) +------------+
| | 6 (IPIs: Xspuriousint)
0x60 (96) +------------+
| | 5 (IPIs: Xcpustop)
0x50 (80) +------------+
| | 4 (IPIs: Xinvltlb)
0x40 (64) +------------+
| | 3 (extended APIC hardware INTs: PCI)
0x30 (48) +------------+
| | 2 (start of hardware INTs: ISA)
0x20 (32) +------------+
| | 1 (lowest)
0x10 (16) +------------+
| | 0
0x00 (0) +------------+
*/
#define TPR_BLOCK_HWI 0x3f /* block hardware INTs via APIC TPR */
#define TPR_BLOCK_XINVLTLB 0x4f /* block ? via APIC TPR */
#define TPR_BLOCK_XCPUSTOP 0x5f /* block ? via APIC TPR */
/*
* Note: this vector MUST be xxxx1111, 32 + 79 = 111 = 0x6f:
* also remember i386/include/segments.h: #define NIDT 129
*/
#define XSPURIOUSINT_OFFSET (ICU_OFFSET + 79)
/* TLB shootdowns */
#define XINVLTLB_OFFSET (ICU_OFFSET + 32)
#if defined(TEST_CPUSTOP)
/* IPI to signal CPUs to stop and wait for another CPU to restart them */
#define XCPUSTOP_OFFSET (ICU_OFFSET + 48)
#endif /** TEST_CPUSTOP */
#if defined(TEST_TEST1)
/* put a 'fake' HWI in top of APIC prio 0x3x, 32 + 31 = 63 = 0x3f */
#define XTEST1_OFFSET (ICU_OFFSET + 31)
#endif /** TEST_TEST1 */
#ifndef LOCORE
/*
* Type of the first (asm) part of an interrupt handler.
*/
@ -83,30 +151,25 @@ inthand_t
IDTVEC(intr16), IDTVEC(intr17), IDTVEC(intr18), IDTVEC(intr19),
IDTVEC(intr20), IDTVEC(intr21), IDTVEC(intr22), IDTVEC(intr23);
#define XINVLTLB_OFFSET (ICU_OFFSET + 32)
inthand_t
Xinvltlb;
Xinvltlb,
Xspuriousint;
#if defined(TEST_CPUSTOP)
#define XCPUSTOP_OFFSET (ICU_OFFSET + 64)
inthand_t
Xcpustop;
/*
* XXX FIXME: rethink location for this (and all IPI vectors)
* Note: this vector MUST be xxxx1111, 32 + 79 = 111 = 0x6f:
* also remember i386/include/segments.h: #define NIDT 129
*/
#define XSPURIOUSINT_OFFSET (ICU_OFFSET + 79)
Xcpustop; /* stop & wait for another CPU to restart it */
#endif /** TEST_CPUSTOP */
#if defined(TEST_CPUSTOP)
inthand_t
Xspuriousint;
#endif /* TEST_CPUSTOP */
Xtest1; /* 'fake' HWI in top of APIC prio 0x3x, 32+31 = 0x3f */
#endif /** TEST_TEST1 */
struct isa_device;
void isa_defaultirq __P((void));
int isa_irq_pending __P((struct isa_device *dvp));
/* this function ONLY exists in an SMP/APIC_IO kernel: */
int icu_irq_pending __P((struct isa_device *dvp));
int icu_irq_pending __P((struct isa_device *dvp)); /* APIC_IO kernel */
int isa_nmi __P((int cd));
void update_intrname __P((int intr, int device_id));
int icu_setup __P((int intr, inthand2_t *func, void *arg,
@ -115,6 +178,8 @@ int icu_unset __P((int intr, inthand2_t *handler));
int update_intr_masks __P((void));
void register_imask __P((struct isa_device *dvp, u_int mask));
#endif /* LOCORE */
#endif /* KERNEL */
#endif /* !_I386_ISA_INTR_MACHDEP_H_ */

84
sys/i386/i386/apic_vector.s
View file

@ -1,6 +1,6 @@
/*
* from: vector.s, 386BSD 0.1 unknown origin
* $Id: apic_vector.s,v 1.3 1997/07/06 23:29:00 smp Exp smp $
* $Id: apic_vector.s,v 1.9 1997/07/13 00:18:33 smp Exp smp $
*/
@ -168,6 +168,27 @@ __CONCAT(Xresume,irq_num): ; \
iret
/*
* Handle "spurious INTerrupts".
* Notes:
* This is different than the "spurious INTerrupt" generated by an
* 8259 PIC for missing INTs. See the APIC documentation for details.
* This routine should NOT do an 'EOI' cycle.
*/
.text
SUPERALIGN_TEXT
.globl _Xspuriousint
_Xspuriousint:
#ifdef COUNT_SPURIOUS_INTS
ss
incl _sihits
#endif
/* No EOI cycle used here */
iret
/*
* Handle TLB shootdowns.
*/
@ -195,38 +216,9 @@ _Xinvltlb:
iret
/*
* Handle "spurious INTerrupts".
* Notes:
* This is different than the "spurious INTerrupt" generated by an
* 8259 PIC for missing INTs. See the APIC documentation for details.
* This routine should NOT do an 'EOI' cycle.
*/
.text
SUPERALIGN_TEXT
.globl _Xspuriousint
_Xspuriousint:
pushl %eax
pushl %ds /* save current data segment */
#ifdef TEST_CPUSTOP
movl $KDSEL, %eax
movl %ax, %ds /* use KERNEL data segment */
#if 1
ASMPOSTCODE_HI(0xc0)
#endif
#ifdef COUNT_SPURIOUS_INTS
incl _sihits
#endif
/* No EOI cycle used here */
popl %ds /* restore previous data segment */
popl %eax
iret
#ifdef TEST_CPUSTOP
#include "i386/isa/intr_machdep.h"
/*
* Executed by a CPU when it receives an Xcpustop IPI from another CPU,
@ -246,15 +238,13 @@ _Xcpustop:
movl $KDSEL, %eax
movl %ax, %ds /* use KERNEL data segment */
#if 1
/** XXX still trying to make this !^#$#% thing work... */
movl _cpuid, %eax
incl _cshits(,%eax,4)
#else /** !^#$#% */
ASMPOSTCODE_HI(0x10)
movl _cpuid, %eax /* id */
#ifdef COUNT_CSHITS
incl _cshits(,%eax,4)
#endif /* COUNT_CSHITS */
ASMPOSTCODE_HI(0x10)
lock
btsl %eax, _stopped_cpus /* stopped_cpus |= (1<<id) */
@ -270,7 +260,6 @@ _Xcpustop:
btrl %eax, _started_cpus /* started_cpus &= ~(1<<id) */
ASMPOSTCODE_HI(0x40)
#endif /** !^#$#% */
movl $lapic_eoi, %eax
movl $0, (%eax) /* End Of Interrupt to APIC */
@ -366,6 +355,11 @@ _ivectors:
iactive:
.long 0
#ifdef COUNT_SPURIOUS_INTS
.globl _sihits
_sihits:
.long 0
#endif /* COUNT_SPURIOUS_INTS */
#ifdef COUNT_XINVLTLB_HITS
.globl _xhits
@ -376,13 +370,8 @@ _xhits:
.long 0
#endif /* COUNT_XINVLTLB_HITS */
#ifdef COUNT_SPURIOUS_INTS
.globl _sihits
_sihits:
.long 0
#endif /* COUNT_SPURIOUS_INTS */
#ifdef TEST_CPUSTOP
.globl _stopped_cpus
_stopped_cpus:
.long 0
@ -391,12 +380,15 @@ _stopped_cpus:
_started_cpus:
.long 0
#ifdef COUNT_CSHITS
.globl _cshits
_cshits:
.long 0
.long 0
.long 0
.long 0
#endif /* COUNT_CSHITS */
#endif /* TEST_CPUSTOP */

28
sys/i386/i386/tsc.c
View file

@ -34,7 +34,7 @@
* SUCH DAMAGE.
*
* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
* $Id: clock.c,v 1.3 1997/06/25 20:37:29 smp Exp smp $
* $Id: clock.c,v 1.88 1997/06/25 20:59:58 fsmp Exp $
*/
/*
@ -66,6 +66,7 @@
#include <machine/ipl.h>
#ifdef APIC_IO
#include <machine/smp.h>
#include <machine/smptests.h> /** TEST_ALTTIMER */
#endif /* APIC_IO */
#include <i386/isa/icu.h>
@ -871,9 +872,11 @@ cpu_initclocks()
/* Finish initializing 8253 timer 0. */
#ifdef APIC_IO
#if 0
#ifndef IO_ICU1
#define IO_ICU1 0x20
#define IO_ICU1 0x20
#endif /* IO_ICU1 */
#endif /** 0 */
/* 8254 is traditionally on ISA IRQ0 */
if ((x = isa_apic_pin(0)) < 0) {
@ -882,14 +885,27 @@ cpu_initclocks()
printf("APIC missing 8254 connection\n");
/* allow 8254 timer to INTerrupt 8259 */
x = inb(IO_ICU1 + 1); /* current mask in 8259 */
x &= ~1; /* clear 8254 timer mask */
outb(IO_ICU1 + 1, x); /* write new mask */
#ifdef TEST_ALTTIMER
/*
* re-initialize master 8259:
* reset; prog 4 bytes, single ICU, edge triggered
*/
outb(IO_ICU1, 0x13);
outb(IO_ICU1 + 1, NRSVIDT); /* start vector */
outb(IO_ICU1 + 1, 0x00); /* ignore slave */
outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
#else
x = inb(IO_ICU1 + 1); /* current mask in 8259 */
x &= ~1; /* clear 8254 timer mask */
outb(IO_ICU1 + 1, x); /* write new mask */
#endif /* TEST_ALTTIMER */
/* program IO APIC for type 3 INT on INT0 */
if (ext_int_setup(0, 0) < 0)
panic("8254 redirect impossible!");
x = 0; /* 8259 is on 0 */
x = 0; /* 8259 is on 0 */
}
vec[x] = (u_int)vec8254;

84
sys/i386/isa/apic_vector.s
View file

@ -1,6 +1,6 @@
/*
* from: vector.s, 386BSD 0.1 unknown origin
* $Id: apic_vector.s,v 1.3 1997/07/06 23:29:00 smp Exp smp $
* $Id: apic_vector.s,v 1.9 1997/07/13 00:18:33 smp Exp smp $
*/
@ -168,6 +168,27 @@ __CONCAT(Xresume,irq_num): ; \
iret
/*
* Handle "spurious INTerrupts".
* Notes:
* This is different than the "spurious INTerrupt" generated by an
* 8259 PIC for missing INTs. See the APIC documentation for details.
* This routine should NOT do an 'EOI' cycle.
*/
.text
SUPERALIGN_TEXT
.globl _Xspuriousint
_Xspuriousint:
#ifdef COUNT_SPURIOUS_INTS
ss
incl _sihits
#endif
/* No EOI cycle used here */
iret
/*
* Handle TLB shootdowns.
*/
@ -195,38 +216,9 @@ _Xinvltlb:
iret
/*
* Handle "spurious INTerrupts".
* Notes:
* This is different than the "spurious INTerrupt" generated by an
* 8259 PIC for missing INTs. See the APIC documentation for details.
* This routine should NOT do an 'EOI' cycle.
*/
.text
SUPERALIGN_TEXT
.globl _Xspuriousint
_Xspuriousint:
pushl %eax
pushl %ds /* save current data segment */
#ifdef TEST_CPUSTOP
movl $KDSEL, %eax
movl %ax, %ds /* use KERNEL data segment */
#if 1
ASMPOSTCODE_HI(0xc0)
#endif
#ifdef COUNT_SPURIOUS_INTS
incl _sihits
#endif
/* No EOI cycle used here */
popl %ds /* restore previous data segment */
popl %eax
iret
#ifdef TEST_CPUSTOP
#include "i386/isa/intr_machdep.h"
/*
* Executed by a CPU when it receives an Xcpustop IPI from another CPU,
@ -246,15 +238,13 @@ _Xcpustop:
movl $KDSEL, %eax
movl %ax, %ds /* use KERNEL data segment */
#if 1
/** XXX still trying to make this !^#$#% thing work... */
movl _cpuid, %eax
incl _cshits(,%eax,4)
#else /** !^#$#% */
ASMPOSTCODE_HI(0x10)
movl _cpuid, %eax /* id */
#ifdef COUNT_CSHITS
incl _cshits(,%eax,4)
#endif /* COUNT_CSHITS */
ASMPOSTCODE_HI(0x10)
lock
btsl %eax, _stopped_cpus /* stopped_cpus |= (1<<id) */
@ -270,7 +260,6 @@ _Xcpustop:
btrl %eax, _started_cpus /* started_cpus &= ~(1<<id) */
ASMPOSTCODE_HI(0x40)
#endif /** !^#$#% */
movl $lapic_eoi, %eax
movl $0, (%eax) /* End Of Interrupt to APIC */
@ -366,6 +355,11 @@ _ivectors:
iactive:
.long 0
#ifdef COUNT_SPURIOUS_INTS
.globl _sihits
_sihits:
.long 0
#endif /* COUNT_SPURIOUS_INTS */
#ifdef COUNT_XINVLTLB_HITS
.globl _xhits
@ -376,13 +370,8 @@ _xhits:
.long 0
#endif /* COUNT_XINVLTLB_HITS */
#ifdef COUNT_SPURIOUS_INTS
.globl _sihits
_sihits:
.long 0
#endif /* COUNT_SPURIOUS_INTS */
#ifdef TEST_CPUSTOP
.globl _stopped_cpus
_stopped_cpus:
.long 0
@ -391,12 +380,15 @@ _stopped_cpus:
_started_cpus:
.long 0
#ifdef COUNT_CSHITS
.globl _cshits
_cshits:
.long 0
.long 0
.long 0
.long 0
#endif /* COUNT_CSHITS */
#endif /* TEST_CPUSTOP */

28
sys/i386/isa/clock.c
View file

@ -34,7 +34,7 @@
* SUCH DAMAGE.
*
* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
* $Id: clock.c,v 1.3 1997/06/25 20:37:29 smp Exp smp $
* $Id: clock.c,v 1.88 1997/06/25 20:59:58 fsmp Exp $
*/
/*
@ -66,6 +66,7 @@
#include <machine/ipl.h>
#ifdef APIC_IO
#include <machine/smp.h>
#include <machine/smptests.h> /** TEST_ALTTIMER */
#endif /* APIC_IO */
#include <i386/isa/icu.h>
@ -871,9 +872,11 @@ cpu_initclocks()
/* Finish initializing 8253 timer 0. */
#ifdef APIC_IO
#if 0
#ifndef IO_ICU1
#define IO_ICU1 0x20
#define IO_ICU1 0x20
#endif /* IO_ICU1 */
#endif /** 0 */
/* 8254 is traditionally on ISA IRQ0 */
if ((x = isa_apic_pin(0)) < 0) {
@ -882,14 +885,27 @@ cpu_initclocks()
printf("APIC missing 8254 connection\n");
/* allow 8254 timer to INTerrupt 8259 */
x = inb(IO_ICU1 + 1); /* current mask in 8259 */
x &= ~1; /* clear 8254 timer mask */
outb(IO_ICU1 + 1, x); /* write new mask */
#ifdef TEST_ALTTIMER
/*
* re-initialize master 8259:
* reset; prog 4 bytes, single ICU, edge triggered
*/
outb(IO_ICU1, 0x13);
outb(IO_ICU1 + 1, NRSVIDT); /* start vector */
outb(IO_ICU1 + 1, 0x00); /* ignore slave */
outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
#else
x = inb(IO_ICU1 + 1); /* current mask in 8259 */
x &= ~1; /* clear 8254 timer mask */
outb(IO_ICU1 + 1, x); /* write new mask */
#endif /* TEST_ALTTIMER */
/* program IO APIC for type 3 INT on INT0 */
if (ext_int_setup(0, 0) < 0)
panic("8254 redirect impossible!");
x = 0; /* 8259 is on 0 */
x = 0; /* 8259 is on 0 */
}
vec[x] = (u_int)vec8254;

95
sys/i386/isa/intr_machdep.h
View file

@ -31,7 +31,7 @@
* SUCH DAMAGE.
*
* from: @(#)isa_device.h 7.1 (Berkeley) 5/9/91
* $Id: intr_machdep.h,v 1.2 1997/06/27 23:48:05 fsmp Exp $
* $Id: intr_machdep.h,v 1.6 1997/07/13 00:18:33 smp Exp smp $
*/
#ifndef _I386_ISA_INTR_MACHDEP_H_
@ -43,6 +43,74 @@
#ifdef KERNEL
/*
* XXX FIXME: rethink location for all IPI vectors.
*/
/*
APIC TPR priority vector levels:
0xff (255) +------------+
| | 15 (highest)
0xf0 (240) +------------+
| | 14
0xe0 (224) +------------+
| | 13
0xd0 (208) +------------+
| | 12
0xc0 (192) +------------+
| | 11
0xb0 (176) +------------+
| | 10
0xa0 (160) +------------+
| | 9
0x90 (144) +------------+
| | 8
0x80 (128) +------------+
| | 7
0x70 (112) +------------+
| | 6 (IPIs: Xspuriousint)
0x60 (96) +------------+
| | 5 (IPIs: Xcpustop)
0x50 (80) +------------+
| | 4 (IPIs: Xinvltlb)
0x40 (64) +------------+
| | 3 (extended APIC hardware INTs: PCI)
0x30 (48) +------------+
| | 2 (start of hardware INTs: ISA)
0x20 (32) +------------+
| | 1 (lowest)
0x10 (16) +------------+
| | 0
0x00 (0) +------------+
*/
#define TPR_BLOCK_HWI 0x3f /* block hardware INTs via APIC TPR */
#define TPR_BLOCK_XINVLTLB 0x4f /* block ? via APIC TPR */
#define TPR_BLOCK_XCPUSTOP 0x5f /* block ? via APIC TPR */
/*
* Note: this vector MUST be xxxx1111, 32 + 79 = 111 = 0x6f:
* also remember i386/include/segments.h: #define NIDT 129
*/
#define XSPURIOUSINT_OFFSET (ICU_OFFSET + 79)
/* TLB shootdowns */
#define XINVLTLB_OFFSET (ICU_OFFSET + 32)
#if defined(TEST_CPUSTOP)
/* IPI to signal CPUs to stop and wait for another CPU to restart them */
#define XCPUSTOP_OFFSET (ICU_OFFSET + 48)
#endif /** TEST_CPUSTOP */
#if defined(TEST_TEST1)
/* put a 'fake' HWI in top of APIC prio 0x3x, 32 + 31 = 63 = 0x3f */
#define XTEST1_OFFSET (ICU_OFFSET + 31)
#endif /** TEST_TEST1 */
#ifndef LOCORE
/*
* Type of the first (asm) part of an interrupt handler.
*/
@ -83,30 +151,25 @@ inthand_t
IDTVEC(intr16), IDTVEC(intr17), IDTVEC(intr18), IDTVEC(intr19),
IDTVEC(intr20), IDTVEC(intr21), IDTVEC(intr22), IDTVEC(intr23);
#define XINVLTLB_OFFSET (ICU_OFFSET + 32)
inthand_t
Xinvltlb;
Xinvltlb,
Xspuriousint;
#if defined(TEST_CPUSTOP)
#define XCPUSTOP_OFFSET (ICU_OFFSET + 64)
inthand_t
Xcpustop;
/*
* XXX FIXME: rethink location for this (and all IPI vectors)
* Note: this vector MUST be xxxx1111, 32 + 79 = 111 = 0x6f:
* also remember i386/include/segments.h: #define NIDT 129
*/
#define XSPURIOUSINT_OFFSET (ICU_OFFSET + 79)
Xcpustop; /* stop & wait for another CPU to restart it */
#endif /** TEST_CPUSTOP */
#if defined(TEST_CPUSTOP)
inthand_t
Xspuriousint;
#endif /* TEST_CPUSTOP */
Xtest1; /* 'fake' HWI in top of APIC prio 0x3x, 32+31 = 0x3f */
#endif /** TEST_TEST1 */
struct isa_device;
void isa_defaultirq __P((void));
int isa_irq_pending __P((struct isa_device *dvp));
/* this function ONLY exists in an SMP/APIC_IO kernel: */
int icu_irq_pending __P((struct isa_device *dvp));
int icu_irq_pending __P((struct isa_device *dvp)); /* APIC_IO kernel */
int isa_nmi __P((int cd));
void update_intrname __P((int intr, int device_id));
int icu_setup __P((int intr, inthand2_t *func, void *arg,
@ -115,6 +178,8 @@ int icu_unset __P((int intr, inthand2_t *handler));
int update_intr_masks __P((void));
void register_imask __P((struct isa_device *dvp, u_int mask));
#endif /* LOCORE */
#endif /* KERNEL */
#endif /* !_I386_ISA_INTR_MACHDEP_H_ */

28
sys/isa/atrtc.c
View file

@ -34,7 +34,7 @@
* SUCH DAMAGE.
*
* from: @(#)clock.c 7.2 (Berkeley) 5/12/91
* $Id: clock.c,v 1.3 1997/06/25 20:37:29 smp Exp smp $
* $Id: clock.c,v 1.88 1997/06/25 20:59:58 fsmp Exp $
*/
/*
@ -66,6 +66,7 @@
#include <machine/ipl.h>
#ifdef APIC_IO
#include <machine/smp.h>
#include <machine/smptests.h> /** TEST_ALTTIMER */
#endif /* APIC_IO */
#include <i386/isa/icu.h>
@ -871,9 +872,11 @@ cpu_initclocks()
/* Finish initializing 8253 timer 0. */
#ifdef APIC_IO
#if 0
#ifndef IO_ICU1
#define IO_ICU1 0x20
#define IO_ICU1 0x20
#endif /* IO_ICU1 */
#endif /** 0 */
/* 8254 is traditionally on ISA IRQ0 */
if ((x = isa_apic_pin(0)) < 0) {
@ -882,14 +885,27 @@ cpu_initclocks()
printf("APIC missing 8254 connection\n");
/* allow 8254 timer to INTerrupt 8259 */
x = inb(IO_ICU1 + 1); /* current mask in 8259 */
x &= ~1; /* clear 8254 timer mask */
outb(IO_ICU1 + 1, x); /* write new mask */
#ifdef TEST_ALTTIMER
/*
* re-initialize master 8259:
* reset; prog 4 bytes, single ICU, edge triggered
*/
outb(IO_ICU1, 0x13);
outb(IO_ICU1 + 1, NRSVIDT); /* start vector */
outb(IO_ICU1 + 1, 0x00); /* ignore slave */
outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
#else
x = inb(IO_ICU1 + 1); /* current mask in 8259 */
x &= ~1; /* clear 8254 timer mask */
outb(IO_ICU1 + 1, x); /* write new mask */
#endif /* TEST_ALTTIMER */
/* program IO APIC for type 3 INT on INT0 */
if (ext_int_setup(0, 0) < 0)
panic("8254 redirect impossible!");
x = 0; /* 8259 is on 0 */
x = 0; /* 8259 is on 0 */
}
vec[x] = (u_int)vec8254;