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Add support for external PCIe (PEM) on Cavium's ThunderX
Reviewed by: jhb Obtained from: Semihalf Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D3257
This commit is contained in:
Zbigniew Bodek
parent
444e7e3d82
commit
bfc3978594
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=286477
637
sys/arm64/cavium/thunder_pcie_pem.c
Normal file
637
sys/arm64/cavium/thunder_pcie_pem.c
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@ -0,0 +1,637 @@
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/*-
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* Copyright (c) 2015 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Semihalf under
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* the sponsorship of the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* PCIe external MAC root complex driver (PEM) for Cavium Thunder SOC */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/endian.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/smp.h>
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#include <machine/intr.h>
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#include "thunder_pcie_common.h"
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#include "pcib_if.h"
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#define THUNDER_PEM_DEVICE_ID 0xa020
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#define THUNDER_PEM_VENDOR_ID 0x177d
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#define THUNDER_PEM_DESC "ThunderX PEM"
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/* ThunderX specific defines */
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#define THUNDER_PEMn_REG_BASE(unit) (0x87e0c0000000UL | ((unit) << 24))
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#define PCIERC_CFG002 0x08
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#define PCIERC_CFG006 0x18
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#define PCIERC_CFG032 0x80
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#define PCIERC_CFG006_SEC_BUS(reg) (((reg) >> 8) & 0xFF)
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#define PEM_CFG_RD_REG_ALIGN(reg) ((reg) & ~0x3)
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#define PEM_CFG_RD_REG_DATA(val) (((val) >> 32) & 0xFFFFFFFF)
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#define PEM_CFG_RD 0x30
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#define PEM_CFG_LINK_MASK 0x3
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#define PEM_CFG_LINK_RDY 0x3
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#define PEM_CFG_SLIX_TO_REG(slix) ((slix) << 4)
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#define SBNUM_OFFSET 0x8
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#define SBNUM_MASK 0xFF
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#define PEM_ON_REG 0x420
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#define PEM_CTL_STATUS 0x0
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#define PEM_LINK_ENABLE (1 << 4)
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#define PEM_LINK_DLLA (1 << 29)
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#define PEM_LINK_LT (1 << 27)
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#define PEM_BUS_SHIFT (24)
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#define PEM_SLOT_SHIFT (19)
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#define PEM_FUNC_SHIFT (16)
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#define SLIX_S2M_REGX_ACC 0x874001000000UL
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#define SLIX_S2M_REGX_ACC_SIZE 0x1000
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#define SLIX_S2M_REGX_ACC_SPACING 0x001000000000UL
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#define SLI_BASE 0x880000000000UL
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#define SLI_WINDOW_SPACING 0x004000000000UL
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#define SLI_WINDOW_SIZE 0x0000FF000000UL
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#define SLI_PCI_OFFSET 0x001000000000UL
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#define SLI_NODE_SHIFT (44)
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#define SLI_NODE_MASK (3)
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#define SLI_GROUP_SHIFT (40)
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#define SLI_ID_SHIFT (24)
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#define SLI_ID_MASK (7)
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#define SLI_PEMS_PER_GROUP (3)
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#define SLI_GROUPS_PER_NODE (2)
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#define SLI_PEMS_PER_NODE (SLI_PEMS_PER_GROUP * SLI_GROUPS_PER_NODE)
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#define SLI_ACC_REG_CNT (256)
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/*
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* Each PEM device creates its own bus with
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* own address translation, so we can adjust bus addresses
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* as we want. To support 32-bit cards let's assume
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* PCI window assignment looks as following:
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*
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* 0x00000000 - 0x000FFFFF IO
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* 0x00100000 - 0xFFFFFFFF Memory
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*/
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#define PCI_IO_BASE 0x00000000UL
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#define PCI_IO_SIZE 0x00100000UL
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#define PCI_MEMORY_BASE PCI_IO_SIZE
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#define PCI_MEMORY_SIZE 0xFFF00000UL
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struct thunder_pem_softc {
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device_t dev;
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struct resource *reg;
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bus_space_tag_t reg_bst;
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bus_space_handle_t reg_bsh;
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struct pcie_range ranges[MAX_RANGES_TUPLES];
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struct rman mem_rman;
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struct rman io_rman;
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bus_space_handle_t pem_sli_base;
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uint32_t node;
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uint32_t id;
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uint32_t sli;
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uint32_t sli_group;
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uint64_t sli_window_base;
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};
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static struct resource * thunder_pem_alloc_resource(device_t, device_t, int,
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int *, u_long, u_long, u_long, u_int);
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static int thunder_pem_attach(device_t);
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static int thunder_pem_detach(device_t);
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static uint64_t thunder_pem_config_reg_read(struct thunder_pem_softc *, int);
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static int thunder_pem_link_init(struct thunder_pem_softc *);
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static int thunder_pem_maxslots(device_t);
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static int thunder_pem_probe(device_t);
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static uint32_t thunder_pem_read_config(device_t, u_int, u_int, u_int, u_int,
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int);
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static int thunder_pem_read_ivar(device_t, device_t, int, uintptr_t *);
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static void thunder_pem_release_all(device_t);
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static int thunder_pem_release_resource(device_t, device_t, int, int,
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struct resource *);
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static void thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *,
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int, int);
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static void thunder_pem_write_config(device_t, u_int, u_int, u_int, u_int,
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uint32_t, int);
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static int thunder_pem_write_ivar(device_t, device_t, int, uintptr_t);
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/* Global handlers for SLI interface */
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static bus_space_handle_t sli0_s2m_regx_base = 0;
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static bus_space_handle_t sli1_s2m_regx_base = 0;
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static device_method_t thunder_pem_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, thunder_pem_probe),
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DEVMETHOD(device_attach, thunder_pem_attach),
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DEVMETHOD(device_detach, thunder_pem_detach),
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DEVMETHOD(pcib_maxslots, thunder_pem_maxslots),
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DEVMETHOD(pcib_read_config, thunder_pem_read_config),
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DEVMETHOD(pcib_write_config, thunder_pem_write_config),
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DEVMETHOD(bus_read_ivar, thunder_pem_read_ivar),
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DEVMETHOD(bus_write_ivar, thunder_pem_write_ivar),
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DEVMETHOD(bus_alloc_resource, thunder_pem_alloc_resource),
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DEVMETHOD(bus_release_resource, thunder_pem_release_resource),
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DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
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DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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DEVMETHOD(pcib_map_msi, thunder_common_map_msi),
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DEVMETHOD(pcib_alloc_msix, thunder_common_alloc_msix),
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DEVMETHOD(pcib_release_msix, thunder_common_release_msix),
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DEVMETHOD(pcib_alloc_msi, thunder_common_alloc_msi),
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DEVMETHOD(pcib_release_msi, thunder_common_release_msi),
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DEVMETHOD_END
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};
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static driver_t thunder_pem_driver = {
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"pcib",
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thunder_pem_methods,
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sizeof(struct thunder_pem_softc),
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};
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static int
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thunder_pem_maxslots(device_t dev)
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{
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/* max slots per bus acc. to standard */
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return (PCI_SLOTMAX);
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}
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static int
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thunder_pem_read_ivar(device_t dev, device_t child, int index,
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uintptr_t *result)
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{
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struct thunder_pem_softc *sc;
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int secondary_bus = 0;
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sc = device_get_softc(dev);
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if (index == PCIB_IVAR_BUS) {
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secondary_bus = thunder_pem_config_reg_read(sc, PCIERC_CFG006);
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*result = PCIERC_CFG006_SEC_BUS(secondary_bus);
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return (0);
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}
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if (index == PCIB_IVAR_DOMAIN) {
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*result = sc->id;
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return (0);
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}
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return (ENOENT);
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}
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static int
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thunder_pem_write_ivar(device_t dev, device_t child, int index,
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uintptr_t value)
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{
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return (ENOENT);
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}
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static int
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thunder_pem_identify(device_t dev)
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{
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struct thunder_pem_softc *sc;
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u_long start;
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sc = device_get_softc(dev);
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start = rman_get_start(sc->reg);
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/* Calculate PEM designations from its address */
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sc->node = (start >> SLI_NODE_SHIFT) & SLI_NODE_MASK;
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sc->id = ((start >> SLI_ID_SHIFT) & SLI_ID_MASK) +
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(SLI_PEMS_PER_NODE * sc->node);
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sc->sli = sc->id % SLI_PEMS_PER_GROUP;
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sc->sli_group = (sc->id / SLI_PEMS_PER_GROUP) % SLI_GROUPS_PER_NODE;
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sc->sli_window_base = SLI_BASE |
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(((uint64_t)sc->node) << SLI_NODE_SHIFT) |
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((uint64_t)sc->sli_group << SLI_GROUP_SHIFT);
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sc->sli_window_base += SLI_WINDOW_SPACING * sc->sli;
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return (0);
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}
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static void
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thunder_pem_slix_s2m_regx_acc_modify(struct thunder_pem_softc *sc,
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int sli_group, int slix)
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{
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uint64_t regval;
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bus_space_handle_t handle = 0;
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KASSERT(slix >= 0 && slix <= SLI_ACC_REG_CNT, ("Invalid SLI index"));
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if (sli_group == 0)
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handle = sli0_s2m_regx_base;
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else if (sli_group == 1)
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handle = sli1_s2m_regx_base;
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else
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device_printf(sc->dev, "SLI group is not correct\n");
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if (handle) {
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/* Clear lower 32-bits of the SLIx register */
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regval = bus_space_read_8(sc->reg_bst, handle,
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PEM_CFG_SLIX_TO_REG(slix));
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regval &= ~(0xFFFFFFFFUL);
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bus_space_write_8(sc->reg_bst, handle,
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PEM_CFG_SLIX_TO_REG(slix), regval);
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}
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}
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static int
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thunder_pem_link_init(struct thunder_pem_softc *sc)
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{
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uint64_t regval;
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/* check whether PEM is safe to access. */
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regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_ON_REG);
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if ((regval & PEM_CFG_LINK_MASK) != PEM_CFG_LINK_RDY) {
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device_printf(sc->dev, "PEM%d is not ON\n", sc->id);
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return (ENXIO);
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}
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regval = bus_space_read_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS);
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regval |= PEM_LINK_ENABLE;
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bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CTL_STATUS, regval);
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/* Wait 1ms as per Cavium specification */
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DELAY(1000);
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regval = thunder_pem_config_reg_read(sc, PCIERC_CFG032);
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if (((regval & PEM_LINK_DLLA) == 0) || ((regval & PEM_LINK_LT) != 0)) {
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device_printf(sc->dev, "PCIe RC: Port %d Link Timeout\n",
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sc->id);
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return (ENXIO);
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}
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return (0);
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}
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static int
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thunder_pem_init(struct thunder_pem_softc *sc)
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{
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int i, retval = 0;
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retval = thunder_pem_link_init(sc);
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if (retval) {
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device_printf(sc->dev, "%s failed\n", __func__);
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return retval;
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}
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retval = bus_space_map(sc->reg_bst, sc->sli_window_base,
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SLI_WINDOW_SIZE, 0, &sc->pem_sli_base);
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if (retval) {
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device_printf(sc->dev,
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"Unable to map RC%d pem_addr base address", sc->id);
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return (ENOMEM);
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}
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/* To support 32-bit PCIe devices, set S2M_REGx_ACC[BA]=0x0 */
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for (i = 0; i < SLI_ACC_REG_CNT; i++) {
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thunder_pem_slix_s2m_regx_acc_modify(sc, sc->sli_group, i);
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}
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return (retval);
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}
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static uint64_t
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thunder_pem_config_reg_read(struct thunder_pem_softc *sc, int reg)
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{
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uint64_t data;
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/* Write to ADDR register */
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bus_space_write_8(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD,
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PEM_CFG_RD_REG_ALIGN(reg));
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bus_space_barrier(sc->reg_bst, sc->reg_bsh, PEM_CFG_RD, 8,
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BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
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/* Read from DATA register */
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data = PEM_CFG_RD_REG_DATA(bus_space_read_8(sc->reg_bst, sc->reg_bsh,
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PEM_CFG_RD));
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return (data);
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}
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static uint32_t
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thunder_pem_read_config(device_t dev, u_int bus, u_int slot,
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u_int func, u_int reg, int bytes)
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{
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uint64_t offset;
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uint32_t data;
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struct thunder_pem_softc *sc;
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bus_space_tag_t t;
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bus_space_handle_t h;
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if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
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(func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
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return (~0U);
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sc = device_get_softc(dev);
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/* Calculate offset */
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offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) |
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(func << PEM_FUNC_SHIFT) | reg;
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t = sc->reg_bst;
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h = sc->pem_sli_base;
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switch (bytes) {
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case 1:
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data = bus_space_read_1(t, h, offset);
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break;
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case 2:
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data = le16toh(bus_space_read_2(t, h, offset));
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break;
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case 4:
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data = le32toh(bus_space_read_4(t, h, offset));
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break;
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default:
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return (~0U);
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}
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return (data);
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}
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static void
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thunder_pem_write_config(device_t dev, u_int bus, u_int slot,
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u_int func, u_int reg, uint32_t val, int bytes)
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{
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uint64_t offset;
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struct thunder_pem_softc *sc;
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bus_space_tag_t t;
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bus_space_handle_t h;
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if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
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(func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
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return;
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sc = device_get_softc(dev);
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/* Calculate offset */
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offset = (bus << PEM_BUS_SHIFT) | (slot << PEM_SLOT_SHIFT) |
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(func << PEM_FUNC_SHIFT) | reg;
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t = sc->reg_bst;
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h = sc->pem_sli_base;
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switch (bytes) {
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case 1:
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bus_space_write_1(t, h, offset, val);
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break;
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case 2:
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bus_space_write_2(t, h, offset, htole16(val));
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break;
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case 4:
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bus_space_write_4(t, h, offset, htole32(val));
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break;
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default:
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return;
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}
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}
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static struct resource *
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thunder_pem_alloc_resource(device_t dev, device_t child, int type, int *rid,
|
||||
u_long start, u_long end, u_long count, u_int flags)
|
||||
{
|
||||
struct thunder_pem_softc *sc = device_get_softc(dev);
|
||||
struct rman *rm = NULL;
|
||||
struct resource *res;
|
||||
device_t parent_dev;
|
||||
|
||||
switch (type) {
|
||||
case SYS_RES_IOPORT:
|
||||
rm = &sc->io_rman;
|
||||
break;
|
||||
case SYS_RES_MEMORY:
|
||||
rm = &sc->mem_rman;
|
||||
break;
|
||||
default:
|
||||
/* Find parent device. On ThunderX we know an exact path. */
|
||||
parent_dev = device_get_parent(device_get_parent(dev));
|
||||
return (BUS_ALLOC_RESOURCE(parent_dev, dev, type, rid, start,
|
||||
end, count, flags));
|
||||
};
|
||||
|
||||
if ((start == 0UL) && (end == ~0UL)) {
|
||||
device_printf(dev,
|
||||
"Cannot allocate resource with unspecified range\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* Translate PCI address to host PHYS */
|
||||
if (range_addr_is_pci(sc->ranges, start, count) == 0)
|
||||
goto fail;
|
||||
start = range_addr_pci_to_phys(sc->ranges, start);
|
||||
end = start + count - 1;
|
||||
|
||||
if (bootverbose) {
|
||||
device_printf(dev,
|
||||
"rman_reserve_resource: start=%#lx, end=%#lx, count=%#lx\n",
|
||||
start, end, count);
|
||||
}
|
||||
|
||||
res = rman_reserve_resource(rm, start, end, count, flags, child);
|
||||
if (res == NULL)
|
||||
goto fail;
|
||||
|
||||
rman_set_rid(res, *rid);
|
||||
|
||||
if (flags & RF_ACTIVE)
|
||||
if (bus_activate_resource(child, type, *rid, res)) {
|
||||
rman_release_resource(res);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
return (res);
|
||||
|
||||
fail:
|
||||
if (bootverbose) {
|
||||
device_printf(dev, "%s FAIL: type=%d, rid=%d, "
|
||||
"start=%016lx, end=%016lx, count=%016lx, flags=%x\n",
|
||||
__func__, type, *rid, start, end, count, flags);
|
||||
}
|
||||
|
||||
return (NULL);
|
||||
}
|
||||
|
||||
static int
|
||||
thunder_pem_release_resource(device_t dev, device_t child, int type, int rid,
|
||||
struct resource *res)
|
||||
{
|
||||
device_t parent_dev;
|
||||
|
||||
/* Find parent device. On ThunderX we know an exact path. */
|
||||
parent_dev = device_get_parent(device_get_parent(dev));
|
||||
|
||||
if ((type != SYS_RES_MEMORY) && (type != SYS_RES_IOPORT))
|
||||
return (BUS_RELEASE_RESOURCE(parent_dev, child,
|
||||
type, rid, res));
|
||||
|
||||
return (rman_release_resource(res));
|
||||
}
|
||||
|
||||
static int
|
||||
thunder_pem_probe(device_t dev)
|
||||
{
|
||||
uint16_t pci_vendor_id;
|
||||
uint16_t pci_device_id;
|
||||
|
||||
pci_vendor_id = pci_get_vendor(dev);
|
||||
pci_device_id = pci_get_device(dev);
|
||||
|
||||
if ((pci_vendor_id == THUNDER_PEM_VENDOR_ID) &&
|
||||
(pci_device_id == THUNDER_PEM_DEVICE_ID)) {
|
||||
device_set_desc_copy(dev, THUNDER_PEM_DESC);
|
||||
return (0);
|
||||
}
|
||||
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
static int
|
||||
thunder_pem_attach(device_t dev)
|
||||
{
|
||||
struct thunder_pem_softc *sc;
|
||||
int error;
|
||||
int rid;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
sc->dev = dev;
|
||||
|
||||
/* Allocate memory for BAR(0) */
|
||||
rid = PCIR_BAR(0);
|
||||
sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
||||
&rid, RF_ACTIVE);
|
||||
if (sc->reg == NULL) {
|
||||
device_printf(dev, "Failed to allocate resource\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
sc->reg_bst = rman_get_bustag(sc->reg);
|
||||
sc->reg_bsh = rman_get_bushandle(sc->reg);
|
||||
|
||||
/* Map SLI, do it only once */
|
||||
if (!sli0_s2m_regx_base) {
|
||||
bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC,
|
||||
SLIX_S2M_REGX_ACC_SIZE, 0, &sli0_s2m_regx_base);
|
||||
}
|
||||
if (!sli1_s2m_regx_base) {
|
||||
bus_space_map(sc->reg_bst, SLIX_S2M_REGX_ACC +
|
||||
SLIX_S2M_REGX_ACC_SPACING, SLIX_S2M_REGX_ACC_SIZE, 0,
|
||||
&sli1_s2m_regx_base);
|
||||
}
|
||||
|
||||
if ((sli0_s2m_regx_base == 0) || (sli1_s2m_regx_base == 0)) {
|
||||
device_printf(dev,
|
||||
"bus_space_map failed to map slix_s2m_regx_base\n");
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* Identify PEM */
|
||||
if (thunder_pem_identify(dev) != 0)
|
||||
goto fail;
|
||||
|
||||
/* Initialize rman and allocate regions */
|
||||
sc->mem_rman.rm_type = RMAN_ARRAY;
|
||||
sc->mem_rman.rm_descr = "PEM PCIe Memory";
|
||||
error = rman_init(&sc->mem_rman);
|
||||
if (error != 0) {
|
||||
device_printf(dev, "memory rman_init() failed. error = %d\n",
|
||||
error);
|
||||
goto fail;
|
||||
}
|
||||
sc->io_rman.rm_type = RMAN_ARRAY;
|
||||
sc->io_rman.rm_descr = "PEM PCIe IO";
|
||||
error = rman_init(&sc->io_rman);
|
||||
if (error != 0) {
|
||||
device_printf(dev, "IO rman_init() failed. error = %d\n",
|
||||
error);
|
||||
goto fail_mem;
|
||||
}
|
||||
|
||||
/* Fill memory window */
|
||||
sc->ranges[0].pci_base = PCI_MEMORY_BASE;
|
||||
sc->ranges[0].size = PCI_MEMORY_SIZE;
|
||||
sc->ranges[0].phys_base = sc->sli_window_base + SLI_PCI_OFFSET +
|
||||
sc->ranges[0].pci_base;
|
||||
rman_manage_region(&sc->mem_rman, sc->ranges[0].phys_base,
|
||||
sc->ranges[0].phys_base + sc->ranges[0].size - 1);
|
||||
|
||||
/* Fill IO window */
|
||||
sc->ranges[1].pci_base = PCI_IO_BASE;
|
||||
sc->ranges[1].size = PCI_IO_SIZE;
|
||||
sc->ranges[1].phys_base = sc->sli_window_base + SLI_PCI_OFFSET +
|
||||
sc->ranges[1].pci_base;
|
||||
rman_manage_region(&sc->io_rman, sc->ranges[1].phys_base,
|
||||
sc->ranges[1].phys_base + sc->ranges[1].size - 1);
|
||||
|
||||
if (thunder_pem_init(sc)) {
|
||||
device_printf(dev, "Failure during PEM init\n");
|
||||
goto fail_io;
|
||||
}
|
||||
|
||||
device_add_child(dev, "pci", -1);
|
||||
|
||||
return (bus_generic_attach(dev));
|
||||
|
||||
fail_io:
|
||||
rman_fini(&sc->io_rman);
|
||||
fail_mem:
|
||||
rman_fini(&sc->mem_rman);
|
||||
fail:
|
||||
bus_free_resource(dev, SYS_RES_MEMORY, sc->reg);
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
static void
|
||||
thunder_pem_release_all(device_t dev)
|
||||
{
|
||||
struct thunder_pem_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
rman_fini(&sc->io_rman);
|
||||
rman_fini(&sc->mem_rman);
|
||||
|
||||
if (sc->reg != NULL)
|
||||
bus_free_resource(dev, SYS_RES_MEMORY, sc->reg);
|
||||
}
|
||||
|
||||
static int
|
||||
thunder_pem_detach(device_t dev)
|
||||
{
|
||||
|
||||
thunder_pem_release_all(dev);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static devclass_t thunder_pem_devclass;
|
||||
|
||||
DRIVER_MODULE(thunder_pem, pci, thunder_pem_driver, thunder_pem_devclass, 0, 0);
|
||||
MODULE_DEPEND(thunder_pem, pci, 1, 1, 1);
|
||||
|
|
@ -51,6 +51,7 @@ arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack
|
|||
arm64/arm64/vfp.c standard
|
||||
arm64/arm64/vm_machdep.c standard
|
||||
arm64/cavium/thunder_pcie.c optional thunder_pci fdt
|
||||
arm64/cavium/thunder_pcie_pem.c optional thunder_pci
|
||||
arm64/cavium/thunder_pcie_common.c optional thunder_pci
|
||||
crypto/blowfish/bf_enc.c optional crypto | ipsec
|
||||
crypto/des/des_enc.c optional crypto | ipsec | netsmb
|
||||
|
|
|
|||
Loading…
Reference in a new issue