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arm64: HWCAP/HWCAP2 aux args support for 32-bit ARM binaries.
This fixes build/run of golang under COMPAT32 emulation.
PR: 256897
Reviewed by: andrew, mmel, manu, jhb, cognet, Robert Clausecker
Tested by: brd, andrew, Robert Clausecker
MFC after: 3 weeks
Relnotes: yes
Sponsored by: Rubicon Communications, LLC ("Netgate")
Differential Revision: https://reviews.freebsd.org/D31175
This commit is contained in:
Peter Grehan
parent
87c010e6e3
commit
bbe80bff7c
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@ -77,6 +77,9 @@ static boolean_t elf32_arm_abi_supported(struct image_params *, int32_t *,
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extern void freebsd32_sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask);
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u_long __read_frequently elf32_hwcap;
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u_long __read_frequently elf32_hwcap2;
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static struct sysentvec elf32_freebsd_sysvec = {
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.sv_size = SYS_MAXSYSCALL,
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.sv_table = freebsd32_sysent,
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@ -112,6 +115,8 @@ static struct sysentvec elf32_freebsd_sysvec = {
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.sv_schedtail = NULL,
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.sv_thread_detach = NULL,
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.sv_trap = NULL,
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.sv_hwcap = &elf32_hwcap,
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.sv_hwcap2 = &elf32_hwcap2,
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.sv_onexec_old = exec_onexec_old,
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.sv_onexit = exit_onexit,
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};
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@ -50,6 +50,10 @@ __FBSDID("$FreeBSD$");
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static void print_cpu_features(u_int cpu);
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static u_long parse_cpu_features_hwcap(void);
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static u_long parse_cpu_features_hwcap2(void);
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#ifdef COMPAT_FREEBSD32
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static u_long parse_cpu_features_hwcap32(void);
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static u_long parse_cpu_features_hwcap32_2(void);
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#endif
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char machine[] = "arm64";
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@ -135,6 +139,11 @@ struct cpu_desc {
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uint64_t id_aa64pfr0;
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uint64_t id_aa64pfr1;
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uint64_t ctr;
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#ifdef COMPAT_FREEBSD32
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uint64_t id_isar5;
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uint64_t mvfr0;
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uint64_t mvfr1;
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#endif
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};
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static struct cpu_desc cpu_desc[MAXCPU];
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@ -152,6 +161,11 @@ static u_int cpu_print_regs;
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#define PRINT_ID_AA64_MMFR2 0x00004000
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#define PRINT_ID_AA64_PFR0 0x00010000
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#define PRINT_ID_AA64_PFR1 0x00020000
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#ifdef COMPAT_FREEBSD32
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#define PRINT_ID_ISAR5 0x01000000
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#define PRINT_MVFR0 0x02000000
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#define PRINT_MVFR1 0x04000000
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#endif
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#define PRINT_CTR_EL0 0x10000000
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struct cpu_parts {
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@ -987,6 +1001,167 @@ static struct mrs_field id_aa64pfr1_fields[] = {
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MRS_FIELD_END,
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};
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#ifdef COMPAT_FREEBSD32
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/* ID_ISAR5_EL1 */
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static struct mrs_field_value id_isar5_vcma[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, VCMA, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_isar5_rdm[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, RDM, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_isar5_crc32[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, CRC32, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_isar5_sha2[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SHA2, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_isar5_sha1[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SHA1, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_isar5_aes[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, AES, NONE, BASE),
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MRS_FIELD_VALUE(ID_ISAR5_AES_VMULL, "AES+VMULL"),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value id_isar5_sevl[] = {
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MRS_FIELD_VALUE_NONE_IMPL(ID_ISAR5, SEVL, NOP, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field id_isar5_fields[] = {
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MRS_FIELD(ID_ISAR5, VCMA, false, MRS_LOWER, id_isar5_vcma),
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MRS_FIELD(ID_ISAR5, RDM, false, MRS_LOWER, id_isar5_rdm),
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MRS_FIELD(ID_ISAR5, CRC32, false, MRS_LOWER, id_isar5_crc32),
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MRS_FIELD(ID_ISAR5, SHA2, false, MRS_LOWER, id_isar5_sha2),
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MRS_FIELD(ID_ISAR5, SHA1, false, MRS_LOWER, id_isar5_sha1),
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MRS_FIELD(ID_ISAR5, AES, false, MRS_LOWER, id_isar5_aes),
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MRS_FIELD(ID_ISAR5, SEVL, false, MRS_LOWER, id_isar5_sevl),
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MRS_FIELD_END,
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};
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/* MVFR0 */
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static struct mrs_field_value mvfr0_fpround[] = {
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MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPRound, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value mvfr0_fpsqrt[] = {
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MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPSqrt, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value mvfr0_fpdivide[] = {
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MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPDivide, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value mvfr0_fptrap[] = {
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MRS_FIELD_VALUE_NONE_IMPL(MVFR0, FPTrap, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value mvfr0_fpdp[] = {
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MRS_FIELD_VALUE(MVFR0_FPDP_NONE, ""),
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MRS_FIELD_VALUE(MVFR0_FPDP_VFP_v2, "DP VFPv2"),
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MRS_FIELD_VALUE(MVFR0_FPDP_VFP_v3_v4, "DP VFPv3+v4"),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value mvfr0_fpsp[] = {
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MRS_FIELD_VALUE(MVFR0_FPSP_NONE, ""),
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MRS_FIELD_VALUE(MVFR0_FPSP_VFP_v2, "SP VFPv2"),
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MRS_FIELD_VALUE(MVFR0_FPSP_VFP_v3_v4, "SP VFPv3+v4"),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value mvfr0_simdreg[] = {
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MRS_FIELD_VALUE(MVFR0_SIMDReg_NONE, ""),
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MRS_FIELD_VALUE(MVFR0_SIMDReg_FP, "FP 16x64"),
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MRS_FIELD_VALUE(MVFR0_SIMDReg_AdvSIMD, "AdvSIMD"),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field mvfr0_fields[] = {
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MRS_FIELD(MVFR0, FPRound, false, MRS_LOWER, mvfr0_fpround),
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MRS_FIELD(MVFR0, FPSqrt, false, MRS_LOWER, mvfr0_fpsqrt),
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MRS_FIELD(MVFR0, FPDivide, false, MRS_LOWER, mvfr0_fpdivide),
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MRS_FIELD(MVFR0, FPTrap, false, MRS_LOWER, mvfr0_fptrap),
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MRS_FIELD(MVFR0, FPDP, false, MRS_LOWER, mvfr0_fpdp),
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MRS_FIELD(MVFR0, FPSP, false, MRS_LOWER, mvfr0_fpsp),
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MRS_FIELD(MVFR0, SIMDReg, false, MRS_LOWER, mvfr0_simdreg),
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MRS_FIELD_END,
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};
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/* MVFR1 */
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static struct mrs_field_value mvfr1_simdfmac[] = {
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MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDFMAC, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value mvfr1_fphp[] = {
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MRS_FIELD_VALUE(MVFR1_FPHP_NONE, ""),
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MRS_FIELD_VALUE(MVFR1_FPHP_CONV_SP, "FPHP SP Conv"),
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MRS_FIELD_VALUE(MVFR1_FPHP_CONV_DP, "FPHP DP Conv"),
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MRS_FIELD_VALUE(MVFR1_FPHP_ARITH, "FPHP Arith"),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value mvfr1_simdhp[] = {
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MRS_FIELD_VALUE(MVFR1_SIMDHP_NONE, ""),
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MRS_FIELD_VALUE(MVFR1_SIMDHP_CONV_SP, "SIMDHP SP Conv"),
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MRS_FIELD_VALUE(MVFR1_SIMDHP_ARITH, "SIMDHP Arith"),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value mvfr1_simdsp[] = {
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MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDSP, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value mvfr1_simdint[] = {
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MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDInt, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value mvfr1_simdls[] = {
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MRS_FIELD_VALUE_NONE_IMPL(MVFR1, SIMDLS, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value mvfr1_fpdnan[] = {
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MRS_FIELD_VALUE_NONE_IMPL(MVFR1, FPDNaN, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field_value mvfr1_fpftz[] = {
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MRS_FIELD_VALUE_NONE_IMPL(MVFR1, FPFtZ, NONE, IMPL),
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MRS_FIELD_VALUE_END,
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};
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static struct mrs_field mvfr1_fields[] = {
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MRS_FIELD(MVFR1, SIMDFMAC, false, MRS_LOWER, mvfr1_simdfmac),
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MRS_FIELD(MVFR1, FPHP, false, MRS_LOWER, mvfr1_fphp),
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MRS_FIELD(MVFR1, SIMDHP, false, MRS_LOWER, mvfr1_simdhp),
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MRS_FIELD(MVFR1, SIMDSP, false, MRS_LOWER, mvfr1_simdsp),
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MRS_FIELD(MVFR1, SIMDInt, false, MRS_LOWER, mvfr1_simdint),
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MRS_FIELD(MVFR1, SIMDLS, false, MRS_LOWER, mvfr1_simdls),
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MRS_FIELD(MVFR1, FPDNaN, false, MRS_LOWER, mvfr1_fpdnan),
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MRS_FIELD(MVFR1, FPFtZ, false, MRS_LOWER, mvfr1_fpftz),
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MRS_FIELD_END,
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};
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#endif /* COMPAT_FREEBSD32 */
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struct mrs_user_reg {
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u_int reg;
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u_int CRm;
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@ -1038,6 +1213,32 @@ static struct mrs_user_reg user_regs[] = {
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.offset = __offsetof(struct cpu_desc, id_aa64mmfr0),
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.fields = id_aa64mmfr0_fields,
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},
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#ifdef COMPAT_FREEBSD32
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{
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/* id_isar5_el1 */
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.reg = ID_ISAR5_EL1,
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.CRm = 2,
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.Op2 = 5,
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.offset = __offsetof(struct cpu_desc, id_isar5),
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.fields = id_isar5_fields,
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},
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{
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/* mvfr0 */
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.reg = MVFR0_EL1,
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.CRm = 3,
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.Op2 = 0,
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.offset = __offsetof(struct cpu_desc, mvfr0),
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.fields = mvfr0_fields,
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},
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{
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/* mvfr1 */
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.reg = MVFR1_EL1,
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.CRm = 3,
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.Op2 = 1,
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.offset = __offsetof(struct cpu_desc, mvfr1),
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.fields = mvfr1_fields,
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},
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#endif /* COMPAT_FREEBSD32 */
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};
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#define CPU_DESC_FIELD(desc, idx) \
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@ -1288,6 +1489,12 @@ identify_cpu_sysinit(void *dummy __unused)
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elf_hwcap = parse_cpu_features_hwcap();
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elf_hwcap2 = parse_cpu_features_hwcap2();
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#ifdef COMPAT_FREEBSD32
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/* 32-bit ARM versions of AT_HWCAP/HWCAP2 */
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elf32_hwcap = parse_cpu_features_hwcap32();
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elf32_hwcap2 = parse_cpu_features_hwcap32_2();
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#endif
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if (dic && idc) {
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arm64_icache_sync_range = &arm64_dic_idc_icache_sync_range;
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if (bootverbose)
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@ -1499,6 +1706,66 @@ parse_cpu_features_hwcap2(void)
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return (hwcap2);
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}
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#ifdef COMPAT_FREEBSD32
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static u_long
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parse_cpu_features_hwcap32(void)
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{
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u_long hwcap = HWCAP32_DEFAULT;
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if (MVFR0_FPDP_VAL(user_cpu_desc.mvfr0) >=
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MVFR0_FPDP_VFP_v2) {
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hwcap |= HWCAP32_VFP;
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if (MVFR0_FPDP_VAL(user_cpu_desc.mvfr0) ==
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MVFR0_FPDP_VFP_v3_v4) {
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hwcap |= HWCAP32_VFPv3;
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if (MVFR1_SIMDFMAC_VAL(user_cpu_desc.mvfr1) ==
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MVFR1_SIMDFMAC_IMPL)
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hwcap |= HWCAP32_VFPv4;
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}
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}
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if ((MVFR1_SIMDLS_VAL(user_cpu_desc.mvfr1) ==
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MVFR1_SIMDLS_IMPL) &&
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(MVFR1_SIMDInt_VAL(user_cpu_desc.mvfr1) ==
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MVFR1_SIMDInt_IMPL) &&
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(MVFR1_SIMDSP_VAL(user_cpu_desc.mvfr1) ==
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MVFR1_SIMDSP_IMPL))
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hwcap |= HWCAP32_NEON;
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return (hwcap);
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}
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static u_long
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parse_cpu_features_hwcap32_2(void)
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{
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u_long hwcap2 = 0;
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if (ID_ISAR5_AES_VAL(user_cpu_desc.id_isar5) >=
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ID_ISAR5_AES_BASE)
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hwcap2 |= HWCAP32_2_AES;
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if (ID_ISAR5_AES_VAL(user_cpu_desc.id_isar5) ==
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ID_ISAR5_AES_VMULL)
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hwcap2 |= HWCAP32_2_PMULL;
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if (ID_ISAR5_SHA1_VAL(user_cpu_desc.id_isar5) ==
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ID_ISAR5_SHA1_IMPL)
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hwcap2 |= HWCAP32_2_SHA1;
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if (ID_ISAR5_SHA2_VAL(user_cpu_desc.id_isar5) ==
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ID_ISAR5_SHA2_IMPL)
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hwcap2 |= HWCAP32_2_SHA2;
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if (ID_ISAR5_CRC32_VAL(user_cpu_desc.id_isar5) ==
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ID_ISAR5_CRC32_IMPL)
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hwcap2 |= HWCAP32_2_CRC32;
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return (hwcap2);
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}
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#endif /* COMPAT_FREEBSD32 */
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static void
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print_ctr_fields(struct sbuf *sb, uint64_t reg, void *arg)
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{
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@ -1712,6 +1979,23 @@ print_cpu_features(u_int cpu)
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print_id_register(sb, "Auxiliary Features 1",
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cpu_desc[cpu].id_aa64afr1, id_aa64afr1_fields);
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#ifdef COMPAT_FREEBSD32
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/* AArch32 Instruction Set Attribute Register 5 */
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if (cpu == 0 || (cpu_print_regs & PRINT_ID_ISAR5) != 0)
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print_id_register(sb, "AArch32 Instruction Set Attributes 5",
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cpu_desc[cpu].id_isar5, id_isar5_fields);
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/* AArch32 Media and VFP Feature Register 0 */
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if (cpu == 0 || (cpu_print_regs & PRINT_MVFR0) != 0)
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print_id_register(sb, "AArch32 Media and VFP Features 0",
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cpu_desc[cpu].mvfr0, mvfr0_fields);
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/* AArch32 Media and VFP Feature Register 1 */
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if (cpu == 0 || (cpu_print_regs & PRINT_MVFR1) != 0)
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print_id_register(sb, "AArch32 Media and VFP Features 1",
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cpu_desc[cpu].mvfr1, mvfr1_fields);
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#endif
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sbuf_delete(sb);
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sb = NULL;
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#undef SEP_STR
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@ -1811,6 +2095,15 @@ identify_cpu(u_int cpu)
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cpu_desc[cpu].id_aa64mmfr2 = READ_SPECIALREG(id_aa64mmfr2_el1);
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cpu_desc[cpu].id_aa64pfr0 = READ_SPECIALREG(id_aa64pfr0_el1);
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cpu_desc[cpu].id_aa64pfr1 = READ_SPECIALREG(id_aa64pfr1_el1);
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#ifdef COMPAT_FREEBSD32
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/* Only read aarch32 SRs if EL0-32 is available */
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if (ID_AA64PFR0_EL0_VAL(cpu_desc[cpu].id_aa64pfr0) ==
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ID_AA64PFR0_EL0_64_32) {
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cpu_desc[cpu].id_isar5 = READ_SPECIALREG(id_isar5_el1);
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cpu_desc[cpu].mvfr0 = READ_SPECIALREG(mvfr0_el1);
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cpu_desc[cpu].mvfr1 = READ_SPECIALREG(mvfr1_el1);
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}
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#endif
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}
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static void
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@ -1875,4 +2168,13 @@ check_cpu_regs(u_int cpu)
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identify_cache(cpu_desc[cpu].ctr);
|
||||
cpu_print_regs |= PRINT_CTR_EL0;
|
||||
}
|
||||
|
||||
#ifdef COMPAT_FREEBSD32
|
||||
if (cpu_desc[cpu].id_isar5 != cpu_desc[0].id_isar5)
|
||||
cpu_print_regs |= PRINT_ID_ISAR5;
|
||||
if (cpu_desc[cpu].mvfr0 != cpu_desc[0].mvfr0)
|
||||
cpu_print_regs |= PRINT_MVFR0;
|
||||
if (cpu_desc[cpu].mvfr1 != cpu_desc[0].mvfr1)
|
||||
cpu_print_regs |= PRINT_MVFR1;
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -771,6 +771,45 @@
|
|||
#define ID_AA64PFR1_RAS_frac_V1 (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT)
|
||||
#define ID_AA64PFR1_RAS_frac_V2 (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT)
|
||||
|
||||
/* ID_ISAR5_EL1 */
|
||||
#define ID_ISAR5_EL1 MRS_REG(3, 0, 0, 2, 5)
|
||||
#define ID_ISAR5_SEVL_SHIFT 0
|
||||
#define ID_ISAR5_SEVL_MASK (UL(0xf) << ID_ISAR5_SEVL_SHIFT)
|
||||
#define ID_ISAR5_SEVL_VAL(x) ((x) & ID_ISAR5_SEVL_MASK)
|
||||
#define ID_ISAR5_SEVL_NOP (UL(0x0) << ID_ISAR5_SEVL_SHIFT)
|
||||
#define ID_ISAR5_SEVL_IMPL (UL(0x1) << ID_ISAR5_SEVL_SHIFT)
|
||||
#define ID_ISAR5_AES_SHIFT 4
|
||||
#define ID_ISAR5_AES_MASK (UL(0xf) << ID_ISAR5_AES_SHIFT)
|
||||
#define ID_ISAR5_AES_VAL(x) ((x) & ID_ISAR5_AES_MASK)
|
||||
#define ID_ISAR5_AES_NONE (UL(0x0) << ID_ISAR5_AES_SHIFT)
|
||||
#define ID_ISAR5_AES_BASE (UL(0x1) << ID_ISAR5_AES_SHIFT)
|
||||
#define ID_ISAR5_AES_VMULL (UL(0x2) << ID_ISAR5_AES_SHIFT)
|
||||
#define ID_ISAR5_SHA1_SHIFT 8
|
||||
#define ID_ISAR5_SHA1_MASK (UL(0xf) << ID_ISAR5_SHA1_SHIFT)
|
||||
#define ID_ISAR5_SHA1_VAL(x) ((x) & ID_ISAR5_SHA1_MASK)
|
||||
#define ID_ISAR5_SHA1_NONE (UL(0x0) << ID_ISAR5_SHA1_SHIFT)
|
||||
#define ID_ISAR5_SHA1_IMPL (UL(0x1) << ID_ISAR5_SHA1_SHIFT)
|
||||
#define ID_ISAR5_SHA2_SHIFT 12
|
||||
#define ID_ISAR5_SHA2_MASK (UL(0xf) << ID_ISAR5_SHA2_SHIFT)
|
||||
#define ID_ISAR5_SHA2_VAL(x) ((x) & ID_ISAR5_SHA2_MASK)
|
||||
#define ID_ISAR5_SHA2_NONE (UL(0x0) << ID_ISAR5_SHA2_SHIFT)
|
||||
#define ID_ISAR5_SHA2_IMPL (UL(0x1) << ID_ISAR5_SHA2_SHIFT)
|
||||
#define ID_ISAR5_CRC32_SHIFT 16
|
||||
#define ID_ISAR5_CRC32_MASK (UL(0xf) << ID_ISAR5_CRC32_SHIFT)
|
||||
#define ID_ISAR5_CRC32_VAL(x) ((x) & ID_ISAR5_CRC32_MASK)
|
||||
#define ID_ISAR5_CRC32_NONE (UL(0x0) << ID_ISAR5_CRC32_SHIFT)
|
||||
#define ID_ISAR5_CRC32_IMPL (UL(0x1) << ID_ISAR5_CRC32_SHIFT)
|
||||
#define ID_ISAR5_RDM_SHIFT 24
|
||||
#define ID_ISAR5_RDM_MASK (UL(0xf) << ID_ISAR5_RDM_SHIFT)
|
||||
#define ID_ISAR5_RDM_VAL(x) ((x) & ID_ISAR5_RDM_MASK)
|
||||
#define ID_ISAR5_RDM_NONE (UL(0x0) << ID_ISAR5_RDM_SHIFT)
|
||||
#define ID_ISAR5_RDM_IMPL (UL(0x1) << ID_ISAR5_RDM_SHIFT)
|
||||
#define ID_ISAR5_VCMA_SHIFT 28
|
||||
#define ID_ISAR5_VCMA_MASK (UL(0xf) << ID_ISAR5_VCMA_SHIFT)
|
||||
#define ID_ISAR5_VCMA_VAL(x) ((x) & ID_ISAR5_VCMA_MASK)
|
||||
#define ID_ISAR5_VCMA_NONE (UL(0x0) << ID_ISAR5_VCMA_SHIFT)
|
||||
#define ID_ISAR5_VCMA_IMPL (UL(0x1) << ID_ISAR5_VCMA_SHIFT)
|
||||
|
||||
/* MAIR_EL1 - Memory Attribute Indirection Register */
|
||||
#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8))
|
||||
#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
|
||||
|
|
@ -780,6 +819,98 @@
|
|||
#define MAIR_NORMAL_WT 0xbb
|
||||
#define MAIR_NORMAL_WB 0xff
|
||||
|
||||
/* MVFR0_EL1 */
|
||||
#define MVFR0_EL1 MRS_REG(3, 0, 0, 3, 0)
|
||||
#define MVFR0_SIMDReg_SHIFT 0
|
||||
#define MVFR0_SIMDReg_MASK (UL(0xf) << MVFR0_SIMDReg_SHIFT)
|
||||
#define MVFR0_SIMDReg_VAL(x) ((x) & MVFR0_SIMDReg_MASK)
|
||||
#define MVFR0_SIMDReg_NONE (UL(0x0) << MVFR0_SIMDReg_SHIFT)
|
||||
#define MVFR0_SIMDReg_FP (UL(0x1) << MVFR0_SIMDReg_SHIFT)
|
||||
#define MVFR0_SIMDReg_AdvSIMD (UL(0x2) << MVFR0_SIMDReg_SHIFT)
|
||||
#define MVFR0_FPSP_SHIFT 4
|
||||
#define MVFR0_FPSP_MASK (UL(0xf) << MVFR0_FPSP_SHIFT)
|
||||
#define MVFR0_FPSP_VAL(x) ((x) & MVFR0_FPSP_MASK)
|
||||
#define MVFR0_FPSP_NONE (UL(0x0) << MVFR0_FPSP_SHIFT)
|
||||
#define MVFR0_FPSP_VFP_v2 (UL(0x1) << MVFR0_FPSP_SHIFT)
|
||||
#define MVFR0_FPSP_VFP_v3_v4 (UL(0x2) << MVFR0_FPSP_SHIFT)
|
||||
#define MVFR0_FPDP_SHIFT 8
|
||||
#define MVFR0_FPDP_MASK (UL(0xf) << MVFR0_FPDP_SHIFT)
|
||||
#define MVFR0_FPDP_VAL(x) ((x) & MVFR0_FPDP_MASK)
|
||||
#define MVFR0_FPDP_NONE (UL(0x0) << MVFR0_FPDP_SHIFT)
|
||||
#define MVFR0_FPDP_VFP_v2 (UL(0x1) << MVFR0_FPDP_SHIFT)
|
||||
#define MVFR0_FPDP_VFP_v3_v4 (UL(0x2) << MVFR0_FPDP_SHIFT)
|
||||
#define MVFR0_FPTrap_SHIFT 12
|
||||
#define MVFR0_FPTrap_MASK (UL(0xf) << MVFR0_FPTrap_SHIFT)
|
||||
#define MVFR0_FPTrap_VAL(x) ((x) & MVFR0_FPTrap_MASK)
|
||||
#define MVFR0_FPTrap_NONE (UL(0x0) << MVFR0_FPTrap_SHIFT)
|
||||
#define MVFR0_FPTrap_IMPL (UL(0x1) << MVFR0_FPTrap_SHIFT)
|
||||
#define MVFR0_FPDivide_SHIFT 16
|
||||
#define MVFR0_FPDivide_MASK (UL(0xf) << MVFR0_FPDivide_SHIFT)
|
||||
#define MVFR0_FPDivide_VAL(x) ((x) & MVFR0_FPDivide_MASK)
|
||||
#define MVFR0_FPDivide_NONE (UL(0x0) << MVFR0_FPDivide_SHIFT)
|
||||
#define MVFR0_FPDivide_IMPL (UL(0x1) << MVFR0_FPDivide_SHIFT)
|
||||
#define MVFR0_FPSqrt_SHIFT 20
|
||||
#define MVFR0_FPSqrt_MASK (UL(0xf) << MVFR0_FPSqrt_SHIFT)
|
||||
#define MVFR0_FPSqrt_VAL(x) ((x) & MVFR0_FPSqrt_MASK)
|
||||
#define MVFR0_FPSqrt_NONE (UL(0x0) << MVFR0_FPSqrt_SHIFT)
|
||||
#define MVFR0_FPSqrt_IMPL (UL(0x1) << MVFR0_FPSqrt_SHIFT)
|
||||
#define MVFR0_FPShVec_SHIFT 24
|
||||
#define MVFR0_FPShVec_MASK (UL(0xf) << MVFR0_FPShVec_SHIFT)
|
||||
#define MVFR0_FPShVec_VAL(x) ((x) & MVFR0_FPShVec_MASK)
|
||||
#define MVFR0_FPShVec_NONE (UL(0x0) << MVFR0_FPShVec_SHIFT)
|
||||
#define MVFR0_FPShVec_IMPL (UL(0x1) << MVFR0_FPShVec_SHIFT)
|
||||
#define MVFR0_FPRound_SHIFT 28
|
||||
#define MVFR0_FPRound_MASK (UL(0xf) << MVFR0_FPRound_SHIFT)
|
||||
#define MVFR0_FPRound_VAL(x) ((x) & MVFR0_FPRound_MASK)
|
||||
#define MVFR0_FPRound_NONE (UL(0x0) << MVFR0_FPRound_SHIFT)
|
||||
#define MVFR0_FPRound_IMPL (UL(0x1) << MVFR0_FPRound_SHIFT)
|
||||
|
||||
/* MVFR1_EL1 */
|
||||
#define MVFR1_EL1 MRS_REG(3, 0, 0, 3, 1)
|
||||
#define MVFR1_FPFtZ_SHIFT 0
|
||||
#define MVFR1_FPFtZ_MASK (UL(0xf) << MVFR1_FPFtZ_SHIFT)
|
||||
#define MVFR1_FPFtZ_VAL(x) ((x) & MVFR1_FPFtZ_MASK)
|
||||
#define MVFR1_FPFtZ_NONE (UL(0x0) << MVFR1_FPFtZ_SHIFT)
|
||||
#define MVFR1_FPFtZ_IMPL (UL(0x1) << MVFR1_FPFtZ_SHIFT)
|
||||
#define MVFR1_FPDNaN_SHIFT 4
|
||||
#define MVFR1_FPDNaN_MASK (UL(0xf) << MVFR1_FPDNaN_SHIFT)
|
||||
#define MVFR1_FPDNaN_VAL(x) ((x) & MVFR1_FPDNaN_MASK)
|
||||
#define MVFR1_FPDNaN_NONE (UL(0x0) << MVFR1_FPDNaN_SHIFT)
|
||||
#define MVFR1_FPDNaN_IMPL (UL(0x1) << MVFR1_FPDNaN_SHIFT)
|
||||
#define MVFR1_SIMDLS_SHIFT 8
|
||||
#define MVFR1_SIMDLS_MASK (UL(0xf) << MVFR1_SIMDLS_SHIFT)
|
||||
#define MVFR1_SIMDLS_VAL(x) ((x) & MVFR1_SIMDLS_MASK)
|
||||
#define MVFR1_SIMDLS_NONE (UL(0x0) << MVFR1_SIMDLS_SHIFT)
|
||||
#define MVFR1_SIMDLS_IMPL (UL(0x1) << MVFR1_SIMDLS_SHIFT)
|
||||
#define MVFR1_SIMDInt_SHIFT 12
|
||||
#define MVFR1_SIMDInt_MASK (UL(0xf) << MVFR1_SIMDInt_SHIFT)
|
||||
#define MVFR1_SIMDInt_VAL(x) ((x) & MVFR1_SIMDInt_MASK)
|
||||
#define MVFR1_SIMDInt_NONE (UL(0x0) << MVFR1_SIMDInt_SHIFT)
|
||||
#define MVFR1_SIMDInt_IMPL (UL(0x1) << MVFR1_SIMDInt_SHIFT)
|
||||
#define MVFR1_SIMDSP_SHIFT 16
|
||||
#define MVFR1_SIMDSP_MASK (UL(0xf) << MVFR1_SIMDSP_SHIFT)
|
||||
#define MVFR1_SIMDSP_VAL(x) ((x) & MVFR1_SIMDSP_MASK)
|
||||
#define MVFR1_SIMDSP_NONE (UL(0x0) << MVFR1_SIMDSP_SHIFT)
|
||||
#define MVFR1_SIMDSP_IMPL (UL(0x1) << MVFR1_SIMDSP_SHIFT)
|
||||
#define MVFR1_SIMDHP_SHIFT 20
|
||||
#define MVFR1_SIMDHP_MASK (UL(0xf) << MVFR1_SIMDHP_SHIFT)
|
||||
#define MVFR1_SIMDHP_VAL(x) ((x) & MVFR1_SIMDHP_MASK)
|
||||
#define MVFR1_SIMDHP_NONE (UL(0x0) << MVFR1_SIMDHP_SHIFT)
|
||||
#define MVFR1_SIMDHP_CONV_SP (UL(0x1) << MVFR1_SIMDHP_SHIFT)
|
||||
#define MVFR1_SIMDHP_ARITH (UL(0x2) << MVFR1_SIMDHP_SHIFT)
|
||||
#define MVFR1_FPHP_SHIFT 24
|
||||
#define MVFR1_FPHP_MASK (UL(0xf) << MVFR1_FPHP_SHIFT)
|
||||
#define MVFR1_FPHP_VAL(x) ((x) & MVFR1_FPHP_MASK)
|
||||
#define MVFR1_FPHP_NONE (UL(0x0) << MVFR1_FPHP_SHIFT)
|
||||
#define MVFR1_FPHP_CONV_SP (UL(0x1) << MVFR1_FPHP_SHIFT)
|
||||
#define MVFR1_FPHP_CONV_DP (UL(0x2) << MVFR1_FPHP_SHIFT)
|
||||
#define MVFR1_FPHP_ARITH (UL(0x3) << MVFR1_FPHP_SHIFT)
|
||||
#define MVFR1_SIMDFMAC_SHIFT 28
|
||||
#define MVFR1_SIMDFMAC_MASK (UL(0xf) << MVFR1_SIMDFMAC_SHIFT)
|
||||
#define MVFR1_SIMDFMAC_VAL(x) ((x) & MVFR1_SIMDFMAC_MASK)
|
||||
#define MVFR1_SIMDFMAC_NONE (UL(0x0) << MVFR1_SIMDFMAC_SHIFT)
|
||||
#define MVFR1_SIMDFMAC_IMPL (UL(0x1) << MVFR1_SIMDFMAC_SHIFT)
|
||||
|
||||
/* PAR_EL1 - Physical Address Register */
|
||||
#define PAR_F_SHIFT 0
|
||||
#define PAR_F (0x1 << PAR_F_SHIFT)
|
||||
|
|
|
|||
|
|
@ -150,4 +150,33 @@ __ElfType(Auxinfo);
|
|||
#define HWCAP2_RNG 0x00010000
|
||||
#define HWCAP2_BTI 0x00020000
|
||||
|
||||
#ifdef COMPAT_FREEBSD32
|
||||
/* ARM HWCAP */
|
||||
#define HWCAP32_HALF 0x00000002 /* Always set. */
|
||||
#define HWCAP32_THUMB 0x00000004 /* Always set. */
|
||||
#define HWCAP32_FAST_MULT 0x00000010 /* Always set. */
|
||||
#define HWCAP32_VFP 0x00000040
|
||||
#define HWCAP32_EDSP 0x00000080 /* Always set. */
|
||||
#define HWCAP32_NEON 0x00001000
|
||||
#define HWCAP32_VFPv3 0x00002000
|
||||
#define HWCAP32_TLS 0x00008000 /* Always set. */
|
||||
#define HWCAP32_VFPv4 0x00010000
|
||||
#define HWCAP32_IDIVA 0x00020000 /* Always set. */
|
||||
#define HWCAP32_IDIVT 0x00040000 /* Always set. */
|
||||
#define HWCAP32_VFPD32 0x00080000 /* Always set. */
|
||||
#define HWCAP32_LPAE 0x00100000 /* Always set. */
|
||||
|
||||
#define HWCAP32_DEFAULT \
|
||||
(HWCAP32_HALF | HWCAP32_THUMB | HWCAP32_FAST_MULT | HWCAP32_EDSP |\
|
||||
HWCAP32_TLS | HWCAP32_IDIVA | HWCAP32_IDIVT | HWCAP32_VFPD32 | \
|
||||
HWCAP32_LPAE)
|
||||
|
||||
/* ARM HWCAP2 */
|
||||
#define HWCAP32_2_AES 0x00000001
|
||||
#define HWCAP32_2_PMULL 0x00000002
|
||||
#define HWCAP32_2_SHA1 0x00000004
|
||||
#define HWCAP32_2_SHA2 0x00000008
|
||||
#define HWCAP32_2_CRC32 0x00000010
|
||||
#endif
|
||||
|
||||
#endif /* !_MACHINE_ELF_H_ */
|
||||
|
|
|
|||
|
|
@ -38,6 +38,10 @@ extern char sigcode[];
|
|||
extern int szsigcode;
|
||||
extern u_long elf_hwcap;
|
||||
extern u_long elf_hwcap2;
|
||||
#ifdef COMPAT_FREEBSD32
|
||||
extern u_long elf32_hwcap;
|
||||
extern u_long elf32_hwcap2;
|
||||
#endif
|
||||
|
||||
struct dumperinfo;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue