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- Calculate clock frequency using PLL registers

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- Remove stale comments
This commit is contained in:
Oleksandr Tymoshenko 2009-05-15 01:54:32 +00:00
parent b31707c849
commit b75cca0708
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/projects/mips/; revision=192133
1 changed files with 17 additions and 10 deletions
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27
sys/mips/atheros/uart_cpu_ar71xx.c
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@ -53,27 +53,34 @@ uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
int
uart_cpu_getdev(int devtype, struct uart_devinfo *di)
{
uint32_t pll_config, div;
uint64_t freq;
/* PLL freq */
pll_config = ATH_READ_REG(AR71XX_PLL_CPU_CONFIG);
div = ((pll_config >> PLL_FB_SHIFT) & PLL_FB_MASK) + 1;
freq = div * AR71XX_BASE_FREQ;
/* CPU freq */
div = ((pll_config >> PLL_CPU_DIV_SEL_SHIFT) & PLL_CPU_DIV_SEL_MASK)
+ 1;
freq = freq / div;
/* AHB freq */
div = (((pll_config >> PLL_AHB_DIV_SHIFT) & PLL_AHB_DIV_MASK) + 1) * 2;
freq = freq / div;
di->ops = uart_getops(&uart_ns8250_class);
di->bas.chan = 0;
di->bas.bst = ar71xx_bus_space_reversed;
di->bas.regshft = 2;
/* TODO: calculate proper AHB freq using PLL registers */
di->bas.rclk = 85000000;
di->bas.rclk = freq;
di->baudrate = 115200;
di->databits = 8;
di->stopbits = 1;
di->parity = UART_PARITY_NONE;
/* TODO: check if uart_bus_space_io mandatory to set */
uart_bus_space_io = NULL;
uart_bus_space_mem = ar71xx_bus_space_reversed;
/*
* FIXME:
* 3 is to compensate big endian, uart operates
* with bus_space_read_1/bus_space_write_1 and hence gets
* highest byte instead of lowest one. Actual fix will involve
* MIPS bus_space fixing.
*/
di->bas.bsh = MIPS_PHYS_TO_KSEG1(AR71XX_UART_ADDR);
return (0);
}