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e1000: Corrections for lem(4)/em(4) txcsum offload
Explicitly set ipcss/ipcse/ipcso for IPv6 per intel SDM as indicated in
inline comments.
Fix and consolidate 82543/82547 hwcsum exemption.
While here rearrange and expand some commentary.
(cherry picked from commit cbcab907f8
)
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41e440c381
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@ -186,7 +186,7 @@ em_tso_setup(struct e1000_softc *sc, if_pkt_info_t pi, uint32_t *txd_upper,
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TXD->tcp_seg_setup.fields.hdr_len = hdr_len;
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/*
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* 8254x SDM4.0 page 45, and PCIe GbE SDM2.5 page 63
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* "PCI/PCI-X SDM 4.0" page 45, and "PCIe GbE SDM 2.5" page 63
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* - Set up basic TUCMDs
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* - Enable IP bit on 82544
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* - For others IP bit on indicates IPv4, while off indicates IPv6
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@ -212,10 +212,6 @@ em_tso_setup(struct e1000_softc *sc, if_pkt_info_t pi, uint32_t *txd_upper,
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return (cur);
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}
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#define TSO_WORKAROUND 4
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#define DONT_FORCE_CTX 1
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/*********************************************************************
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* The offload context is protocol specific (TCP/UDP) and thus
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* only needs to be set when the protocol changes. The occasion
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@ -232,6 +228,7 @@ em_tso_setup(struct e1000_softc *sc, if_pkt_info_t pi, uint32_t *txd_upper,
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* in turn greatly slow down performance to send small sized
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* frames.
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**********************************************************************/
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#define DONT_FORCE_CTX 1
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static int
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em_transmit_checksum_setup(struct e1000_softc *sc, if_pkt_info_t pi,
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@ -271,20 +268,30 @@ em_transmit_checksum_setup(struct e1000_softc *sc, if_pkt_info_t pi,
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}
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TXD = (struct e1000_context_desc *)&txr->tx_base[cur];
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/*
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* ipcss - Start offset for header checksum calculation.
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* ipcse - End offset for header checksum calculation.
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* ipcso - Offset of place to put the checksum.
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*
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* We set ipcsX values regardless of IP version to work around HW issues
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* and ipcse must be 0 for IPv6 per "PCIe GbE SDM 2.5" page 61.
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* IXSM controls whether it's inserted.
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*/
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TXD->lower_setup.ip_fields.ipcss = pi->ipi_ehdrlen;
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TXD->lower_setup.ip_fields.ipcso = pi->ipi_ehdrlen +
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offsetof(struct ip, ip_sum);
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if (csum_flags & CSUM_IP) {
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*txd_upper |= E1000_TXD_POPTS_IXSM << 8;
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/*
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* Start offset for header checksum calculation.
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* End offset for header checksum calculation.
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* Offset of place to put the checksum.
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*/
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TXD->lower_setup.ip_fields.ipcss = pi->ipi_ehdrlen;
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TXD->lower_setup.ip_fields.ipcse = htole16(hdr_len);
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TXD->lower_setup.ip_fields.ipcso = pi->ipi_ehdrlen +
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offsetof(struct ip, ip_sum);
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cmd |= E1000_TXD_CMD_IP;
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}
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} else if (csum_flags & (CSUM_IP6_TCP | CSUM_IP6_UDP))
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TXD->lower_setup.ip_fields.ipcse = htole16(0);
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/*
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* tucss - Start offset for payload checksum calculation.
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* tucse - End offset for payload checksum calculation.
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* tucso - Offset of place to put the checksum.
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*/
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if (csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_IP6_TCP | CSUM_IP6_UDP)) {
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uint8_t tucso;
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@ -320,6 +327,8 @@ em_transmit_checksum_setup(struct e1000_softc *sc, if_pkt_info_t pi,
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return (cur);
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}
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#define TSO_WORKAROUND 4 /* TSO sentinel descriptor */
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static int
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em_isc_txd_encap(void *arg, if_pkt_info_t pi)
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{
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@ -950,15 +950,13 @@ em_if_attach_pre(if_ctx_t ctx)
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scctx->isc_tx_csum_flags = CSUM_TCP | CSUM_UDP | CSUM_IP_TSO |
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CSUM_IP6_TCP | CSUM_IP6_UDP;
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/* 8254x SDM4.0 page 33 - FDX requirement on these chips */
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if (hw->mac.type == e1000_82547 || hw->mac.type == e1000_82547_rev_2)
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/* "PCI/PCI-X SDM 4.0" page 33 (b) - FDX requirement on these chips */
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if (hw->mac.type < e1000_82543 || hw->mac.type == e1000_82547 ||
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hw->mac.type == e1000_82547_rev_2)
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scctx->isc_capenable &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
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if (hw->mac.type < e1000_82543)
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scctx->isc_capabilities &= ~(IFCAP_HWCSUM|IFCAP_VLAN_HWCSUM);
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/* 82541ER doesn't do HW tagging */
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if (hw->device_id == E1000_DEV_ID_82541ER || hw->device_id == E1000_DEV_ID_82541ER_LOM)
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scctx->isc_capabilities &= ~IFCAP_VLAN_HWTAGGING;
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scctx->isc_capenable &= ~IFCAP_VLAN_HWTAGGING;
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/* INTx only */
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scctx->isc_msix_bar = 0;
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}
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@ -1354,7 +1352,6 @@ em_if_init(if_ctx_t ctx)
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E1000_RAR_ENTRIES - 1);
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}
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/* Initialize the hardware */
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em_reset(ctx);
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em_if_update_admin_status(ctx);
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