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https://github.com/freebsd/freebsd-src
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Don't bother enabling interrupts before we're ready to handle them. This
prevents the firmware of Fujitsu Siemens PRIMEPOWER250, which both causes stray interrupts and erroneously enables interrupts at least when calling SUNW,set-trap-table, in the foot.
This commit is contained in:
parent
18333f544e
commit
b641222476
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=207248
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@ -58,13 +58,6 @@ void
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cheetah_init(u_int cpu_impl)
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{
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u_long val;
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register_t s;
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/*
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* Disable interrupts for safety, this shouldn't be actually
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* necessary though.
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*/
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s = intr_disable();
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/* Ensure the TSB Extension Registers hold 0 as TSB_Base. */
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@ -134,8 +127,6 @@ cheetah_init(u_int cpu_impl)
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val &= ~DCR_DTPE;
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}
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wr(asr18, val, 0);
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intr_restore(s);
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}
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/*
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@ -29,6 +29,7 @@ __FBSDID("$FreeBSD$");
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#include <machine/asi.h>
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#include <machine/asmacros.h>
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#include <machine/intr_machdep.h>
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#include <machine/pstate.h>
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#include <machine/wstate.h>
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@ -47,7 +48,7 @@ ENTRY(btext)
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ENTRY(_start)
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/*
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* Initialize misc. state to known values: interrupts disabled, normal
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* globals, windows flushed (cr = 0, cs = nwindows - 1), PIL 0 and
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* globals, windows flushed (cr = 0, cs = nwindows - 1), PIL_TICK and
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* floating point disabled.
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* Note that some firmware versions don't implement a clean window
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* trap handler so we unfortunately can't clear the windows by setting
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@ -55,7 +56,7 @@ ENTRY(_start)
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*/
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wrpr %g0, PSTATE_NORMAL, %pstate
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flushw
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wrpr %g0, 0, %pil
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wrpr %g0, PIL_TICK, %pil
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wr %g0, 0, %fprs
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/*
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@ -65,11 +66,6 @@ ENTRY(_start)
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SET(pcpu0 + (PCPU_PAGES * PAGE_SIZE) - PC_SIZEOF, %l1, %l0)
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sub %l0, SPOFF + CCFSZ, %sp
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/*
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* Enable interrupts.
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*/
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wrpr %g0, PSTATE_KERNEL, %pstate
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/*
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* Do initial bootstrap to setup pmap and thread0.
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*/
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@ -97,7 +93,7 @@ ENTRY(cpu_setregs)
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ldx [%o0 + PC_CURPCB], %o1
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/*
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* Disable interrupts, normal globals.
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* Ensure we are on normal globals.
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*/
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wrpr %g0, PSTATE_NORMAL, %pstate
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@ -147,11 +143,6 @@ ENTRY(cpu_setregs)
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wrpr %o1, 0, %tba
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stw %o3, [%o2]
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/*
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* Re-enable interrupts.
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*/
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wrpr %g0, PSTATE_KERNEL, %pstate
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retl
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nop
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END(cpu_setregs)
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@ -341,7 +341,7 @@ sparc64_init(caddr_t mdp, u_long o1, u_long o2, u_long o3, ofw_vec_t *vec)
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cpu_impl = VER_IMPL(rdpr(ver));
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/*
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* Do CPU-specific Initialization.
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* Do CPU-specific initialization.
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*/
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if (cpu_impl >= CPU_IMPL_ULTRASPARCIII)
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cheetah_init(cpu_impl);
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@ -477,6 +477,10 @@ sparc64_init(caddr_t mdp, u_long o1, u_long o2, u_long o3, ofw_vec_t *vec)
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sizeof(itlb_slots)) == -1)
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panic("sparc64_init: cannot determine number of iTLB slots");
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/*
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* Initialize and enable the caches. Note that his may include
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* applying workarounds.
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*/
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cache_init(pc);
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cache_enable(cpu_impl);
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uma_set_align(pc->pc_cache.dc_linesize - 1);
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@ -568,8 +572,18 @@ sparc64_init(caddr_t mdp, u_long o1, u_long o2, u_long o3, ofw_vec_t *vec)
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dpcpu_init(dpcpu0, 0);
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msgbufinit(msgbufp, MSGBUF_SIZE);
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/*
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* Initialize mutexes.
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*/
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mutex_init();
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/*
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* Finish the interrupt initialization now that mutexes work and
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* enable them.
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*/
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intr_init2();
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wrpr(pil, 0, PIL_TICK);
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wrpr(pstate, 0, PSTATE_KERNEL);
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/*
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* Finish pmap initialization now that we're ready for mutexes.
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@ -30,6 +30,7 @@ __FBSDID("$FreeBSD$");
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#include <machine/asi.h>
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#include <machine/asmacros.h>
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#include <machine/intr_machdep.h>
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#include <machine/ktr.h>
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#include <machine/pstate.h>
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#include <machine/smp.h>
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@ -44,14 +45,14 @@ __FBSDID("$FreeBSD$");
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_ALIGN_TEXT
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/*
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* Initialize misc. state to known values: interrupts disabled, normal
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* globals, windows flushed (cr = 0, cs = nwindows - 1), PIL 0 and
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* globals, windows flushed (cr = 0, cs = nwindows - 1), PIL_TICK and
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* floating point disabled.
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* Note that some firmware versions don't implement a clean window
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* trap handler so we unfortunately can't clear the windows by setting
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* %cleanwin to zero here.
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*/
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1: wrpr %g0, PSTATE_NORMAL, %pstate
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wrpr %g0, 0, %pil
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wrpr %g0, PIL_TICK, %pil
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wr %g0, 0, %fprs
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rdpr %ver, %l7
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@ -262,11 +263,6 @@ ENTRY(mp_startup)
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add %l1, %l2, %l1
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sub %l1, SPOFF + CCFSZ, %sp
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/*
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* Enable interrupts.
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*/
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wrpr %g0, PSTATE_KERNEL, %pstate
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#if KTR_COMPILE & KTR_SMP
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CATR(KTR_SMP,
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"mp_startup: bootstrap cpuid=%d mid=%d pcpu=%#lx data=%#lx sp=%#lx"
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@ -409,16 +409,32 @@ cpu_mp_bootstrap(struct pcpu *pc)
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volatile struct cpu_start_args *csa;
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csa = &cpu_start_args;
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/* Do CPU-specific initialization. */
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if (pc->pc_impl >= CPU_IMPL_ULTRASPARCIII)
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cheetah_init(pc->pc_impl);
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/*
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* Enable the caches. Note that his may include applying workarounds.
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*/
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cache_enable(pc->pc_impl);
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/* Lock the kernel TSB in the TLB. */
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pmap_map_tsb();
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/*
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* Flush all non-locked TLB entries possibly left over by the
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* firmware.
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*/
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tlb_flush_nonlocked();
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/* Initialize global registers. */
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cpu_setregs(pc);
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/* Enable interrupts. */
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wrpr(pil, 0, PIL_TICK);
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wrpr(pstate, 0, PSTATE_KERNEL);
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/* Start the (S)TICK interrupts. */
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tick_start();
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smp_cpus++;
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