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Don't bother enabling interrupts before we're ready to handle them. This

Browse source 
prevents the firmware of Fujitsu Siemens PRIMEPOWER250, which both causes
stray interrupts and erroneously enables interrupts at least when calling
SUNW,set-trap-table, in the foot.
This commit is contained in:
Marius Strobl 2010-04-26 20:19:49 +00:00
parent 18333f544e
commit b641222476
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=207248
5 changed files with 38 additions and 30 deletions
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9
sys/sparc64/sparc64/cheetah.c
View file

@ -58,13 +58,6 @@ void
cheetah_init(u_int cpu_impl)
{
u_long val;
register_t s;
/*
* Disable interrupts for safety, this shouldn't be actually
* necessary though.
*/
s = intr_disable();
/* Ensure the TSB Extension Registers hold 0 as TSB_Base. */
@ -134,8 +127,6 @@ cheetah_init(u_int cpu_impl)
val &= ~DCR_DTPE;
}
wr(asr18, val, 0);
intr_restore(s);
}
/*

17
sys/sparc64/sparc64/locore.S
View file

@ -29,6 +29,7 @@ __FBSDID("$FreeBSD$");
#include <machine/asi.h>
#include <machine/asmacros.h>
#include <machine/intr_machdep.h>
#include <machine/pstate.h>
#include <machine/wstate.h>
@ -47,7 +48,7 @@ ENTRY(btext)
ENTRY(_start)
/*
* Initialize misc. state to known values: interrupts disabled, normal
* globals, windows flushed (cr = 0, cs = nwindows - 1), PIL 0 and
* globals, windows flushed (cr = 0, cs = nwindows - 1), PIL_TICK and
* floating point disabled.
* Note that some firmware versions don't implement a clean window
* trap handler so we unfortunately can't clear the windows by setting
@ -55,7 +56,7 @@ ENTRY(_start)
*/
wrpr %g0, PSTATE_NORMAL, %pstate
flushw
wrpr %g0, 0, %pil
wrpr %g0, PIL_TICK, %pil
wr %g0, 0, %fprs
/*
@ -65,11 +66,6 @@ ENTRY(_start)
SET(pcpu0 + (PCPU_PAGES * PAGE_SIZE) - PC_SIZEOF, %l1, %l0)
sub %l0, SPOFF + CCFSZ, %sp
/*
* Enable interrupts.
*/
wrpr %g0, PSTATE_KERNEL, %pstate
/*
* Do initial bootstrap to setup pmap and thread0.
*/
@ -97,7 +93,7 @@ ENTRY(cpu_setregs)
ldx [%o0 + PC_CURPCB], %o1
/*
* Disable interrupts, normal globals.
* Ensure we are on normal globals.
*/
wrpr %g0, PSTATE_NORMAL, %pstate
@ -147,11 +143,6 @@ ENTRY(cpu_setregs)
wrpr %o1, 0, %tba
stw %o3, [%o2]
/*
* Re-enable interrupts.
*/
wrpr %g0, PSTATE_KERNEL, %pstate
retl
nop
END(cpu_setregs)

16
sys/sparc64/sparc64/machdep.c
View file

@ -341,7 +341,7 @@ sparc64_init(caddr_t mdp, u_long o1, u_long o2, u_long o3, ofw_vec_t *vec)
cpu_impl = VER_IMPL(rdpr(ver));
/*
* Do CPU-specific Initialization.
* Do CPU-specific initialization.
*/
if (cpu_impl >= CPU_IMPL_ULTRASPARCIII)
cheetah_init(cpu_impl);
@ -477,6 +477,10 @@ sparc64_init(caddr_t mdp, u_long o1, u_long o2, u_long o3, ofw_vec_t *vec)
sizeof(itlb_slots)) == -1)
panic("sparc64_init: cannot determine number of iTLB slots");
/*
* Initialize and enable the caches. Note that his may include
* applying workarounds.
*/
cache_init(pc);
cache_enable(cpu_impl);
uma_set_align(pc->pc_cache.dc_linesize - 1);
@ -568,8 +572,18 @@ sparc64_init(caddr_t mdp, u_long o1, u_long o2, u_long o3, ofw_vec_t *vec)
dpcpu_init(dpcpu0, 0);
msgbufinit(msgbufp, MSGBUF_SIZE);
/*
* Initialize mutexes.
*/
mutex_init();
/*
* Finish the interrupt initialization now that mutexes work and
* enable them.
*/
intr_init2();
wrpr(pil, 0, PIL_TICK);
wrpr(pstate, 0, PSTATE_KERNEL);
/*
* Finish pmap initialization now that we're ready for mutexes.

10
sys/sparc64/sparc64/mp_locore.S
View file

@ -30,6 +30,7 @@ __FBSDID("$FreeBSD$");
#include <machine/asi.h>
#include <machine/asmacros.h>
#include <machine/intr_machdep.h>
#include <machine/ktr.h>
#include <machine/pstate.h>
#include <machine/smp.h>
@ -44,14 +45,14 @@ __FBSDID("$FreeBSD$");
_ALIGN_TEXT
/*
* Initialize misc. state to known values: interrupts disabled, normal
* globals, windows flushed (cr = 0, cs = nwindows - 1), PIL 0 and
* globals, windows flushed (cr = 0, cs = nwindows - 1), PIL_TICK and
* floating point disabled.
* Note that some firmware versions don't implement a clean window
* trap handler so we unfortunately can't clear the windows by setting
* %cleanwin to zero here.
*/
1: wrpr %g0, PSTATE_NORMAL, %pstate
wrpr %g0, 0, %pil
wrpr %g0, PIL_TICK, %pil
wr %g0, 0, %fprs
rdpr %ver, %l7
@ -262,11 +263,6 @@ ENTRY(mp_startup)
add %l1, %l2, %l1
sub %l1, SPOFF + CCFSZ, %sp
/*
* Enable interrupts.
*/
wrpr %g0, PSTATE_KERNEL, %pstate
#if KTR_COMPILE & KTR_SMP
CATR(KTR_SMP,
"mp_startup: bootstrap cpuid=%d mid=%d pcpu=%#lx data=%#lx sp=%#lx"

16
sys/sparc64/sparc64/mp_machdep.c
View file

@ -409,16 +409,32 @@ cpu_mp_bootstrap(struct pcpu *pc)
volatile struct cpu_start_args *csa;
csa = &cpu_start_args;
/* Do CPU-specific initialization. */
if (pc->pc_impl >= CPU_IMPL_ULTRASPARCIII)
cheetah_init(pc->pc_impl);
/*
* Enable the caches. Note that his may include applying workarounds.
*/
cache_enable(pc->pc_impl);
/* Lock the kernel TSB in the TLB. */
pmap_map_tsb();
/*
* Flush all non-locked TLB entries possibly left over by the
* firmware.
*/
tlb_flush_nonlocked();
/* Initialize global registers. */
cpu_setregs(pc);
/* Enable interrupts. */
wrpr(pil, 0, PIL_TICK);
wrpr(pstate, 0, PSTATE_KERNEL);
/* Start the (S)TICK interrupts. */
tick_start();
smp_cpus++;