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Add Simon Shapiro's DPT driver

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this shouldn't break anything existing.
Userland utilities to follow.
This commit is contained in:
Julian Elischer 1998-01-26 06:11:18 +00:00
parent f5c9b8cbc7
commit b37c91fdc7
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=32801
14 changed files with 7434 additions and 8 deletions
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5
sys/conf/files.i386
View file

@ -1,7 +1,7 @@
# This file tells config what files go into building a kernel,
# files marked standard are always included.
#
# $Id: files.i386,v 1.185 1998/01/15 07:30:54 gibbs Exp $
# $Id: files.i386,v 1.186 1998/01/16 22:13:00 pst Exp $
#
# The long compile-with and dependency lines are required because of
# limitations in config: backslash-newline doesn't work in strings, and
@ -313,3 +313,6 @@ gnu/i386/fpemul/wm_sqrt.s optional gpl_math_emulate
gnu/i386/isa/dgb.c optional dgb device-driver
gnu/i386/isa/sound/awe_wave.c optional awe device-driver
pci/ide_pci.c optional wd device-driver
dev/dpt/dpt_control.c optional dpt device-driver
dev/dpt/dpt_scsi.c optional dpt device-driver
pci/dpt_pci.c optional dpt device-driver

3
sys/conf/majors
View file

@ -1,4 +1,4 @@
$Id: majors.i386,v 1.23 1997/12/09 10:51:11 jamil Exp $
$Id: majors.i386,v 1.24 1998/01/16 22:13:01 pst Exp $
Hopefully, this list will one day be obsoleted by DEVFS, but for now
this is the current allocation of device major numbers.
@ -127,3 +127,4 @@ chrdev name comments
85 vesa VESA support device (j_mini@efn.org)
86 alog Industrial Computer Source AIO8-P driver
87 wfd ATAPI floppy client of "ata"
88 dpt DPT RAID Controller <shimon@i-connect.net>

11
sys/conf/options.i386
View file

@ -1,4 +1,4 @@
# $Id: options.i386,v 1.66 1997/12/28 13:36:00 phk Exp $
# $Id: options.i386,v 1.67 1998/01/25 04:37:47 eivind Exp $
BOUNCEPAGES opt_bounce.h
USER_LDT
@ -114,3 +114,12 @@ PCVT_SCANSET opt_pcvt.h
PCVT_SCREENSAVER opt_pcvt.h
PCVT_USEKBDSEC opt_pcvt.h
PCVT_VT220KEYB opt_pcvt.h
DPT_VERIFY_HINTR opt_dpt.h
DPT_USE_SINTR opt_dpt.h
DPT_RESTRICTED_FREELIST opt_dpt.h
DPT_MEASURE_PERFORMANCE opt_dpt.h
DPT_FREELIST_IS_STACK opt_dpt.h
DPT_HANDLE_TIMEOUTS opt_dpt.h
DPT_TIMEOUT_FACTOR opt_dpt.h
DPT_INTR_DELAY opt_dpt.h
DPT_LOST_IRQ opt_dpt.h

883
sys/dev/dpt/dpt_control.c Normal file
View file

@ -0,0 +1,883 @@
/**
* Copyright (c) 1997 by Simon Shapiro
* All Rights Reserved
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
/**
* dpt_control.c: Control Functions and /dev entry points for /dev/dpt*
*
* Caveat Emptor! This is work in progress. The interfaces and
* functionality of this code will change (possibly radically) in the
* future.
*/
#ident "$Id: dpt_control.c,v 1.21 1998/01/23 02:46:51 ShimonR Exp ShimonR $"
#include "opt_dpt.h"
#include <sys/types.h>
/* #include <i386/isa/isa.h> */
#include <i386/include/cputypes.h>
#include <i386/isa/timerreg.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/resourcevar.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/buf.h>
#include <sys/uio.h>
#include <sys/conf.h>
#include <machine/clock.h>
#include <machine/speaker.h>
#include <machine/cpu.h>
#include <machine/cpufunc.h>
#include <vm/vm.h>
#include <vm/vm_kern.h>
#include <vm/vm_extern.h>
#include <vm/pmap.h>
#include <scsi/scsi_all.h>
#include <scsi/scsi_message.h>
#include <scsi/scsiconf.h>
#include <sys/dpt.h>
#include <sys/queue.h>
#define INLINE __inline
extern char osrelease[];
dpt_sysinfo_t dpt_sysinfo;
/* Entry points and other prototypes */
static vm_offset_t dpt_physmap(u_int32_t paddr, vm_size_t size);
static void dpt_unphysmap(u_int8_t * vaddr, vm_size_t size);
static void dpt_get_sysinfo(void);
static INLINE dpt_softc_t *dpt_minor2softc(int minor_no);
static INLINE int dpt_minor2unit(int minor_no);
int dpt_open(dev_t dev, int flags, int fmt, struct proc * p);
int dpt_close(dev_t dev, int flags, int fmt, struct proc * p);
int dpt_write(dev_t dev, struct uio * uio, int ioflag);
int dpt_read(dev_t dev, struct uio * uio, int ioflag);
int dpt_ioctl(dev_t dev, int cmd, caddr_t cmdarg, int flags, struct proc * p);
/* This has to be modified as the processor and CPU are not known yet */
static dpt_sig_t dpt_sig = {
'd', 'P', 't', 'S', 'i', 'G',
SIG_VERSION, PROC_INTEL, PROC_386,
FT_HBADRVR, FTF_PROTECTED,
OEM_DPT, OS_FREEBSD,
CAP_PASS | CAP_OVERLAP | CAP_RAID0 | CAP_RAID1 | CAP_RAID5 | CAP_ASPI,
DEV_ALL, ADF_SC4_PCI | ADF_SC3_PCI, 0, 0,
DPT_RELEASE, DPT_VERSION, DPT_PATCH,
DPT_MONTH, DPT_DAY, DPT_YEAR,
"DPT FreeBSD Driver (c) 1997 Simon Shapiro"
};
#define CDEV_MAJOR DPT_CDEV_MAJOR
/* Normally, this is a static structure. But we need it in pci/dpt_pci.c */
struct cdevsw dpt_cdevsw = {
dpt_open, dpt_close, dpt_read, dpt_write,
dpt_ioctl, nostop, nullreset, nodevtotty,
seltrue, nommap, NULL, "dpt",
NULL, -1};
static struct buf *dpt_inbuf[DPT_MAX_ADAPTERS];
static char dpt_rw_command[DPT_MAX_ADAPTERS][DPT_RW_CMD_LEN + 1];
/**
* Map a physical address to virtual one.
* This is a first cut, experimental thing
*
* Paddr is the physical address to map
* size is the size of the region, in bytes.
* Because of alignment problems, we actually round up the size requested to
* the next page count.
*/
static vm_offset_t
dpt_physmap(u_int32_t req_paddr, vm_size_t req_size)
{
vm_offset_t va;
int ndx;
vm_size_t size;
u_int32_t paddr;
u_int32_t offset;
size = (req_size / PAGE_SIZE + 1) * PAGE_SIZE;
paddr = req_paddr & 0xfffff000;
offset = req_paddr - paddr;
va = kmem_alloc_pageable(kernel_map, size);
if (va == (vm_offset_t) 0)
return (va);
for (ndx = 0; ndx < size; ndx += PAGE_SIZE) {
pmap_kenter(va + ndx, paddr + ndx);
invltlb();
}
return (va + offset);
}
/*
* Release virtual space allocated by physmap We ASSUME that the correct
* srart address and the correct LENGTH are given.
*
* Disaster will follow if these assumptions are false!
*/
static void
dpt_unphysmap(u_int8_t * vaddr, vm_size_t size)
{
int ndx;
for (ndx = 0; ndx < size; ndx += PAGE_SIZE) {
pmap_kremove((vm_offset_t) vaddr + ndx);
}
kmem_free(kernel_map, (vm_offset_t) vaddr, size);
}
/**
* Given a minor device number, get its SCSI Unit.
*/
static INLINE int
dpt_minor2unit(int minor)
{
int unit;
unit = minor2hba(minor & ~SCSI_CONTROL_MASK);
return (unit);
}
/**
* Given a minor device number,
* return the pointer to it's softc structure
*/
static INLINE dpt_softc_t *
dpt_minor2softc(int minor_no)
{
dpt_softc_t *dpt;
if (dpt_minor2unit(minor_no & ~SCSI_CONTROL_MASK) == -1)
return (NULL);
for (dpt = TAILQ_FIRST(&dpt_softc_list);
(dpt != NULL) && (dpt->unit != (minor_no & ~SCSI_CONTROL_MASK));
dpt = TAILQ_NEXT(dpt, links));
return (dpt);
}
/**
* Collect interesting system information
* The following is one of the worst hacks I have ever allowed my
* name to be associated with.
* There MUST be a system structure that provides this data.
*/
static void
dpt_get_sysinfo(void)
{
int i;
int j;
int ospl;
char *addr;
bzero(&dpt_sysinfo, sizeof(dpt_sysinfo_t));
/**
* This is really silly, but we better run this in splhigh as we
* have no clue what we bump into.
* Let's hope anyone else who does this sort of things protects them
* with splhigh too.
*/
ospl = splhigh();
switch (cpu_class) {
case CPUCLASS_386:
dpt_sig.Processor = dpt_sysinfo.processorType = PROC_386;
break;
case CPUCLASS_486:
dpt_sig.Processor = dpt_sysinfo.processorType = PROC_486;
break;
case CPUCLASS_586:
dpt_sig.Processor = dpt_sysinfo.processorType = PROC_PENTIUM;
break;
case CPUCLASS_686:
dpt_sig.Processor = dpt_sysinfo.processorType = PROC_P6;
break;
default:
dpt_sig.Processor = dpt_sysinfo.flags &= ~SI_ProcessorValid;
break;
}
/* Get The First Drive Type From CMOS */
outb(0x70, 0x12);
i = inb(0x71);
j = i >> 4;
if (i == 0x0f) {
outb(0x70, 0x19);
j = inb(0x71);
}
dpt_sysinfo.drive0CMOS = j;
/* Get The Second Drive Type From CMOS */
j = i & 0x0f;
if (i == 0x0f) {
outb(0x70, 0x1a);
j = inb(0x71);
}
dpt_sysinfo.drive1CMOS = j;
/* Get The Number Of Drives From The Bios Data Area */
if ((addr = (char *) dpt_physmap(0x0475, 1024)) == NULL) {
printf("DPT: Cannot map BIOS address 0x0475. No sysinfo... :-(\n");
return;
}
dpt_sysinfo.numDrives = *addr;
dpt_unphysmap(addr, 1024);
/* Get the processor fields from the SIG structure, and set the flags */
dpt_sysinfo.processorFamily = dpt_sig.ProcessorFamily;
dpt_sysinfo.flags = SI_CMOS_Valid | SI_NumDrivesValid;
/* Go out and look for SmartROM */
for (i = 0; i < 3; ++i) {
switch (i) {
case 0:
addr = (char *) dpt_physmap(0xC8000, 1024);
case 1:
addr = (char *) dpt_physmap(0xD8000, 1024);
default:
addr = (char *) dpt_physmap(0xDC000, 1024);
}
if (addr == NULL)
continue;
if (*((u_int16_t *) addr) == 0xaa55) {
if ((*((u_int32_t *) (addr + 6)) == 0x00202053)
&& (*((u_int32_t *) (addr + 10)) == 0x00545044)) {
break;
}
}
dpt_unphysmap(addr, 1024);
addr = NULL;
}
/**
* If i < 3, we founday it so set up a pointer to the starting
* version digit by searching for it.
*/
if (addr != NULL) {
addr += 0x15;
for (i = 0; i < 64; ++i)
if ((addr[i] == ' ') && (addr[i + 1] == 'v'))
break;
if (i < 64) {
addr += (i + 4);
} else {
dpt_unphysmap(addr, 1024);
addr = NULL;
}
}
/* If all is well, set up the SmartROM version fields */
if (addr != NULL) {
dpt_sysinfo.smartROMMajorVersion = *addr - '0'; /* Assumes ASCII */
dpt_sysinfo.smartROMMinorVersion = *(addr + 2);
dpt_sysinfo.smartROMRevision = *(addr + 3);
dpt_sysinfo.flags |= SI_SmartROMverValid;
} else {
dpt_sysinfo.flags |= SI_NO_SmartROM;
}
/* Get the conventional memory size from CMOS */
outb(0x70, 0x16);
j = inb(0x71);
j <<= 8;
outb(0x70, 0x15);
j |= inb(0x71);
dpt_sysinfo.conventionalMemSize = j;
/**
* Get the extended memory found at power on from CMOS
*/
outb(0x70, 0x31);
j = inb(0x71);
j <<= 8;
outb(0x70, 0x30);
j |= inb(0x71);
dpt_sysinfo.extendedMemSize = j;
dpt_sysinfo.flags |= SI_MemorySizeValid;
/* If there is 1 or 2 drives found, set up the drive parameters */
if (dpt_sysinfo.numDrives > 0) {
/* Get the pointer from int 41 for the first drive parameters */
addr = (char *) dpt_physmap(0x0104, 1024);
if (addr != NULL) {
j = *((ushort *) (addr + 2));
j *= 16;
j += *((ushort *) (addr));
dpt_unphysmap(addr, 1024);
addr = (char *) dpt_physmap(j, 1024);
if (addr != NULL) {
dpt_sysinfo.drives[0].cylinders = *((ushort *) addr);
dpt_sysinfo.drives[0].heads = *(addr + 2);
dpt_sysinfo.drives[0].sectors = *(addr + 14);
dpt_unphysmap(addr, 1024);
}
}
if (dpt_sysinfo.numDrives > 1) {
/*
* Get the pointer from Int 46 for the second drive
* parameters
*/
addr = (char *) dpt_physmap(0x01118, 1024);
j = *((ushort *) (addr + 2));
j *= 16;
j += *((ushort *) (addr));
dpt_unphysmap(addr, 1024);
addr = (char *) dpt_physmap(j, 1024);
if (addr != NULL) {
dpt_sysinfo.drives[1].cylinders = *((ushort *) addr);
dpt_sysinfo.drives[1].heads = *(addr + 2);
dpt_sysinfo.drives[1].sectors = *(addr + 14);
dpt_unphysmap(addr, 1024);
}
}
dpt_sysinfo.flags |= SI_DriveParamsValid;
}
splx(ospl);
/* Get the processor information */
dpt_sysinfo.flags |= SI_ProcessorValid;
/* Get the bus I/O bus information */
dpt_sysinfo.flags |= SI_BusTypeValid;
dpt_sysinfo.busType = HBA_BUS_PCI;
#warning "O/S Version determination is an ugly hack"
dpt_sysinfo.osType = OS_FREEBSD;
dpt_sysinfo.osMajorVersion = osrelease[0] - '0';
if (osrelease[1] == '.')
dpt_sysinfo.osMinorVersion = osrelease[2] - '0';
else
dpt_sysinfo.osMinorVersion = 0;
if (osrelease[3] == '.')
dpt_sysinfo.osRevision = osrelease[4] - '0';
else
dpt_sysinfo.osMinorVersion = 0;
if (osrelease[5] == '.')
dpt_sysinfo.osSubRevision = osrelease[6] - '0';
else
dpt_sysinfo.osMinorVersion = 0;
dpt_sysinfo.flags |= SI_OSversionValid;
}
int
dpt_open(dev_t dev, int flags, int fmt, struct proc * p)
{
int minor_no;
int ospl;
dpt_softc_t *dpt;
minor_no = minor(dev);
if (dpt_minor2unit(minor_no) == -1)
return (ENXIO);
else
dpt = dpt_minor2softc(minor_no);
if (dpt == NULL)
return (ENXIO);
ospl = splbio();
if (dpt->state & DPT_HA_CONTROL_ACTIVE) {
splx(ospl);
return (EBUSY);
} else {
if ((dpt_inbuf[minor_no & ~SCSI_CONTROL_MASK] = geteblk(PAGE_SIZE))
== NULL) {
#ifdef DPT_DEBUG_CONTROL
printf("dpt%d: Failed to obtain an I/O buffer\n",
minor_no & ~SCSI_CONTROL_MASK);
#endif
return (EINVAL);
}
}
dpt->state |= DPT_HA_CONTROL_ACTIVE;
splx(ospl);
return (0);
}
int
dpt_close(dev_t dev, int flags, int fmt, struct proc * p)
{
int minor_no;
dpt_softc_t *dpt;
minor_no = minor(dev);
dpt = dpt_minor2softc(minor_no);
if ((dpt_minor2unit(minor_no) == -1) || (dpt == NULL))
return (ENXIO);
else {
brelse(dpt_inbuf[minor_no & ~SCSI_CONTROL_MASK]);
dpt->state &= ~DPT_HA_CONTROL_ACTIVE;
return (0);
}
}
int
dpt_write(dev_t dev, struct uio * uio, int ioflag)
{
int minor_no;
int unit;
int error;
minor_no = minor(dev);
if (minor_no & SCSI_CONTROL_MASK) {
#ifdef DPT_DEBUG_CONTROL
printf("dpt%d: I/O attempted to control channel (%x)\n",
dpt_minor2unit(minor_no), minor_no);
#endif
return (ENXIO);
}
unit = dpt_minor2unit(minor_no);
if (unit == -1) {
return (ENXIO);
} else if (uio->uio_resid > DPT_RW_CMD_LEN) {
return (E2BIG);
} else {
char *cp;
int length;
cp = dpt_inbuf[minor_no]->b_data;
length = uio->uio_resid; /* uiomove will change it! */
if ((error = uiomove(cp, length, uio) != 0)) {
#ifdef DPT_DEBUG_CONTROL
printf("dpt%d: uiomove(%x, %d, %x) failed (%d)\n",
minor_no, cp, length, uio, error);
#endif
return (error);
} else {
cp[length] = '\0';
/* A real kludge, to allow plain echo(1) to work */
if (cp[length - 1] == '\n')
cp[length - 1] = '\0';
strncpy(dpt_rw_command[unit], cp, DPT_RW_CMD_LEN);
#ifdef DPT_DEBUG_CONTROL
/**
* For lack of anything better to do;
* For now, dump the data so we can look at it and rejoice
*/
printf("dpt%d: Command \"%s\" arrived\n",
unit, dpt_rw_command[unit]);
#endif
}
}
return (error);
}
int
dpt_read(dev_t dev, struct uio * uio, int ioflag)
{
dpt_softc_t *dpt;
int error;
int minor_no;
int ospl;
minor_no = minor(dev);
error = 0;
#ifdef DPT_DEBUG_CONTROL
printf("dpt%d: read, count = %d, dev = %08x\n",
minor_no, uio->uio_resid, dev);
#endif
if (minor_no & SCSI_CONTROL_MASK) {
#ifdef DPT_DEBUG_CONTROL
printf("dpt%d: I/O attempted to control channel (%x)\n",
dpt_minor2unit(minor_no), minor_no);
#endif
return (ENXIO);
}
if (dpt_minor2unit(minor_no) == -1) {
return (ENXIO);
}
/*
* else if ( uio->uio_resid > PAGE_SIZE ) { return(E2BIG); }
*/
else {
char *work_buffer;
char *wbp;
char *command;
int work_size;
int ndx;
int x;
if ((dpt = dpt_minor2softc(minor_no)) == NULL)
return (ENXIO);
work_buffer = (u_int8_t *) malloc(PAGE_SIZE, M_TEMP, M_WAITOK);
wbp = work_buffer;
work_size = 0;
ospl = splbio();
command = dpt_rw_command[dpt->unit];
if (strcmp(command, DPT_RW_CMD_DUMP_SOFTC) == 0) {
x = sprintf(wbp, "dpt%d:%s:%s:%s:%s:%x\n",
dpt->unit,
dpt->board_data.vendor,
dpt->board_data.modelNum,
dpt->board_data.firmware,
dpt->board_data.protocol,
dpt->EATA_revision);
work_size += x;
wbp += x;
} else if (strcmp(command, DPT_RW_CMD_DUMP_SYSINFO) == 0) {
x = sprintf(wbp, "dpt%d:%d:%d:%d:%d:%d:%d:%d:%d:%s:"
"%d:%d:%d:%d:%d:%d:%d:%d\n",
dpt->unit,
dpt_sysinfo.drive0CMOS,
dpt_sysinfo.drive1CMOS,
dpt_sysinfo.numDrives,
dpt_sysinfo.processorFamily,
dpt_sysinfo.processorType,
dpt_sysinfo.smartROMMajorVersion,
dpt_sysinfo.smartROMMinorVersion,
dpt_sysinfo.smartROMRevision,
i2bin(dpt_sysinfo.flags,
sizeof(dpt->queue_status) * 8),
dpt_sysinfo.conventionalMemSize,
dpt_sysinfo.extendedMemSize,
dpt_sysinfo.osType, dpt_sysinfo.osMajorVersion,
dpt_sysinfo.osMinorVersion, dpt_sysinfo.osRevision,
dpt_sysinfo.osSubRevision, dpt_sysinfo.busType);
work_size += x;
wbp += x;
for (ndx = 0; ndx < 16; ndx++) {
if (dpt_sysinfo.drives[ndx].cylinders != 0) {
x = sprintf(wbp, "dpt%d:d%dc%dh%ds%d\n",
dpt->unit,
ndx,
dpt_sysinfo.drives[ndx].cylinders,
dpt_sysinfo.drives[ndx].heads,
dpt_sysinfo.drives[ndx].sectors);
work_size += x;
wbp += x;
}
}
} else if (strcmp(command, DPT_RW_CMD_DUMP_METRICS) == 0) {
x = sprintf(wbp,
"dpt%d: No metrics available.\n"
"Run the dpt_dm command, or use the\n"
"DPT_IOCTL_INTERNAL_METRICS ioctl system call\n",
dpt->unit);
work_size += x;
wbp += x;
} else if (strcmp(command, DPT_RW_CMD_CLEAR_METRICS) == 0) {
#ifdef DPT_MEASURE_PERFORMANCE
bzero(&dpt->performance, sizeof(dpt->performance));
#endif /* DPT_MEASURE_PERFORMANCE */
x = sprintf(wbp, "dpt%d: Metrics have been cleared\n",
dpt->unit);
work_size += x;
wbp += x;
} else if (strcmp(command, DPT_RW_CMD_SHOW_LED) == 0) {
#ifdef DPT_MEASURE_PERFORMANCE
bzero(&dpt->performance, sizeof(dpt->performance));
#endif /* DPT_MEASURE_PERFORMANCE */
x = sprintf(wbp, "dpt%d:%s\n",
dpt->unit, i2bin(dpt_blinking_led(dpt), 8));
work_size += x;
wbp += x;
} else {
#ifdef DPT_DEBUG_CONTROL
printf("dpt%d: Bad READ state (%s)\n", minor_no, command);
#endif
splx(ospl);
error = EINVAL;
}
if (error == 0) {
work_buffer[work_size++] = '\0';
error = uiomove(work_buffer, work_size, uio);
uio->uio_resid = 0;
#ifdef DPT_DEBUG_CONTROL
if (error) {
printf("dpt%d: READ uimove failed (%d)\n", dpt->unit, error);
}
#endif
}
}
splx(ospl);
return (error);
}
/**
* This is the control syscall interface.
* It should be binary compatible with UnixWare,
* if not totally syntatically so.
*/
int
dpt_ioctl(dev_t dev, int cmd, caddr_t cmdarg, int flags, struct proc * p)
{
int minor_no;
dpt_softc_t *dpt;
dpt_user_softc_t udpt;
int result;
int ndx;
eata_pt_t *eata_pass_thru;
minor_no = minor(dev);
result = 0;
if (!(minor_no & SCSI_CONTROL_MASK)) {
#ifdef DPT_DEBUG_CONTROL
printf("dpt%d: Control attempted to I/O channel (%x)\n",
dpt_minor2unit(minor_no), minor_no);
#endif /* DEBUG */
return (ENXIO);
} else
minor_no &= ~SCSI_CONTROL_MASK;
#ifdef DPT_DEBUG_CONTROL
printf("dpt%d: IOCTL(%x, %x, %p, %x, %p)\n",
minor_no, dev, cmd, cmdarg, flags, p);
#endif /* DEBUG */
if ((dpt = dpt_minor2softc(minor_no)) == NULL)
return (result);
switch (cmd) {
#ifdef DPT_MEASURE_PERFORMANCE
case DPT_IOCTL_INTERNAL_METRICS:
(void) memcpy(cmdarg, (char *) &dpt->performance, sizeof(dpt_perf_t));
return (0);
#endif /* DPT_MEASURE_PERFORMANCE */
case DPT_IOCTL_SOFTC:
udpt.unit = dpt->unit;
udpt.handle_interrupts = dpt->handle_interrupts;
udpt.target_mode_enabled = dpt->target_mode_enabled;
udpt.spare = dpt->spare;
udpt.total_ccbs_count = dpt->total_ccbs_count;
udpt.free_ccbs_count = dpt->free_ccbs_count;
udpt.waiting_ccbs_count = dpt->waiting_ccbs_count;
udpt.submitted_ccbs_count = dpt->submitted_ccbs_count;
udpt.completed_ccbs_count = dpt->completed_ccbs_count;
udpt.queue_status = dpt->queue_status;
udpt.free_lock = dpt->free_lock;
udpt.waiting_lock = dpt->waiting_lock;
udpt.submitted_lock = dpt->submitted_lock;
udpt.completed_lock = dpt->completed_lock;
udpt.commands_processed = dpt->commands_processed;
udpt.lost_interrupts = dpt->lost_interrupts;
udpt.channels = dpt->channels;
udpt.max_id = dpt->max_id;
udpt.max_lun = dpt->max_lun;
udpt.io_base = dpt->io_base;
udpt.v_membase = (u_int8_t *) dpt->v_membase;
udpt.p_membase = (u_int8_t *) dpt->p_membase;
udpt.irq = dpt->irq;
udpt.dma_channel = dpt->dma_channel;
udpt.board_data = dpt->board_data;
udpt.EATA_revision = dpt->EATA_revision;
udpt.bustype = dpt->bustype;
udpt.state = dpt->state;
udpt.primary = dpt->primary;
udpt.more_support = dpt->more_support;
udpt.immediate_support = dpt->immediate_support;
udpt.broken_INQUIRY = dpt->broken_INQUIRY;
udpt.spare2 = dpt->spare2;
for (ndx = 0; ndx < MAX_CHANNELS; ndx++) {
udpt.resetlevel[ndx] = dpt->resetlevel[ndx];
udpt.hostid[ndx] = dpt->hostid[ndx];
}
udpt.last_ccb = dpt->last_ccb;
udpt.cplen = dpt->cplen;
udpt.cppadlen = dpt->cppadlen;
udpt.queuesize = dpt->queuesize;
udpt.sgsize = dpt->sgsize;
udpt.cache_type = dpt->cache_type;
udpt.cache_size = dpt->cache_size;
(void) memcpy(cmdarg, (char *) &udpt, sizeof(dpt_user_softc_t));
return (0);
case SDI_SEND:
case DPT_IOCTL_SEND:
eata_pass_thru = (eata_pt_t *) cmdarg;
if ((eata_pass_thru->eataID[0] != 'E')
|| (eata_pass_thru->eataID[1] != 'A')
|| (eata_pass_thru->eataID[2] != 'T')
|| (eata_pass_thru->eataID[3] != 'A')) {
return (EFAULT);
}
switch (eata_pass_thru->command) {
case DPT_SIGNATURE:
return (copyout((char *) &dpt_sig,
(caddr_t *) eata_pass_thru->command_buffer,
sizeof(dpt_sig)));
case DPT_NUMCTRLS:
return (copyout((char *) &dpt_controllers_present,
(caddr_t *) eata_pass_thru->command_buffer,
sizeof(dpt_controllers_present)));
case DPT_CTRLINFO:
{
dpt_compat_ha_t compat_softc;
int ndx;
compat_softc.ha_state = dpt->state; /* Different Meaning! */
for (ndx = 0; ndx < MAX_CHANNELS; ndx++)
compat_softc.ha_id[ndx] = dpt->hostid[ndx];
compat_softc.ha_vect = dpt->irq;
compat_softc.ha_base = BaseRegister(dpt);
compat_softc.ha_max_jobs = dpt->total_ccbs_count;
compat_softc.ha_cache = dpt->cache_type;
compat_softc.ha_cachesize = dpt->cache_size;
compat_softc.ha_nbus = dpt->dma_channel + 1;
compat_softc.ha_ntargets = dpt->max_id + 1;
compat_softc.ha_nluns = dpt->max_lun + 1;
compat_softc.ha_tshift = (dpt->max_id == 7) ? 3 : 4;
compat_softc.ha_bshift = 2;
compat_softc.ha_npend = dpt->submitted_ccbs_count;
compat_softc.ha_active_jobs = dpt->waiting_ccbs_count;
strncpy(compat_softc.ha_fw_version,
dpt->board_data.firmware, 4);
compat_softc.ha_ccb = NULL;
compat_softc.ha_cblist = NULL;
compat_softc.ha_dev = NULL;
compat_softc.ha_StPkt_lock = NULL;
compat_softc.ha_ccb_lock = NULL;
compat_softc.ha_LuQWaiting = NULL;
compat_softc.ha_QWait_lock = NULL;
compat_softc.ha_QWait_opri = NULL;
return (copyout((char *) &compat_softc,
(caddr_t *) eata_pass_thru->command_buffer,
sizeof(dpt_compat_ha_t)));
}
break;
case DPT_SYSINFO:
return (copyout((char *) &dpt_sysinfo,
(caddr_t *) eata_pass_thru->command_buffer,
sizeof(dpt_sysinfo)));
case EATAUSRCMD:
printf("%d\n", __LINE__);
result = dpt_user_cmd(dpt, eata_pass_thru, cmdarg, minor_no);
printf("%d\n", __LINE__);
return (result);
case DPT_BLINKLED:
result = dpt_blinking_led(dpt);
return (copyout((caddr_t) & result,
(caddr_t *) eata_pass_thru->command_buffer,
sizeof(result)));
default:
printf("dpt%d: Invalid (%x) pass-throu command\n",
dpt->unit, eata_pass_thru->command);
result = EINVAL;
}
default:
printf("dpt%d: Invalid (%x) IOCTL\n", dpt->unit, cmd);
return (EINVAL);
}
return (result);
}
static dpt_devsw_installed = 0;
static void
dpt_drvinit(void *unused)
{
dev_t dev;
if (!dpt_devsw_installed) {
printf("DPT: RAID Manager driver, Version %d.%d.%d\n",
DPT_CTL_RELEASE, DPT_CTL_VERSION, DPT_CTL_PATCH);
/* Add the I/O (data) channel */
dev = makedev(CDEV_MAJOR, 0);
cdevsw_add(&dev, &dpt_cdevsw, NULL);
/* Add the Control (IOCTL) channel */
dev = makedev(CDEV_MAJOR, SCSI_CONTROL_MASK);
cdevsw_add(&dev, &dpt_cdevsw, NULL);
dpt_devsw_installed = 1;
}
dpt_get_sysinfo();
}
SYSINIT(dpt_dev, SI_SUB_DRIVERS, SI_ORDER_MIDDLE + CDEV_MAJOR, dpt_drvinit, NULL)
/* End of the dpt_control driver */

531
sys/dev/dpt/dpt_pci.c Normal file
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@ -0,0 +1,531 @@
/*
* Copyright (c) 1997 by Simon Shapiro
* All Rights Reserved
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
/*
* dptpci.c: Pseudo device drivers for DPT on PCI on FreeBSD
*
* caveats: We may need an eisa and an isa files too
*/
#ident "$Id: dpt_pci.c,v 1.10 1998/01/21 04:38:47 ShimonR Exp $"
#include "opt_dpt.h"
#include <pci.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/buf.h>
#include <sys/proc.h>
#include <sys/kernel.h>
#include <scsi/scsi_all.h>
#include <scsi/scsi_message.h>
#include <scsi/scsiconf.h>
#include <pci/pcireg.h>
#include <sys/queue.h>
#include <pci/pcivar.h>
#include <sys/dpt.h>
#include <pci/dpt_pci.h>
#include <machine/clock.h>
#include <vm/vm.h>
#include <vm/vm_param.h>
#include <vm/pmap.h>
#define PCI_BASEADR0 PCI_MAP_REG_START /* I/O Address */
#define PCI_BASEADR1 PCI_MAP_REG_START + 4 /* Mem I/O Address */
#define ISA_PRIMARY_WD_ADDRESS 0x1f8
/* Global variables */
int dpt_controllers_present = 0;
/* Function Prototypes */
char *dpt_pci_probe(pcici_t tag, pcidi_t type);
void dpt_pci_attach(pcici_t config_id, int unit);
int dpt_pci_shutdown(int foo, int bar);
extern struct cdevsw dpt_cdevsw;
static struct pci_device dpt_pci_driver =
{
"dpt",
dpt_pci_probe,
dpt_pci_attach,
&dpt_unit,
dpt_pci_shutdown
};
DATA_SET(pcidevice_set, dpt_pci_driver);
/*
* Probe the PCI device.
* Some of this work will have to be duplicated in _attach
* because we do not know for sure how the two relate.
*/
char *
dpt_pci_probe(pcici_t tag, pcidi_t type)
{
static char silly_message[64];
static int already_announced = 0;
u_int32_t dpt_id;
u_int32_t command;
u_int32_t class;
#define pci_device tag.cfg2.port
#define pci_bus tag.cfg2.forward
#define pci_index tag.cfg2.enable
#ifndef PCI_COMMAND_MASTER_ENABLE
#define PCI_COMMAND_MASTER_ENABLE 0x00000004
#endif
#ifndef PCI_SUBCLASS_MASS_STORAGE_SCSI
#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00000000
#endif
if ( !already_announced ) {
printf("DPT: PCI SCSI HBA Driver, version %d.%d.%d\n",
DPT_RELEASE, DPT_VERSION, DPT_PATCH);
++already_announced;
}
if ((dpt_id = (type & 0xffff0000) >> 16) == DPT_DEVICE_ID) {
/* This one appears to belong to us, but what is it? */
class = pci_conf_read(tag, PCI_CLASS_REG);
if (((class & PCI_CLASS_MASK) == PCI_CLASS_MASS_STORAGE) &&
((class & PCI_SUBCLASS_MASK) == PCI_SUBCLASS_MASS_STORAGE_SCSI) ) {
/* It is a SCSI storage device. How do talk to it? */
command = pci_conf_read(tag, PCI_COMMAND_STATUS_REG);
#ifdef DPT_ALLOW_MEMIO
if ( ((command & PCI_COMMAND_IO_ENABLE) == 0)
&& ((command & PCI_COMMAND_MEM_ENABLE) == 0) )
#else
if ( ((command & PCI_COMMAND_IO_ENABLE) == 0) )
#endif /* DPT_ALLOW_MEMIO */
{
printf("DPT: Cannot map the controller registers :-(\n");
return(NULL);
}
} else {
printf("DPT: Device is not Mass Storage, nor SCSI controller\n");
return(NULL);
}
command = pci_conf_read(tag, PCI_COMMAND_STATUS_REG);
if ( (command & PCI_COMMAND_MASTER_ENABLE) == 0 ) {
printf("DPT: Cannot be functional without BUSMASTER. :-(\n");
return (NULL);
}
#ifdef DPT_DEBUG_PCI
printf("DPT: Controller is %s mapable\n",
(command & PCI_COMMAND_MEM_ENABLE)
? "MEMORY"
: ((command & PCI_COMMAND_IO_ENABLE)
? "I/O"
: "NOT"));
#endif
return ("DPT Caching SCSI RAID Controller");
}
#if defined(DPT_DEBUG_PCI) && defined(DPT_DEBUG_WARN)
printf("DPT: Unknown Controller Type %x Found\n", dpt_id);
printf(" (class = %x, command = %x\n", class, command);
#endif
return (NULL);
}
void
dpt_pci_attach(pcici_t config_id, int unit)
{
int ospl;
int result;
int ndx;
vm_offset_t vaddr;
vm_offset_t paddr;
u_int16_t io_base;
u_int32_t command;
u_int32_t data;
dpt_conf_t *config;
dpt_softc_t *dpt;
if (dpt_controllers_present >= DPT_MAX_ADAPTERS) {
printf("dpt%d: More than %d Adapters found! Adapter rejected\n",
unit, DPT_MAX_ADAPTERS);
return;
}
if ((dpt = (dpt_softc_t *) malloc(sizeof(dpt_softc_t), M_DEVBUF, M_NOWAIT))
== NULL) {
printf("dpt%d: Failed to allocate %d bytes for a DPT softc\n",
unit, sizeof(dpt_softc_t));
return;
}
/*
* Initialize the queues. See dpt.h for details. We do this here,
* as we may get hit with interrupts at any moment and we want to
* have a minimal structure in place to handle them. We also want to
* register interrupts correctly. To do so, we need a valid dpt
* structure. To have that, we need this minimal setup here.
*/
bzero(dpt, sizeof(dpt_softc_t));
TAILQ_INIT(&dpt->free_ccbs);
TAILQ_INIT(&dpt->waiting_ccbs);
TAILQ_INIT(&dpt->submitted_ccbs);
TAILQ_INIT(&dpt->completed_ccbs);
if (TAILQ_EMPTY(&dpt_softc_list)) {
TAILQ_INIT(&dpt_softc_list);
}
TAILQ_INSERT_TAIL(&dpt_softc_list, dpt, links);
dpt->queue_status = DPT_QUEUES_NONE_ACTIVE;
dpt->commands_processed = 0;
#ifdef DPT_MEASURE_PERFORMANCE
/* Zero out all command counters */
bzero((void *)&dpt->performance, sizeof(dpt_perf_t));
for ( ndx = 0; ndx < 256; ndx ++ )
dpt->performance.min_command_time[ndx] = BIG_ENOUGH;
dpt->performance.min_intr_time = BIG_ENOUGH;
dpt->performance.min_waiting_time = BIG_ENOUGH;
dpt->performance.min_submit_time = BIG_ENOUGH;
dpt->performance.min_complete_time = BIG_ENOUGH;
dpt->performance.min_eata_tries = BIG_ENOUGH;
for (ndx = 0; ndx < 10; ndx++ ) {
dpt->performance.read_by_size_min_time[ndx] = BIG_ENOUGH;
dpt->performance.write_by_size_min_time[ndx] = BIG_ENOUGH;
}
#endif /* DPT_MEASURE_PERFORMANCE */
dpt->unit = unit;
dpt->handle_interrupts = 0; /*
* Do not set to 1 until all
* initialization is done
*/
dpt->v_membase = NULL;
dpt->p_membase = NULL;
io_base = 0;
vaddr = 0;
paddr = 0;
command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
#ifdef DPT_ALLOW_MEMIO
if ( (command & PCI_COMMAND_MEM_ENABLE) == 0 ) {
#ifdef DPT_DEBUG_PCI
printf("dpt%d: Cannot be memory mapped\n", unit);
#endif
force_io:
if ((command & PCI_COMMAND_IO_ENABLE) == 0 ) {
printf("dpt%d: Cannot be I/O mapped either :-(\n", unit);
free(dpt, M_DEVBUF);
return;
} else {
data = pci_conf_read(config_id, PCI_MAP_REG_START);
if ( pci_map_port(config_id, PCI_MAP_REG_START, &io_base) == 0 ) {
#ifdef DPT_DEBUG_ERROR
printf("dpt%d: Failed to map as I/O :-(\n", unit);
#endif
free(dpt, M_DEVBUF);
return;
} else {
dpt->io_base = io_base + 0x10;
#ifdef DPT_DEBUG_PCI
printf("dpt%d: Mapped registers to I/O space, "
"starting at %x\n",
dpt->unit, dpt->io_base);
#endif
}
}
} else {
if ( pci_map_mem(config_id, PCI_MAP_REG_START + 4, &vaddr,
&paddr) == 0 ) {
#ifdef DPT_DEBUG_ERROR
printf("dpt%d: Failed to map as MEMORY.\n"
" Attemting to force I/O mapping\n", unit);
#endif
goto force_io;
} else {
dpt->v_membase = (volatile u_int8_t *)(vaddr + 0x10);
dpt->p_membase = (volatile u_int8_t *)(paddr + 0x10);
#ifdef DPT_DEBUG_PCI
printf("dpt%d: Mapped registers to MEMORY space, "
"starting at %x/%x\n",
dpt->unit, dpt->v_membase, dpt->p_membase);
#endif
}
}
#else /* !DPT_ALLOW_MEMIO */
data = pci_conf_read(config_id, PCI_MAP_REG_START);
if ((command & PCI_COMMAND_IO_ENABLE) == 0 ) {
printf("dpt%d: Registers cannot be I/O mapped :-(\n", unit);
free(dpt, M_DEVBUF);
return;
} else {
if ( pci_map_port(config_id, PCI_MAP_REG_START, &io_base) == 0 ) {
#ifdef DPT_DEBUG_ERROR
printf("dpt%d: Failed to map registers as I/O :-(\n", unit);
#endif
free(dpt, M_DEVBUF);
return;
} else {
dpt->io_base = io_base + 0x10;
#ifdef DPT_DEBUG_PCI
printf("dpt%d: Mapped registers to I/O space, starting at %x\n",
dpt->unit, dpt->io_base);
#endif
}
}
#endif /* !DPT_ALLOW_MEMIO */
if (pci_map_int(config_id, dpt_intr, (void *)dpt, &cam_imask) == 0) {
#ifdef DPT_DEBUG_WARN
printf("dpt%d: Failed to map interrupt :-(\n", unit);
#endif
free(dpt, M_DEVBUF);
return;
}
/* If the DPT is mapped as an IDE controller, let it be IDE controller */
if (io_base == (ISA_PRIMARY_WD_ADDRESS)) {
#ifdef DPT_DEBUG_WARN
printf("dpt%d: Mapped as an IDE controller. "
"Disabling SCSI setup\n", unit);
#endif
free(dpt, M_DEVBUF);
return;
} else {
if ((config = dpt_get_conf(dpt, 0xc1, 7,
sizeof(dpt_conf_t), 1)) == NULL) {
#ifdef DPT_DEBUG_ERROR
printf("dpt%d: Failed to get board configuration (%x)\n",
unit, BaseRegister(dpt));
#endif
free(dpt, M_DEVBUF);
return;
}
}
dpt->max_id = config->MAX_ID;
dpt->max_lun = config->MAX_LUN;
dpt->irq = config->IRQ;
dpt->channels = config->MAX_CHAN;
dpt->dma_channel = (8 - config->DMA_channel) & 7;
#ifdef DPT_DEBUG_SETUP
printf("dpt%d: max_id = %d, max_chan = %d, max_lun = %d\n",
dpt->unit, dpt->max_id, dpt->channels, dpt->max_lun);
#endif
if (result = dpt_setup(dpt, config)) {
free(config, M_TEMP);
free(dpt, M_DEVBUF);
printf("dpt%d: dpt_setup failed (%d). Driver Disabled :-(\n",
dpt->unit, result);
} else {
/* clean up the informational data, and display */
char clean_vendor[9];
char clean_model[17];
char clean_firmware[5];
char clean_protocol[5];
char clean_other[7];
int ndx;
strncpy(clean_other, dpt->board_data.otherData, 8);
clean_other[6] = '\0';
for (ndx = 5; ndx >= 0; ndx--) {
if (clean_other[ndx] == ' ')
clean_other[ndx] = '\0';
else
break;
}
strncpy(dpt->board_data.otherData, clean_other, 6);
strncpy(clean_vendor, dpt->board_data.vendor, 8);
clean_vendor[8] = '\0';
for (ndx = 7; ndx >= 0; ndx--) {
if (clean_vendor[ndx] == ' ')
clean_vendor[ndx] = '\0';
else
break;
}
strncpy(dpt->board_data.vendor, clean_vendor, 8);
strncpy(clean_model, dpt->board_data.modelNum, 16);
clean_model[16] = '\0';
for (ndx = 15; ndx >= 0; ndx--) {
if (clean_model[ndx] == ' ')
clean_model[ndx] = '\0';
else
break;
}
strncpy(dpt->board_data.modelNum, clean_model, 16);
strncpy(clean_firmware, dpt->board_data.firmware, 4);
clean_firmware[4] = '\0';
for (ndx = 3; ndx >= 0; ndx--) {
if (clean_firmware[ndx] == ' ')
clean_firmware[ndx] = '\0';
else
break;
}
strncpy(dpt->board_data.firmware, clean_firmware, 4);
strncpy(clean_protocol, dpt->board_data.protocol, 4);
clean_protocol[4] = '\0';
for (ndx = 3; ndx >= 0; ndx--) {
if (clean_protocol[ndx] == ' ')
clean_protocol[ndx] = '\0';
else
break;
}
strncpy(dpt->board_data.protocol, clean_protocol, 4);
dpt_detect_cache(dpt);
printf("dpt%d: %s type %x, model %s firmware %s, Protocol %s \n"
" on port %x with %s cache. LED = %s\n",
dpt->unit, clean_vendor, dpt->board_data.deviceType,
clean_model, clean_firmware, clean_protocol, dpt->io_base,
(dpt->cache_type == DPT_NO_CACHE)
? "Disabled"
: (dpt->cache_type == DPT_CACHE_WRITETHROUGH)
? "Write-Through"
: "Write-Back",
i2bin(dpt_blinking_led(dpt), 8));
printf("dpt%d: Enabled Options:\n", dpt->unit);
#ifdef DPT_LOST_IRQ
printf(" Recover Lost Interrupts\n");
#endif
#ifdef DPT_VERIFY_HINTR
printf(" Verify Lost Transactions\n");
#endif
#ifdef DPT_RESTRICTED_FREELIST
printf(" Restrict the Freelist Size\n");
#endif
#ifdef DPT_MEASURE_PERFORMANCE
printf(" Collect Metrics\n");
#endif
#ifdef DPT_FREELIST_IS_STACK
printf(" Optimize CPU Cache\n");
#endif
#ifdef DPT_HANDLE_TIMEOUTS
printf(" Handle Timeouts\n");
#endif
#ifdef DPT_ALLOW_MEMIO
printf(" Allow I/O to be Memeory Mapped\n");
#endif
#ifdef DPT_HINTR_CHECK_SOFTC
printf(" Validate SoftC at Interrupt\n");
#endif
/* register shutdown handlers */
result = at_shutdown((bootlist_fn)dpt_shutdown, (void *)dpt,
SHUTDOWN_POST_SYNC);
switch ( result ) {
case 0:
#ifdef DPT_DEBUG_SHUTDOWN
printf("dpt%d: Shutdown handler registered\n", dpt->unit);
#endif
break;
default:
#ifdef DPT_DEBUG_WARN
printf("dpt%d: Failed to register shutdown handler (%d)\n",
dpt->unit, result);
#endif
break;
}
/* Attach SCSI devices */
dpt_attach(dpt);
++dpt_controllers_present;
/*
* Now we create the DEVFS entry.
* This would be normally done from dpt_control.c,
* But since it appears to be called before we do here,
* We never get the entries made.
*/
#ifdef DEVFS
dpt->devfs_data_token = devfs_add_devswf(&dpt_cdevsw, dpt->unit, DV_CHR,
UID_ROOT, GID_WHEEL, 0600,
"dpt%d", dpt->unit);
dpt->devfs_ctl_token = devfs_add_devswf(&dpt_cdevsw,
dpt->unit | SCSI_CONTROL_MASK,
DV_CHR,
UID_ROOT, GID_WHEEL, 0600,
"dpt%d.ctl", dpt->unit);
#endif
}
}
int
dpt_pci_shutdown(int foo, int bar)
{
#ifdef DPT_DEBUG_WARN
printf("dpt_pci_shutdown(%x, %x)\n", foo, bar);
#endif
return (0);
}
/* End of the DPT PCI part of the driver */
/*
* Hello emacs, these are the
* Local Variables:
* c-indent-level: 8
* c-continued-statement-offset: 8
* c-continued-brace-offset: 0
* c-brace-offset: -8
* c-brace-imaginary-offset: 0
* c-argdecl-indent: 8
* c-label-offset: -8
* c++-hanging-braces: 1
* c++-access-specifier-offset: -8
* c++-empty-arglist-indent: 8
* c++-friend-offset: 0
* End:
*/

207
sys/dev/dpt/dpt_pci.h Normal file
View file

@ -0,0 +1,207 @@
/*
* Copyright (c) 1997 by Simon Shapiro
* All Rights Reserved
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#ident "$Id: dpt_pci.h,v 1.3 1997/10/02 04:25:30 ShimonR Exp $"
#define DPT_VENDOR_ID 0x00001044
#define DPT_DEVICE_ID 0x0000a400
/* The following are taken, shamelessly from Linux include/linux/pci.h */
/*
* Under PCI, each device has 256 bytes of configuration address space,
* of which the first 64 bytes are standardized as follows:
*/
#define PCI_VENDOR_ID 0x00 /* 16 bits */
#define PCI_DEVICE_ID 0x02 /* 16 bits */
#define PCI_COMMAND 0x04 /* 16 bits */
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
#define PCI_STATUS 0x06 /* 16 bits */
#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
#define PCI_STATUS_UDF 0x40 /* Support User Definable Features */
#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
#ifndef PCI_STATUS_DEVSEL_MASK
#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
#define PCI_STATUS_DEVSEL_FAST 0x000
#define PCI_STATUS_DEVSEL_MEDIUM 0x200
#define PCI_STATUS_DEVSEL_SLOW 0x400
#endif
#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
* revision */
#define PCI_REVISION_ID 0x08 /* Revision ID */
#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE 0x0a /* Device class */
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
#define PCI_HEADER_TYPE 0x0e /* 8 bits */
#define PCI_BIST 0x0f /* 8 bits */
#define PCI_BIST_CODE_MASK 0x0f /* Return result */
#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
/*
* Base addresses specify locations in memory or I/O space.
* Decoded size can be determined by writing a value of
* 0xffffffff to the register, and reading it back. Only
* 1 bits are decoded.
*/
#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits */
#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits */
#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
#define PCI_BASE_ADDRESS_SPACE_IO 0x01
#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M */
#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
#define PCI_BASE_ADDRESS_MEM_MASK (~0x0f)
#define PCI_BASE_ADDRESS_IO_MASK (~0x03)
/* bit 1 is reserved if address_space = 1 */
#define PCI_CARDBUS_CIS 0x28
#define PCI_SUBSYSTEM_ID 0x2c
#define PCI_SUBSYSTEM_VENDOR_ID 0x2e
#define PCI_ROM_ADDRESS 0x30 /* 32 bits */
#define PCI_ROM_ADDRESS_ENABLE 0x01 /* Write 1 to enable ROM, bits 31..11
* are address, 10..2 are reserved */
/* 0x34-0x3b are reserved */
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
#define PCI_MIN_GNT 0x3e /* 8 bits */
#define PCI_MAX_LAT 0x3f /* 8 bits */
#define PCI_CLASS_NOT_DEFINED 0x0000
#define PCI_CLASS_NOT_DEFINED_VGA 0x0001
#define PCI_BASE_CLASS_STORAGE 0x01
#define PCI_CLASS_STORAGE_SCSI 0x0100
#define PCI_CLASS_STORAGE_IDE 0x0101
#define PCI_CLASS_STORAGE_FLOPPY 0x0102
#define PCI_CLASS_STORAGE_IPI 0x0103
#define PCI_CLASS_STORAGE_RAID 0x0104
#define PCI_CLASS_STORAGE_OTHER 0x0180
#define PCI_BASE_CLASS_NETWORK 0x02
#define PCI_CLASS_NETWORK_ETHERNET 0x0200
#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201
#define PCI_CLASS_NETWORK_FDDI 0x0202
#define PCI_CLASS_NETWORK_ATM 0x0203
#define PCI_CLASS_NETWORK_OTHER 0x0280
#define PCI_BASE_CLASS_DISPLAY 0x03
#define PCI_CLASS_DISPLAY_VGA 0x0300
#define PCI_CLASS_DISPLAY_XGA 0x0301
#define PCI_CLASS_DISPLAY_OTHER 0x0380
#define PCI_BASE_CLASS_MULTIMEDIA 0x04
#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
#define PCI_BASE_CLASS_MEMORY 0x05
#define PCI_CLASS_MEMORY_RAM 0x0500
#define PCI_CLASS_MEMORY_FLASH 0x0501
#define PCI_CLASS_MEMORY_OTHER 0x0580
#define PCI_BASE_CLASS_BRIDGE 0x06
#define PCI_CLASS_BRIDGE_HOST 0x0600
#define PCI_CLASS_BRIDGE_ISA 0x0601
#define PCI_CLASS_BRIDGE_EISA 0x0602
#define PCI_CLASS_BRIDGE_MC 0x0603
#define PCI_CLASS_BRIDGE_PCI 0x0604
#define PCI_CLASS_BRIDGE_PCMCIA 0x0605
#define PCI_CLASS_BRIDGE_NUBUS 0x0606
#define PCI_CLASS_BRIDGE_CARDBUS 0x0607
#define PCI_CLASS_BRIDGE_OTHER 0x0680
#define PCI_BASE_CLASS_COMMUNICATION 0x07
#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
#define PCI_CLASS_COMMUNICATION_OTHER 0x0780
#define PCI_BASE_CLASS_SYSTEM 0x08
#define PCI_CLASS_SYSTEM_PIC 0x0800
#define PCI_CLASS_SYSTEM_DMA 0x0801
#define PCI_CLASS_SYSTEM_TIMER 0x0802
#define PCI_CLASS_SYSTEM_RTC 0x0803
#define PCI_CLASS_SYSTEM_OTHER 0x0880
#define PCI_BASE_CLASS_INPUT 0x09
#define PCI_CLASS_INPUT_KEYBOARD 0x0900
#define PCI_CLASS_INPUT_PEN 0x0901
#define PCI_CLASS_INPUT_MOUSE 0x0902
#define PCI_CLASS_INPUT_OTHER 0x0980
#define PCI_BASE_CLASS_DOCKING 0x0a
#define PCI_CLASS_DOCKING_GENERIC 0x0a00
#define PCI_CLASS_DOCKING_OTHER 0x0a01
#define PCI_BASE_CLASS_PROCESSOR 0x0b
#define PCI_CLASS_PROCESSOR_386 0x0b00
#define PCI_CLASS_PROCESSOR_486 0x0b01
#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02
#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10
#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
#define PCI_CLASS_PROCESSOR_CO 0x0b40
#define PCI_BASE_CLASS_SERIAL 0x0c
#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00
#define PCI_CLASS_SERIAL_ACCESS 0x0c01
#define PCI_CLASS_SERIAL_SSA 0x0c02
#define PCI_CLASS_SERIAL_USB 0x0c03
#define PCI_CLASS_SERIAL_FIBER 0x0c04
#define PCI_CLASS_OTHERS 0xff

3700
sys/dev/dpt/dpt_scsi.c Normal file
View file

File diff suppressed because it is too large Load diff

5
sys/i386/conf/files.i386
View file

@ -1,7 +1,7 @@
# This file tells config what files go into building a kernel,
# files marked standard are always included.
#
# $Id: files.i386,v 1.185 1998/01/15 07:30:54 gibbs Exp $
# $Id: files.i386,v 1.186 1998/01/16 22:13:00 pst Exp $
#
# The long compile-with and dependency lines are required because of
# limitations in config: backslash-newline doesn't work in strings, and
@ -313,3 +313,6 @@ gnu/i386/fpemul/wm_sqrt.s optional gpl_math_emulate
gnu/i386/isa/dgb.c optional dgb device-driver
gnu/i386/isa/sound/awe_wave.c optional awe device-driver
pci/ide_pci.c optional wd device-driver
dev/dpt/dpt_control.c optional dpt device-driver
dev/dpt/dpt_scsi.c optional dpt device-driver
pci/dpt_pci.c optional dpt device-driver

3
sys/i386/conf/majors.i386
View file

@ -1,4 +1,4 @@
$Id: majors.i386,v 1.23 1997/12/09 10:51:11 jamil Exp $
$Id: majors.i386,v 1.24 1998/01/16 22:13:01 pst Exp $
Hopefully, this list will one day be obsoleted by DEVFS, but for now
this is the current allocation of device major numbers.
@ -127,3 +127,4 @@ chrdev name comments
85 vesa VESA support device (j_mini@efn.org)
86 alog Industrial Computer Source AIO8-P driver
87 wfd ATAPI floppy client of "ata"
88 dpt DPT RAID Controller <shimon@i-connect.net>

11
sys/i386/conf/options.i386
View file

@ -1,4 +1,4 @@
# $Id: options.i386,v 1.66 1997/12/28 13:36:00 phk Exp $
# $Id: options.i386,v 1.67 1998/01/25 04:37:47 eivind Exp $
BOUNCEPAGES opt_bounce.h
USER_LDT
@ -114,3 +114,12 @@ PCVT_SCANSET opt_pcvt.h
PCVT_SCREENSAVER opt_pcvt.h
PCVT_USEKBDSEC opt_pcvt.h
PCVT_VT220KEYB opt_pcvt.h
DPT_VERIFY_HINTR opt_dpt.h
DPT_USE_SINTR opt_dpt.h
DPT_RESTRICTED_FREELIST opt_dpt.h
DPT_MEASURE_PERFORMANCE opt_dpt.h
DPT_FREELIST_IS_STACK opt_dpt.h
DPT_HANDLE_TIMEOUTS opt_dpt.h
DPT_TIMEOUT_FACTOR opt_dpt.h
DPT_INTR_DELAY opt_dpt.h
DPT_LOST_IRQ opt_dpt.h

5
sys/i386/i386/userconfig.c
View file

@ -46,7 +46,7 @@
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
** $Id: userconfig.c,v 1.99 1997/12/28 05:20:59 bde Exp $
** $Id: userconfig.c,v 1.100 1998/01/21 19:23:33 jkh Exp $
**/
/**
@ -227,6 +227,7 @@ static DEVCLASS_INFO devclass_names[] = {
static DEV_INFO device_info[] = {
/*---Name----- ---Description---------------------------------------------- */
{"dpt", "DPT SCSI RAID Controller", FLG_IMMUTABLE, CLS_STORAGE},
{"bt", "Buslogic SCSI controller", 0, CLS_STORAGE},
{"ahc", "Adaptec 274x/284x/294x SCSI controller", 0, CLS_STORAGE},
{"ahb", "Adaptec 174x SCSI controller", 0, CLS_STORAGE},
@ -2372,7 +2373,7 @@ visuserconfig(void)
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: userconfig.c,v 1.99 1997/12/28 05:20:59 bde Exp $
* $Id: userconfig.c,v 1.100 1998/01/21 19:23:33 jkh Exp $
*/
#include "scbus.h"

531
sys/pci/dpt_pci.c Normal file
View file

@ -0,0 +1,531 @@
/*
* Copyright (c) 1997 by Simon Shapiro
* All Rights Reserved
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
/*
* dptpci.c: Pseudo device drivers for DPT on PCI on FreeBSD
*
* caveats: We may need an eisa and an isa files too
*/
#ident "$Id: dpt_pci.c,v 1.10 1998/01/21 04:38:47 ShimonR Exp $"
#include "opt_dpt.h"
#include <pci.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/buf.h>
#include <sys/proc.h>
#include <sys/kernel.h>
#include <scsi/scsi_all.h>
#include <scsi/scsi_message.h>
#include <scsi/scsiconf.h>
#include <pci/pcireg.h>
#include <sys/queue.h>
#include <pci/pcivar.h>
#include <sys/dpt.h>
#include <pci/dpt_pci.h>
#include <machine/clock.h>
#include <vm/vm.h>
#include <vm/vm_param.h>
#include <vm/pmap.h>
#define PCI_BASEADR0 PCI_MAP_REG_START /* I/O Address */
#define PCI_BASEADR1 PCI_MAP_REG_START + 4 /* Mem I/O Address */
#define ISA_PRIMARY_WD_ADDRESS 0x1f8
/* Global variables */
int dpt_controllers_present = 0;
/* Function Prototypes */
char *dpt_pci_probe(pcici_t tag, pcidi_t type);
void dpt_pci_attach(pcici_t config_id, int unit);
int dpt_pci_shutdown(int foo, int bar);
extern struct cdevsw dpt_cdevsw;
static struct pci_device dpt_pci_driver =
{
"dpt",
dpt_pci_probe,
dpt_pci_attach,
&dpt_unit,
dpt_pci_shutdown
};
DATA_SET(pcidevice_set, dpt_pci_driver);
/*
* Probe the PCI device.
* Some of this work will have to be duplicated in _attach
* because we do not know for sure how the two relate.
*/
char *
dpt_pci_probe(pcici_t tag, pcidi_t type)
{
static char silly_message[64];
static int already_announced = 0;
u_int32_t dpt_id;
u_int32_t command;
u_int32_t class;
#define pci_device tag.cfg2.port
#define pci_bus tag.cfg2.forward
#define pci_index tag.cfg2.enable
#ifndef PCI_COMMAND_MASTER_ENABLE
#define PCI_COMMAND_MASTER_ENABLE 0x00000004
#endif
#ifndef PCI_SUBCLASS_MASS_STORAGE_SCSI
#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00000000
#endif
if ( !already_announced ) {
printf("DPT: PCI SCSI HBA Driver, version %d.%d.%d\n",
DPT_RELEASE, DPT_VERSION, DPT_PATCH);
++already_announced;
}
if ((dpt_id = (type & 0xffff0000) >> 16) == DPT_DEVICE_ID) {
/* This one appears to belong to us, but what is it? */
class = pci_conf_read(tag, PCI_CLASS_REG);
if (((class & PCI_CLASS_MASK) == PCI_CLASS_MASS_STORAGE) &&
((class & PCI_SUBCLASS_MASK) == PCI_SUBCLASS_MASS_STORAGE_SCSI) ) {
/* It is a SCSI storage device. How do talk to it? */
command = pci_conf_read(tag, PCI_COMMAND_STATUS_REG);
#ifdef DPT_ALLOW_MEMIO
if ( ((command & PCI_COMMAND_IO_ENABLE) == 0)
&& ((command & PCI_COMMAND_MEM_ENABLE) == 0) )
#else
if ( ((command & PCI_COMMAND_IO_ENABLE) == 0) )
#endif /* DPT_ALLOW_MEMIO */
{
printf("DPT: Cannot map the controller registers :-(\n");
return(NULL);
}
} else {
printf("DPT: Device is not Mass Storage, nor SCSI controller\n");
return(NULL);
}
command = pci_conf_read(tag, PCI_COMMAND_STATUS_REG);
if ( (command & PCI_COMMAND_MASTER_ENABLE) == 0 ) {
printf("DPT: Cannot be functional without BUSMASTER. :-(\n");
return (NULL);
}
#ifdef DPT_DEBUG_PCI
printf("DPT: Controller is %s mapable\n",
(command & PCI_COMMAND_MEM_ENABLE)
? "MEMORY"
: ((command & PCI_COMMAND_IO_ENABLE)
? "I/O"
: "NOT"));
#endif
return ("DPT Caching SCSI RAID Controller");
}
#if defined(DPT_DEBUG_PCI) && defined(DPT_DEBUG_WARN)
printf("DPT: Unknown Controller Type %x Found\n", dpt_id);
printf(" (class = %x, command = %x\n", class, command);
#endif
return (NULL);
}
void
dpt_pci_attach(pcici_t config_id, int unit)
{
int ospl;
int result;
int ndx;
vm_offset_t vaddr;
vm_offset_t paddr;
u_int16_t io_base;
u_int32_t command;
u_int32_t data;
dpt_conf_t *config;
dpt_softc_t *dpt;
if (dpt_controllers_present >= DPT_MAX_ADAPTERS) {
printf("dpt%d: More than %d Adapters found! Adapter rejected\n",
unit, DPT_MAX_ADAPTERS);
return;
}
if ((dpt = (dpt_softc_t *) malloc(sizeof(dpt_softc_t), M_DEVBUF, M_NOWAIT))
== NULL) {
printf("dpt%d: Failed to allocate %d bytes for a DPT softc\n",
unit, sizeof(dpt_softc_t));
return;
}
/*
* Initialize the queues. See dpt.h for details. We do this here,
* as we may get hit with interrupts at any moment and we want to
* have a minimal structure in place to handle them. We also want to
* register interrupts correctly. To do so, we need a valid dpt
* structure. To have that, we need this minimal setup here.
*/
bzero(dpt, sizeof(dpt_softc_t));
TAILQ_INIT(&dpt->free_ccbs);
TAILQ_INIT(&dpt->waiting_ccbs);
TAILQ_INIT(&dpt->submitted_ccbs);
TAILQ_INIT(&dpt->completed_ccbs);
if (TAILQ_EMPTY(&dpt_softc_list)) {
TAILQ_INIT(&dpt_softc_list);
}
TAILQ_INSERT_TAIL(&dpt_softc_list, dpt, links);
dpt->queue_status = DPT_QUEUES_NONE_ACTIVE;
dpt->commands_processed = 0;
#ifdef DPT_MEASURE_PERFORMANCE
/* Zero out all command counters */
bzero((void *)&dpt->performance, sizeof(dpt_perf_t));
for ( ndx = 0; ndx < 256; ndx ++ )
dpt->performance.min_command_time[ndx] = BIG_ENOUGH;
dpt->performance.min_intr_time = BIG_ENOUGH;
dpt->performance.min_waiting_time = BIG_ENOUGH;
dpt->performance.min_submit_time = BIG_ENOUGH;
dpt->performance.min_complete_time = BIG_ENOUGH;
dpt->performance.min_eata_tries = BIG_ENOUGH;
for (ndx = 0; ndx < 10; ndx++ ) {
dpt->performance.read_by_size_min_time[ndx] = BIG_ENOUGH;
dpt->performance.write_by_size_min_time[ndx] = BIG_ENOUGH;
}
#endif /* DPT_MEASURE_PERFORMANCE */
dpt->unit = unit;
dpt->handle_interrupts = 0; /*
* Do not set to 1 until all
* initialization is done
*/
dpt->v_membase = NULL;
dpt->p_membase = NULL;
io_base = 0;
vaddr = 0;
paddr = 0;
command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG);
#ifdef DPT_ALLOW_MEMIO
if ( (command & PCI_COMMAND_MEM_ENABLE) == 0 ) {
#ifdef DPT_DEBUG_PCI
printf("dpt%d: Cannot be memory mapped\n", unit);
#endif
force_io:
if ((command & PCI_COMMAND_IO_ENABLE) == 0 ) {
printf("dpt%d: Cannot be I/O mapped either :-(\n", unit);
free(dpt, M_DEVBUF);
return;
} else {
data = pci_conf_read(config_id, PCI_MAP_REG_START);
if ( pci_map_port(config_id, PCI_MAP_REG_START, &io_base) == 0 ) {
#ifdef DPT_DEBUG_ERROR
printf("dpt%d: Failed to map as I/O :-(\n", unit);
#endif
free(dpt, M_DEVBUF);
return;
} else {
dpt->io_base = io_base + 0x10;
#ifdef DPT_DEBUG_PCI
printf("dpt%d: Mapped registers to I/O space, "
"starting at %x\n",
dpt->unit, dpt->io_base);
#endif
}
}
} else {
if ( pci_map_mem(config_id, PCI_MAP_REG_START + 4, &vaddr,
&paddr) == 0 ) {
#ifdef DPT_DEBUG_ERROR
printf("dpt%d: Failed to map as MEMORY.\n"
" Attemting to force I/O mapping\n", unit);
#endif
goto force_io;
} else {
dpt->v_membase = (volatile u_int8_t *)(vaddr + 0x10);
dpt->p_membase = (volatile u_int8_t *)(paddr + 0x10);
#ifdef DPT_DEBUG_PCI
printf("dpt%d: Mapped registers to MEMORY space, "
"starting at %x/%x\n",
dpt->unit, dpt->v_membase, dpt->p_membase);
#endif
}
}
#else /* !DPT_ALLOW_MEMIO */
data = pci_conf_read(config_id, PCI_MAP_REG_START);
if ((command & PCI_COMMAND_IO_ENABLE) == 0 ) {
printf("dpt%d: Registers cannot be I/O mapped :-(\n", unit);
free(dpt, M_DEVBUF);
return;
} else {
if ( pci_map_port(config_id, PCI_MAP_REG_START, &io_base) == 0 ) {
#ifdef DPT_DEBUG_ERROR
printf("dpt%d: Failed to map registers as I/O :-(\n", unit);
#endif
free(dpt, M_DEVBUF);
return;
} else {
dpt->io_base = io_base + 0x10;
#ifdef DPT_DEBUG_PCI
printf("dpt%d: Mapped registers to I/O space, starting at %x\n",
dpt->unit, dpt->io_base);
#endif
}
}
#endif /* !DPT_ALLOW_MEMIO */
if (pci_map_int(config_id, dpt_intr, (void *)dpt, &cam_imask) == 0) {
#ifdef DPT_DEBUG_WARN
printf("dpt%d: Failed to map interrupt :-(\n", unit);
#endif
free(dpt, M_DEVBUF);
return;
}
/* If the DPT is mapped as an IDE controller, let it be IDE controller */
if (io_base == (ISA_PRIMARY_WD_ADDRESS)) {
#ifdef DPT_DEBUG_WARN
printf("dpt%d: Mapped as an IDE controller. "
"Disabling SCSI setup\n", unit);
#endif
free(dpt, M_DEVBUF);
return;
} else {
if ((config = dpt_get_conf(dpt, 0xc1, 7,
sizeof(dpt_conf_t), 1)) == NULL) {
#ifdef DPT_DEBUG_ERROR
printf("dpt%d: Failed to get board configuration (%x)\n",
unit, BaseRegister(dpt));
#endif
free(dpt, M_DEVBUF);
return;
}
}
dpt->max_id = config->MAX_ID;
dpt->max_lun = config->MAX_LUN;
dpt->irq = config->IRQ;
dpt->channels = config->MAX_CHAN;
dpt->dma_channel = (8 - config->DMA_channel) & 7;
#ifdef DPT_DEBUG_SETUP
printf("dpt%d: max_id = %d, max_chan = %d, max_lun = %d\n",
dpt->unit, dpt->max_id, dpt->channels, dpt->max_lun);
#endif
if (result = dpt_setup(dpt, config)) {
free(config, M_TEMP);
free(dpt, M_DEVBUF);
printf("dpt%d: dpt_setup failed (%d). Driver Disabled :-(\n",
dpt->unit, result);
} else {
/* clean up the informational data, and display */
char clean_vendor[9];
char clean_model[17];
char clean_firmware[5];
char clean_protocol[5];
char clean_other[7];
int ndx;
strncpy(clean_other, dpt->board_data.otherData, 8);
clean_other[6] = '\0';
for (ndx = 5; ndx >= 0; ndx--) {
if (clean_other[ndx] == ' ')
clean_other[ndx] = '\0';
else
break;
}
strncpy(dpt->board_data.otherData, clean_other, 6);
strncpy(clean_vendor, dpt->board_data.vendor, 8);
clean_vendor[8] = '\0';
for (ndx = 7; ndx >= 0; ndx--) {
if (clean_vendor[ndx] == ' ')
clean_vendor[ndx] = '\0';
else
break;
}
strncpy(dpt->board_data.vendor, clean_vendor, 8);
strncpy(clean_model, dpt->board_data.modelNum, 16);
clean_model[16] = '\0';
for (ndx = 15; ndx >= 0; ndx--) {
if (clean_model[ndx] == ' ')
clean_model[ndx] = '\0';
else
break;
}
strncpy(dpt->board_data.modelNum, clean_model, 16);
strncpy(clean_firmware, dpt->board_data.firmware, 4);
clean_firmware[4] = '\0';
for (ndx = 3; ndx >= 0; ndx--) {
if (clean_firmware[ndx] == ' ')
clean_firmware[ndx] = '\0';
else
break;
}
strncpy(dpt->board_data.firmware, clean_firmware, 4);
strncpy(clean_protocol, dpt->board_data.protocol, 4);
clean_protocol[4] = '\0';
for (ndx = 3; ndx >= 0; ndx--) {
if (clean_protocol[ndx] == ' ')
clean_protocol[ndx] = '\0';
else
break;
}
strncpy(dpt->board_data.protocol, clean_protocol, 4);
dpt_detect_cache(dpt);
printf("dpt%d: %s type %x, model %s firmware %s, Protocol %s \n"
" on port %x with %s cache. LED = %s\n",
dpt->unit, clean_vendor, dpt->board_data.deviceType,
clean_model, clean_firmware, clean_protocol, dpt->io_base,
(dpt->cache_type == DPT_NO_CACHE)
? "Disabled"
: (dpt->cache_type == DPT_CACHE_WRITETHROUGH)
? "Write-Through"
: "Write-Back",
i2bin(dpt_blinking_led(dpt), 8));
printf("dpt%d: Enabled Options:\n", dpt->unit);
#ifdef DPT_LOST_IRQ
printf(" Recover Lost Interrupts\n");
#endif
#ifdef DPT_VERIFY_HINTR
printf(" Verify Lost Transactions\n");
#endif
#ifdef DPT_RESTRICTED_FREELIST
printf(" Restrict the Freelist Size\n");
#endif
#ifdef DPT_MEASURE_PERFORMANCE
printf(" Collect Metrics\n");
#endif
#ifdef DPT_FREELIST_IS_STACK
printf(" Optimize CPU Cache\n");
#endif
#ifdef DPT_HANDLE_TIMEOUTS
printf(" Handle Timeouts\n");
#endif
#ifdef DPT_ALLOW_MEMIO
printf(" Allow I/O to be Memeory Mapped\n");
#endif
#ifdef DPT_HINTR_CHECK_SOFTC
printf(" Validate SoftC at Interrupt\n");
#endif
/* register shutdown handlers */
result = at_shutdown((bootlist_fn)dpt_shutdown, (void *)dpt,
SHUTDOWN_POST_SYNC);
switch ( result ) {
case 0:
#ifdef DPT_DEBUG_SHUTDOWN
printf("dpt%d: Shutdown handler registered\n", dpt->unit);
#endif
break;
default:
#ifdef DPT_DEBUG_WARN
printf("dpt%d: Failed to register shutdown handler (%d)\n",
dpt->unit, result);
#endif
break;
}
/* Attach SCSI devices */
dpt_attach(dpt);
++dpt_controllers_present;
/*
* Now we create the DEVFS entry.
* This would be normally done from dpt_control.c,
* But since it appears to be called before we do here,
* We never get the entries made.
*/
#ifdef DEVFS
dpt->devfs_data_token = devfs_add_devswf(&dpt_cdevsw, dpt->unit, DV_CHR,
UID_ROOT, GID_WHEEL, 0600,
"dpt%d", dpt->unit);
dpt->devfs_ctl_token = devfs_add_devswf(&dpt_cdevsw,
dpt->unit | SCSI_CONTROL_MASK,
DV_CHR,
UID_ROOT, GID_WHEEL, 0600,
"dpt%d.ctl", dpt->unit);
#endif
}
}
int
dpt_pci_shutdown(int foo, int bar)
{
#ifdef DPT_DEBUG_WARN
printf("dpt_pci_shutdown(%x, %x)\n", foo, bar);
#endif
return (0);
}
/* End of the DPT PCI part of the driver */
/*
* Hello emacs, these are the
* Local Variables:
* c-indent-level: 8
* c-continued-statement-offset: 8
* c-continued-brace-offset: 0
* c-brace-offset: -8
* c-brace-imaginary-offset: 0
* c-argdecl-indent: 8
* c-label-offset: -8
* c++-hanging-braces: 1
* c++-access-specifier-offset: -8
* c++-empty-arglist-indent: 8
* c++-friend-offset: 0
* End:
*/

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/*
* Copyright (c) 1997 by Simon Shapiro
* All Rights Reserved
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#ident "$Id: dpt_pci.h,v 1.3 1997/10/02 04:25:30 ShimonR Exp $"
#define DPT_VENDOR_ID 0x00001044
#define DPT_DEVICE_ID 0x0000a400
/* The following are taken, shamelessly from Linux include/linux/pci.h */
/*
* Under PCI, each device has 256 bytes of configuration address space,
* of which the first 64 bytes are standardized as follows:
*/
#define PCI_VENDOR_ID 0x00 /* 16 bits */
#define PCI_DEVICE_ID 0x02 /* 16 bits */
#define PCI_COMMAND 0x04 /* 16 bits */
#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
#define PCI_STATUS 0x06 /* 16 bits */
#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
#define PCI_STATUS_UDF 0x40 /* Support User Definable Features */
#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
#ifndef PCI_STATUS_DEVSEL_MASK
#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
#define PCI_STATUS_DEVSEL_FAST 0x000
#define PCI_STATUS_DEVSEL_MEDIUM 0x200
#define PCI_STATUS_DEVSEL_SLOW 0x400
#endif
#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
* revision */
#define PCI_REVISION_ID 0x08 /* Revision ID */
#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE 0x0a /* Device class */
#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
#define PCI_HEADER_TYPE 0x0e /* 8 bits */
#define PCI_BIST 0x0f /* 8 bits */
#define PCI_BIST_CODE_MASK 0x0f /* Return result */
#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
/*
* Base addresses specify locations in memory or I/O space.
* Decoded size can be determined by writing a value of
* 0xffffffff to the register, and reading it back. Only
* 1 bits are decoded.
*/
#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits */
#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits */
#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
#define PCI_BASE_ADDRESS_SPACE_IO 0x01
#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M */
#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
#define PCI_BASE_ADDRESS_MEM_MASK (~0x0f)
#define PCI_BASE_ADDRESS_IO_MASK (~0x03)
/* bit 1 is reserved if address_space = 1 */
#define PCI_CARDBUS_CIS 0x28
#define PCI_SUBSYSTEM_ID 0x2c
#define PCI_SUBSYSTEM_VENDOR_ID 0x2e
#define PCI_ROM_ADDRESS 0x30 /* 32 bits */
#define PCI_ROM_ADDRESS_ENABLE 0x01 /* Write 1 to enable ROM, bits 31..11
* are address, 10..2 are reserved */
/* 0x34-0x3b are reserved */
#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
#define PCI_MIN_GNT 0x3e /* 8 bits */
#define PCI_MAX_LAT 0x3f /* 8 bits */
#define PCI_CLASS_NOT_DEFINED 0x0000
#define PCI_CLASS_NOT_DEFINED_VGA 0x0001
#define PCI_BASE_CLASS_STORAGE 0x01
#define PCI_CLASS_STORAGE_SCSI 0x0100
#define PCI_CLASS_STORAGE_IDE 0x0101
#define PCI_CLASS_STORAGE_FLOPPY 0x0102
#define PCI_CLASS_STORAGE_IPI 0x0103
#define PCI_CLASS_STORAGE_RAID 0x0104
#define PCI_CLASS_STORAGE_OTHER 0x0180
#define PCI_BASE_CLASS_NETWORK 0x02
#define PCI_CLASS_NETWORK_ETHERNET 0x0200
#define PCI_CLASS_NETWORK_TOKEN_RING 0x0201
#define PCI_CLASS_NETWORK_FDDI 0x0202
#define PCI_CLASS_NETWORK_ATM 0x0203
#define PCI_CLASS_NETWORK_OTHER 0x0280
#define PCI_BASE_CLASS_DISPLAY 0x03
#define PCI_CLASS_DISPLAY_VGA 0x0300
#define PCI_CLASS_DISPLAY_XGA 0x0301
#define PCI_CLASS_DISPLAY_OTHER 0x0380
#define PCI_BASE_CLASS_MULTIMEDIA 0x04
#define PCI_CLASS_MULTIMEDIA_VIDEO 0x0400
#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
#define PCI_CLASS_MULTIMEDIA_OTHER 0x0480
#define PCI_BASE_CLASS_MEMORY 0x05
#define PCI_CLASS_MEMORY_RAM 0x0500
#define PCI_CLASS_MEMORY_FLASH 0x0501
#define PCI_CLASS_MEMORY_OTHER 0x0580
#define PCI_BASE_CLASS_BRIDGE 0x06
#define PCI_CLASS_BRIDGE_HOST 0x0600
#define PCI_CLASS_BRIDGE_ISA 0x0601
#define PCI_CLASS_BRIDGE_EISA 0x0602
#define PCI_CLASS_BRIDGE_MC 0x0603
#define PCI_CLASS_BRIDGE_PCI 0x0604
#define PCI_CLASS_BRIDGE_PCMCIA 0x0605
#define PCI_CLASS_BRIDGE_NUBUS 0x0606
#define PCI_CLASS_BRIDGE_CARDBUS 0x0607
#define PCI_CLASS_BRIDGE_OTHER 0x0680
#define PCI_BASE_CLASS_COMMUNICATION 0x07
#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700
#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
#define PCI_CLASS_COMMUNICATION_OTHER 0x0780
#define PCI_BASE_CLASS_SYSTEM 0x08
#define PCI_CLASS_SYSTEM_PIC 0x0800
#define PCI_CLASS_SYSTEM_DMA 0x0801
#define PCI_CLASS_SYSTEM_TIMER 0x0802
#define PCI_CLASS_SYSTEM_RTC 0x0803
#define PCI_CLASS_SYSTEM_OTHER 0x0880
#define PCI_BASE_CLASS_INPUT 0x09
#define PCI_CLASS_INPUT_KEYBOARD 0x0900
#define PCI_CLASS_INPUT_PEN 0x0901
#define PCI_CLASS_INPUT_MOUSE 0x0902
#define PCI_CLASS_INPUT_OTHER 0x0980
#define PCI_BASE_CLASS_DOCKING 0x0a
#define PCI_CLASS_DOCKING_GENERIC 0x0a00
#define PCI_CLASS_DOCKING_OTHER 0x0a01
#define PCI_BASE_CLASS_PROCESSOR 0x0b
#define PCI_CLASS_PROCESSOR_386 0x0b00
#define PCI_CLASS_PROCESSOR_486 0x0b01
#define PCI_CLASS_PROCESSOR_PENTIUM 0x0b02
#define PCI_CLASS_PROCESSOR_ALPHA 0x0b10
#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
#define PCI_CLASS_PROCESSOR_CO 0x0b40
#define PCI_BASE_CLASS_SERIAL 0x0c
#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00
#define PCI_CLASS_SERIAL_ACCESS 0x0c01
#define PCI_CLASS_SERIAL_SSA 0x0c02
#define PCI_CLASS_SERIAL_USB 0x0c03
#define PCI_CLASS_SERIAL_FIBER 0x0c04
#define PCI_CLASS_OTHERS 0xff

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