mirror of
https://github.com/freebsd/freebsd-src
synced 2024-10-08 01:20:40 +00:00
use sbuf so that lines are printed together... As aarch64 often
has SMP enabled, lines can get intermixed with other console output making these lines hard to read... Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D16689
This commit is contained in:
John-Mark Gurney
parent
381388b9c4
commit
b060c61dfd
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=338075
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@ -35,6 +35,7 @@ __FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/pcpu.h>
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#include <sys/sbuf.h>
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#include <sys/smp.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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@ -175,30 +176,34 @@ SYSINIT(idenrity_cpu, SI_SUB_SMP, SI_ORDER_ANY, identify_cpu_sysinit, NULL);
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void
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print_cpu_features(u_int cpu)
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{
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struct sbuf *sb;
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int printed;
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printf("CPU%3d: %s %s r%dp%d", cpu, cpu_desc[cpu].cpu_impl_name,
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cpu_desc[cpu].cpu_part_name, cpu_desc[cpu].cpu_variant,
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cpu_desc[cpu].cpu_revision);
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sb = sbuf_new_auto();
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sbuf_printf(sb, "CPU%3d: %s %s r%dp%d", cpu,
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cpu_desc[cpu].cpu_impl_name, cpu_desc[cpu].cpu_part_name,
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cpu_desc[cpu].cpu_variant, cpu_desc[cpu].cpu_revision);
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printf(" affinity:");
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sbuf_cat(sb, " affinity:");
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switch(cpu_aff_levels) {
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default:
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case 4:
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printf(" %2d", CPU_AFF3(cpu_desc[cpu].mpidr));
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sbuf_printf(sb, " %2d", CPU_AFF3(cpu_desc[cpu].mpidr));
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/* FALLTHROUGH */
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case 3:
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printf(" %2d", CPU_AFF2(cpu_desc[cpu].mpidr));
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sbuf_printf(sb, " %2d", CPU_AFF2(cpu_desc[cpu].mpidr));
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/* FALLTHROUGH */
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case 2:
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printf(" %2d", CPU_AFF1(cpu_desc[cpu].mpidr));
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sbuf_printf(sb, " %2d", CPU_AFF1(cpu_desc[cpu].mpidr));
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/* FALLTHROUGH */
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case 1:
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case 0: /* On UP this will be zero */
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printf(" %2d", CPU_AFF0(cpu_desc[cpu].mpidr));
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sbuf_printf(sb, " %2d", CPU_AFF0(cpu_desc[cpu].mpidr));
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break;
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}
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printf("\n");
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sbuf_finish(sb);
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printf("%s\n", sbuf_data(sb));
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sbuf_clear(sb);
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/*
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* There is a hardware errata where, if one CPU is performing a TLB
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@ -230,39 +235,39 @@ print_cpu_features(u_int cpu)
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/* AArch64 Instruction Set Attribute Register 0 */
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if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR0) != 0) {
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printed = 0;
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printf(" Instruction Set Attributes 0 = <");
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sbuf_printf(sb, " Instruction Set Attributes 0 = <");
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switch (ID_AA64ISAR0_RDM(cpu_desc[cpu].id_aa64isar0)) {
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case ID_AA64ISAR0_RDM_NONE:
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break;
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case ID_AA64ISAR0_RDM_IMPL:
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printf("%sRDM", SEP_STR);
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sbuf_printf(sb, "%sRDM", SEP_STR);
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break;
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default:
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printf("%sUnknown RDM", SEP_STR);
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sbuf_printf(sb, "%sUnknown RDM", SEP_STR);
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}
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switch (ID_AA64ISAR0_ATOMIC(cpu_desc[cpu].id_aa64isar0)) {
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case ID_AA64ISAR0_ATOMIC_NONE:
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break;
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case ID_AA64ISAR0_ATOMIC_IMPL:
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printf("%sAtomic", SEP_STR);
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sbuf_printf(sb, "%sAtomic", SEP_STR);
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break;
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default:
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printf("%sUnknown Atomic", SEP_STR);
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sbuf_printf(sb, "%sUnknown Atomic", SEP_STR);
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}
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switch (ID_AA64ISAR0_AES(cpu_desc[cpu].id_aa64isar0)) {
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case ID_AA64ISAR0_AES_NONE:
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break;
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case ID_AA64ISAR0_AES_BASE:
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printf("%sAES", SEP_STR);
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sbuf_printf(sb, "%sAES", SEP_STR);
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break;
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case ID_AA64ISAR0_AES_PMULL:
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printf("%sAES+PMULL", SEP_STR);
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sbuf_printf(sb, "%sAES+PMULL", SEP_STR);
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break;
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default:
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printf("%sUnknown AES", SEP_STR);
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sbuf_printf(sb, "%sUnknown AES", SEP_STR);
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break;
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}
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@ -270,10 +275,10 @@ print_cpu_features(u_int cpu)
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case ID_AA64ISAR0_SHA1_NONE:
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break;
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case ID_AA64ISAR0_SHA1_BASE:
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printf("%sSHA1", SEP_STR);
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sbuf_printf(sb, "%sSHA1", SEP_STR);
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break;
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default:
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printf("%sUnknown SHA1", SEP_STR);
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sbuf_printf(sb, "%sUnknown SHA1", SEP_STR);
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break;
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}
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@ -281,13 +286,13 @@ print_cpu_features(u_int cpu)
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case ID_AA64ISAR0_SHA2_NONE:
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break;
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case ID_AA64ISAR0_SHA2_BASE:
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printf("%sSHA2", SEP_STR);
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sbuf_printf(sb, "%sSHA2", SEP_STR);
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break;
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case ID_AA64ISAR0_SHA2_512:
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printf("%sSHA2+SHA512", SEP_STR);
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sbuf_printf(sb, "%sSHA2+SHA512", SEP_STR);
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break;
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default:
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printf("%sUnknown SHA2", SEP_STR);
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sbuf_printf(sb, "%sUnknown SHA2", SEP_STR);
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break;
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}
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@ -295,10 +300,10 @@ print_cpu_features(u_int cpu)
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case ID_AA64ISAR0_CRC32_NONE:
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break;
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case ID_AA64ISAR0_CRC32_BASE:
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printf("%sCRC32", SEP_STR);
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sbuf_printf(sb, "%sCRC32", SEP_STR);
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break;
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default:
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printf("%sUnknown CRC32", SEP_STR);
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sbuf_printf(sb, "%sUnknown CRC32", SEP_STR);
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break;
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}
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@ -306,10 +311,10 @@ print_cpu_features(u_int cpu)
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case ID_AA64ISAR0_SHA3_NONE:
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break;
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case ID_AA64ISAR0_SHA3_IMPL:
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printf("%sSHA3", SEP_STR);
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sbuf_printf(sb, "%sSHA3", SEP_STR);
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break;
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default:
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printf("%sUnknown SHA3", SEP_STR);
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sbuf_printf(sb, "%sUnknown SHA3", SEP_STR);
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break;
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}
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@ -317,10 +322,10 @@ print_cpu_features(u_int cpu)
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case ID_AA64ISAR0_SM3_NONE:
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break;
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case ID_AA64ISAR0_SM3_IMPL:
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printf("%sSM3", SEP_STR);
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sbuf_printf(sb, "%sSM3", SEP_STR);
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break;
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default:
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printf("%sUnknown SM3", SEP_STR);
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sbuf_printf(sb, "%sUnknown SM3", SEP_STR);
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break;
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}
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@ -328,10 +333,10 @@ print_cpu_features(u_int cpu)
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case ID_AA64ISAR0_SM4_NONE:
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break;
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case ID_AA64ISAR0_SM4_IMPL:
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printf("%sSM4", SEP_STR);
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sbuf_printf(sb, "%sSM4", SEP_STR);
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break;
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default:
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printf("%sUnknown SM4", SEP_STR);
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sbuf_printf(sb, "%sUnknown SM4", SEP_STR);
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break;
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}
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@ -339,33 +344,35 @@ print_cpu_features(u_int cpu)
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case ID_AA64ISAR0_DP_NONE:
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break;
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case ID_AA64ISAR0_DP_IMPL:
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printf("%sDotProd", SEP_STR);
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sbuf_printf(sb, "%sDotProd", SEP_STR);
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break;
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default:
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printf("%sUnknown DP", SEP_STR);
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sbuf_printf(sb, "%sUnknown DP", SEP_STR);
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break;
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}
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if ((cpu_desc[cpu].id_aa64isar0 & ~ID_AA64ISAR0_MASK) != 0)
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printf("%s%#lx", SEP_STR,
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sbuf_printf(sb, "%s%#lx", SEP_STR,
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cpu_desc[cpu].id_aa64isar0 & ~ID_AA64ISAR0_MASK);
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printf(">\n");
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sbuf_finish(sb);
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printf("%s>\n", sbuf_data(sb));
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sbuf_clear(sb);
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}
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/* AArch64 Instruction Set Attribute Register 1 */
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if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR1) != 0) {
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printed = 0;
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printf(" Instruction Set Attributes 1 = <");
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sbuf_printf(sb, " Instruction Set Attributes 1 = <");
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switch (ID_AA64ISAR1_GPI(cpu_desc[cpu].id_aa64isar1)) {
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case ID_AA64ISAR1_GPI_NONE:
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break;
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case ID_AA64ISAR1_GPI_IMPL:
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printf("%sImpl GenericAuth", SEP_STR);
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sbuf_printf(sb, "%sImpl GenericAuth", SEP_STR);
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break;
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default:
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printf("%sUnknown GenericAuth", SEP_STR);
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sbuf_printf(sb, "%sUnknown GenericAuth", SEP_STR);
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break;
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}
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@ -373,10 +380,10 @@ print_cpu_features(u_int cpu)
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case ID_AA64ISAR1_GPA_NONE:
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break;
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case ID_AA64ISAR1_GPA_IMPL:
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printf("%sPrince GenericAuth", SEP_STR);
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sbuf_printf(sb, "%sPrince GenericAuth", SEP_STR);
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break;
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default:
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printf("%sUnknown GenericAuth", SEP_STR);
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sbuf_printf(sb, "%sUnknown GenericAuth", SEP_STR);
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break;
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}
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@ -384,10 +391,10 @@ print_cpu_features(u_int cpu)
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case ID_AA64ISAR1_LRCPC_NONE:
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break;
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case ID_AA64ISAR1_LRCPC_IMPL:
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printf("%sRCpc", SEP_STR);
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sbuf_printf(sb, "%sRCpc", SEP_STR);
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break;
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default:
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printf("%sUnknown RCpc", SEP_STR);
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sbuf_printf(sb, "%sUnknown RCpc", SEP_STR);
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break;
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}
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@ -395,10 +402,10 @@ print_cpu_features(u_int cpu)
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case ID_AA64ISAR1_FCMA_NONE:
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break;
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case ID_AA64ISAR1_FCMA_IMPL:
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printf("%sFCMA", SEP_STR);
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sbuf_printf(sb, "%sFCMA", SEP_STR);
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break;
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default:
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printf("%sUnknown FCMA", SEP_STR);
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sbuf_printf(sb, "%sUnknown FCMA", SEP_STR);
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break;
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}
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@ -406,10 +413,10 @@ print_cpu_features(u_int cpu)
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case ID_AA64ISAR1_JSCVT_NONE:
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break;
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case ID_AA64ISAR1_JSCVT_IMPL:
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printf("%sJS Conv", SEP_STR);
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sbuf_printf(sb, "%sJS Conv", SEP_STR);
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break;
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default:
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printf("%sUnknown JS Conv", SEP_STR);
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sbuf_printf(sb, "%sUnknown JS Conv", SEP_STR);
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break;
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}
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@ -417,10 +424,10 @@ print_cpu_features(u_int cpu)
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case ID_AA64ISAR1_API_NONE:
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break;
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case ID_AA64ISAR1_API_IMPL:
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printf("%sImpl AddrAuth", SEP_STR);
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sbuf_printf(sb, "%sImpl AddrAuth", SEP_STR);
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break;
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default:
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printf("%sUnknown Impl AddrAuth", SEP_STR);
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sbuf_printf(sb, "%sUnknown Impl AddrAuth", SEP_STR);
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break;
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}
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@ -428,10 +435,10 @@ print_cpu_features(u_int cpu)
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case ID_AA64ISAR1_APA_NONE:
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break;
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case ID_AA64ISAR1_APA_IMPL:
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printf("%sPrince AddrAuth", SEP_STR);
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sbuf_printf(sb, "%sPrince AddrAuth", SEP_STR);
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break;
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default:
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printf("%sUnknown Prince AddrAuth", SEP_STR);
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sbuf_printf(sb, "%sUnknown Prince AddrAuth", SEP_STR);
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break;
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}
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@ -439,32 +446,34 @@ print_cpu_features(u_int cpu)
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case ID_AA64ISAR1_DPB_NONE:
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break;
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case ID_AA64ISAR1_DPB_IMPL:
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printf("%sDC CVAP", SEP_STR);
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sbuf_printf(sb, "%sDC CVAP", SEP_STR);
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break;
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default:
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printf("%sUnknown DC CVAP", SEP_STR);
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sbuf_printf(sb, "%sUnknown DC CVAP", SEP_STR);
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break;
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}
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if ((cpu_desc[cpu].id_aa64isar1 & ~ID_AA64ISAR1_MASK) != 0)
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printf("%s%#lx", SEP_STR,
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sbuf_printf(sb, "%s%#lx", SEP_STR,
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cpu_desc[cpu].id_aa64isar1 & ~ID_AA64ISAR1_MASK);
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printf(">\n");
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sbuf_finish(sb);
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printf("%s>\n", sbuf_data(sb));
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sbuf_clear(sb);
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}
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/* AArch64 Processor Feature Register 0 */
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if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_PFR0) != 0) {
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printed = 0;
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printf(" Processor Features 0 = <");
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sbuf_printf(sb, " Processor Features 0 = <");
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switch (ID_AA64PFR0_SVE(cpu_desc[cpu].id_aa64pfr0)) {
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case ID_AA64PFR0_SVE_NONE:
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break;
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case ID_AA64PFR0_SVE_IMPL:
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printf("%sSVE", SEP_STR);
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sbuf_printf(sb, "%sSVE", SEP_STR);
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break;
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default:
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printf("%sUnknown SVE", SEP_STR);
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sbuf_printf(sb, "%sUnknown SVE", SEP_STR);
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break;
|
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}
|
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|
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|
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@ -472,10 +481,10 @@ print_cpu_features(u_int cpu)
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case ID_AA64PFR0_RAS_NONE:
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break;
|
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case ID_AA64PFR0_RAS_V1:
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printf("%sRASv1", SEP_STR);
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sbuf_printf(sb, "%sRASv1", SEP_STR);
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break;
|
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default:
|
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printf("%sUnknown RAS", SEP_STR);
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sbuf_printf(sb, "%sUnknown RAS", SEP_STR);
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||||
break;
|
||||
}
|
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|
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|
|
@ -483,10 +492,10 @@ print_cpu_features(u_int cpu)
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case ID_AA64PFR0_GIC_CPUIF_NONE:
|
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break;
|
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case ID_AA64PFR0_GIC_CPUIF_EN:
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printf("%sGIC", SEP_STR);
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sbuf_printf(sb, "%sGIC", SEP_STR);
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break;
|
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default:
|
||||
printf("%sUnknown GIC interface", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown GIC interface", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -494,13 +503,13 @@ print_cpu_features(u_int cpu)
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case ID_AA64PFR0_ADV_SIMD_NONE:
|
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break;
|
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case ID_AA64PFR0_ADV_SIMD_IMPL:
|
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printf("%sAdvSIMD", SEP_STR);
|
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sbuf_printf(sb, "%sAdvSIMD", SEP_STR);
|
||||
break;
|
||||
case ID_AA64PFR0_ADV_SIMD_HP:
|
||||
printf("%sAdvSIMD+HP", SEP_STR);
|
||||
sbuf_printf(sb, "%sAdvSIMD+HP", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown AdvSIMD", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown AdvSIMD", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
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@ -508,75 +517,77 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64PFR0_FP_NONE:
|
||||
break;
|
||||
case ID_AA64PFR0_FP_IMPL:
|
||||
printf("%sFloat", SEP_STR);
|
||||
sbuf_printf(sb, "%sFloat", SEP_STR);
|
||||
break;
|
||||
case ID_AA64PFR0_FP_HP:
|
||||
printf("%sFloat+HP", SEP_STR);
|
||||
sbuf_printf(sb, "%sFloat+HP", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown Float", SEP_STR);
|
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sbuf_printf(sb, "%sUnknown Float", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (ID_AA64PFR0_EL3(cpu_desc[cpu].id_aa64pfr0)) {
|
||||
case ID_AA64PFR0_EL3_NONE:
|
||||
printf("%sNo EL3", SEP_STR);
|
||||
sbuf_printf(sb, "%sNo EL3", SEP_STR);
|
||||
break;
|
||||
case ID_AA64PFR0_EL3_64:
|
||||
printf("%sEL3", SEP_STR);
|
||||
sbuf_printf(sb, "%sEL3", SEP_STR);
|
||||
break;
|
||||
case ID_AA64PFR0_EL3_64_32:
|
||||
printf("%sEL3 32", SEP_STR);
|
||||
sbuf_printf(sb, "%sEL3 32", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown EL3", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown EL3", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (ID_AA64PFR0_EL2(cpu_desc[cpu].id_aa64pfr0)) {
|
||||
case ID_AA64PFR0_EL2_NONE:
|
||||
printf("%sNo EL2", SEP_STR);
|
||||
sbuf_printf(sb, "%sNo EL2", SEP_STR);
|
||||
break;
|
||||
case ID_AA64PFR0_EL2_64:
|
||||
printf("%sEL2", SEP_STR);
|
||||
sbuf_printf(sb, "%sEL2", SEP_STR);
|
||||
break;
|
||||
case ID_AA64PFR0_EL2_64_32:
|
||||
printf("%sEL2 32", SEP_STR);
|
||||
sbuf_printf(sb, "%sEL2 32", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown EL2", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown EL2", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (ID_AA64PFR0_EL1(cpu_desc[cpu].id_aa64pfr0)) {
|
||||
case ID_AA64PFR0_EL1_64:
|
||||
printf("%sEL1", SEP_STR);
|
||||
sbuf_printf(sb, "%sEL1", SEP_STR);
|
||||
break;
|
||||
case ID_AA64PFR0_EL1_64_32:
|
||||
printf("%sEL1 32", SEP_STR);
|
||||
sbuf_printf(sb, "%sEL1 32", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown EL1", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown EL1", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (ID_AA64PFR0_EL0(cpu_desc[cpu].id_aa64pfr0)) {
|
||||
case ID_AA64PFR0_EL0_64:
|
||||
printf("%sEL0", SEP_STR);
|
||||
sbuf_printf(sb, "%sEL0", SEP_STR);
|
||||
break;
|
||||
case ID_AA64PFR0_EL0_64_32:
|
||||
printf("%sEL0 32", SEP_STR);
|
||||
sbuf_printf(sb, "%sEL0 32", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown EL0", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown EL0", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
if ((cpu_desc[cpu].id_aa64pfr0 & ~ID_AA64PFR0_MASK) != 0)
|
||||
printf("%s%#lx", SEP_STR,
|
||||
sbuf_printf(sb, "%s%#lx", SEP_STR,
|
||||
cpu_desc[cpu].id_aa64pfr0 & ~ID_AA64PFR0_MASK);
|
||||
|
||||
printf(">\n");
|
||||
sbuf_finish(sb);
|
||||
printf("%s>\n", sbuf_data(sb));
|
||||
sbuf_clear(sb);
|
||||
}
|
||||
|
||||
/* AArch64 Processor Feature Register 1 */
|
||||
|
|
@ -588,15 +599,15 @@ print_cpu_features(u_int cpu)
|
|||
/* AArch64 Memory Model Feature Register 0 */
|
||||
if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR0) != 0) {
|
||||
printed = 0;
|
||||
printf(" Memory Model Features 0 = <");
|
||||
sbuf_printf(sb, " Memory Model Features 0 = <");
|
||||
switch (ID_AA64MMFR0_TGRAN4(cpu_desc[cpu].id_aa64mmfr0)) {
|
||||
case ID_AA64MMFR0_TGRAN4_NONE:
|
||||
break;
|
||||
case ID_AA64MMFR0_TGRAN4_IMPL:
|
||||
printf("%s4k Granule", SEP_STR);
|
||||
sbuf_printf(sb, "%s4k Granule", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown 4k Granule", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown 4k Granule", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -604,10 +615,10 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64MMFR0_TGRAN16_NONE:
|
||||
break;
|
||||
case ID_AA64MMFR0_TGRAN16_IMPL:
|
||||
printf("%s16k Granule", SEP_STR);
|
||||
sbuf_printf(sb, "%s16k Granule", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown 16k Granule", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown 16k Granule", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -615,10 +626,10 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64MMFR0_TGRAN64_NONE:
|
||||
break;
|
||||
case ID_AA64MMFR0_TGRAN64_IMPL:
|
||||
printf("%s64k Granule", SEP_STR);
|
||||
sbuf_printf(sb, "%s64k Granule", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown 64k Granule", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown 64k Granule", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -626,10 +637,10 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64MMFR0_BIGEND_FIXED:
|
||||
break;
|
||||
case ID_AA64MMFR0_BIGEND_MIXED:
|
||||
printf("%sMixedEndian", SEP_STR);
|
||||
sbuf_printf(sb, "%sMixedEndian", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown Endian switching", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown Endian switching", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -637,10 +648,10 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64MMFR0_BIGEND_EL0_FIXED:
|
||||
break;
|
||||
case ID_AA64MMFR0_BIGEND_EL0_MIXED:
|
||||
printf("%sEL0 MixEndian", SEP_STR);
|
||||
sbuf_printf(sb, "%sEL0 MixEndian", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown EL0 Endian switching", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown EL0 Endian switching", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -648,71 +659,73 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64MMFR0_S_NS_MEM_NONE:
|
||||
break;
|
||||
case ID_AA64MMFR0_S_NS_MEM_DISTINCT:
|
||||
printf("%sS/NS Mem", SEP_STR);
|
||||
sbuf_printf(sb, "%sS/NS Mem", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown S/NS Mem", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown S/NS Mem", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (ID_AA64MMFR0_ASID_BITS(cpu_desc[cpu].id_aa64mmfr0)) {
|
||||
case ID_AA64MMFR0_ASID_BITS_8:
|
||||
printf("%s8bit ASID", SEP_STR);
|
||||
sbuf_printf(sb, "%s8bit ASID", SEP_STR);
|
||||
break;
|
||||
case ID_AA64MMFR0_ASID_BITS_16:
|
||||
printf("%s16bit ASID", SEP_STR);
|
||||
sbuf_printf(sb, "%s16bit ASID", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown ASID", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown ASID", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (ID_AA64MMFR0_PA_RANGE(cpu_desc[cpu].id_aa64mmfr0)) {
|
||||
case ID_AA64MMFR0_PA_RANGE_4G:
|
||||
printf("%s4GB PA", SEP_STR);
|
||||
sbuf_printf(sb, "%s4GB PA", SEP_STR);
|
||||
break;
|
||||
case ID_AA64MMFR0_PA_RANGE_64G:
|
||||
printf("%s64GB PA", SEP_STR);
|
||||
sbuf_printf(sb, "%s64GB PA", SEP_STR);
|
||||
break;
|
||||
case ID_AA64MMFR0_PA_RANGE_1T:
|
||||
printf("%s1TB PA", SEP_STR);
|
||||
sbuf_printf(sb, "%s1TB PA", SEP_STR);
|
||||
break;
|
||||
case ID_AA64MMFR0_PA_RANGE_4T:
|
||||
printf("%s4TB PA", SEP_STR);
|
||||
sbuf_printf(sb, "%s4TB PA", SEP_STR);
|
||||
break;
|
||||
case ID_AA64MMFR0_PA_RANGE_16T:
|
||||
printf("%s16TB PA", SEP_STR);
|
||||
sbuf_printf(sb, "%s16TB PA", SEP_STR);
|
||||
break;
|
||||
case ID_AA64MMFR0_PA_RANGE_256T:
|
||||
printf("%s256TB PA", SEP_STR);
|
||||
sbuf_printf(sb, "%s256TB PA", SEP_STR);
|
||||
break;
|
||||
case ID_AA64MMFR0_PA_RANGE_4P:
|
||||
printf("%s4PB PA", SEP_STR);
|
||||
sbuf_printf(sb, "%s4PB PA", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown PA Range", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown PA Range", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
if ((cpu_desc[cpu].id_aa64mmfr0 & ~ID_AA64MMFR0_MASK) != 0)
|
||||
printf("%s%#lx", SEP_STR,
|
||||
sbuf_printf(sb, "%s%#lx", SEP_STR,
|
||||
cpu_desc[cpu].id_aa64mmfr0 & ~ID_AA64MMFR0_MASK);
|
||||
printf(">\n");
|
||||
sbuf_finish(sb);
|
||||
printf("%s>\n", sbuf_data(sb));
|
||||
sbuf_clear(sb);
|
||||
}
|
||||
|
||||
/* AArch64 Memory Model Feature Register 1 */
|
||||
if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR1) != 0) {
|
||||
printed = 0;
|
||||
printf(" Memory Model Features 1 = <");
|
||||
sbuf_printf(sb, " Memory Model Features 1 = <");
|
||||
|
||||
switch (ID_AA64MMFR1_XNX(cpu_desc[cpu].id_aa64mmfr1)) {
|
||||
case ID_AA64MMFR1_XNX_NONE:
|
||||
break;
|
||||
case ID_AA64MMFR1_XNX_IMPL:
|
||||
printf("%sEL2 XN", SEP_STR);
|
||||
sbuf_printf(sb, "%sEL2 XN", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown XNX", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown XNX", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -720,10 +733,10 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64MMFR1_SPEC_SEI_NONE:
|
||||
break;
|
||||
case ID_AA64MMFR1_SPEC_SEI_IMPL:
|
||||
printf("%sSpecSEI", SEP_STR);
|
||||
sbuf_printf(sb, "%sSpecSEI", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown SpecSEI", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown SpecSEI", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -731,13 +744,13 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64MMFR1_PAN_NONE:
|
||||
break;
|
||||
case ID_AA64MMFR1_PAN_IMPL:
|
||||
printf("%sPAN", SEP_STR);
|
||||
sbuf_printf(sb, "%sPAN", SEP_STR);
|
||||
break;
|
||||
case ID_AA64MMFR1_PAN_ATS1E1:
|
||||
printf("%sPAN+AT", SEP_STR);
|
||||
sbuf_printf(sb, "%sPAN+AT", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown PAN", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown PAN", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -745,10 +758,10 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64MMFR1_LO_NONE:
|
||||
break;
|
||||
case ID_AA64MMFR1_LO_IMPL:
|
||||
printf("%sLO", SEP_STR);
|
||||
sbuf_printf(sb, "%sLO", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown LO", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown LO", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -756,13 +769,13 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64MMFR1_HPDS_NONE:
|
||||
break;
|
||||
case ID_AA64MMFR1_HPDS_HPD:
|
||||
printf("%sHPDS", SEP_STR);
|
||||
sbuf_printf(sb, "%sHPDS", SEP_STR);
|
||||
break;
|
||||
case ID_AA64MMFR1_HPDS_TTPBHA:
|
||||
printf("%sTTPBHA", SEP_STR);
|
||||
sbuf_printf(sb, "%sTTPBHA", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown HPDS", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown HPDS", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -770,10 +783,10 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64MMFR1_VH_NONE:
|
||||
break;
|
||||
case ID_AA64MMFR1_VH_IMPL:
|
||||
printf("%sVHE", SEP_STR);
|
||||
sbuf_printf(sb, "%sVHE", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown VHE", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown VHE", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -781,10 +794,10 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64MMFR1_VMIDBITS_8:
|
||||
break;
|
||||
case ID_AA64MMFR1_VMIDBITS_16:
|
||||
printf("%s16 VMID bits", SEP_STR);
|
||||
sbuf_printf(sb, "%s16 VMID bits", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown VMID bits", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown VMID bits", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -792,59 +805,61 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64MMFR1_HAFDBS_NONE:
|
||||
break;
|
||||
case ID_AA64MMFR1_HAFDBS_AF:
|
||||
printf("%sAF", SEP_STR);
|
||||
sbuf_printf(sb, "%sAF", SEP_STR);
|
||||
break;
|
||||
case ID_AA64MMFR1_HAFDBS_AF_DBS:
|
||||
printf("%sAF+DBS", SEP_STR);
|
||||
sbuf_printf(sb, "%sAF+DBS", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown Hardware update AF/DBS", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown Hardware update AF/DBS", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
if ((cpu_desc[cpu].id_aa64mmfr1 & ~ID_AA64MMFR1_MASK) != 0)
|
||||
printf("%s%#lx", SEP_STR,
|
||||
sbuf_printf(sb, "%s%#lx", SEP_STR,
|
||||
cpu_desc[cpu].id_aa64mmfr1 & ~ID_AA64MMFR1_MASK);
|
||||
printf(">\n");
|
||||
sbuf_finish(sb);
|
||||
printf("%s>\n", sbuf_data(sb));
|
||||
sbuf_clear(sb);
|
||||
}
|
||||
|
||||
/* AArch64 Memory Model Feature Register 2 */
|
||||
if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR2) != 0) {
|
||||
printed = 0;
|
||||
printf(" Memory Model Features 2 = <");
|
||||
sbuf_printf(sb, " Memory Model Features 2 = <");
|
||||
|
||||
switch (ID_AA64MMFR2_NV(cpu_desc[cpu].id_aa64mmfr2)) {
|
||||
case ID_AA64MMFR2_NV_NONE:
|
||||
break;
|
||||
case ID_AA64MMFR2_NV_IMPL:
|
||||
printf("%sNestedVirt", SEP_STR);
|
||||
sbuf_printf(sb, "%sNestedVirt", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown NestedVirt", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown NestedVirt", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (ID_AA64MMFR2_CCIDX(cpu_desc[cpu].id_aa64mmfr2)) {
|
||||
case ID_AA64MMFR2_CCIDX_32:
|
||||
printf("%s32b CCIDX", SEP_STR);
|
||||
sbuf_printf(sb, "%s32b CCIDX", SEP_STR);
|
||||
break;
|
||||
case ID_AA64MMFR2_CCIDX_64:
|
||||
printf("%s64b CCIDX", SEP_STR);
|
||||
sbuf_printf(sb, "%s64b CCIDX", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown CCIDX", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown CCIDX", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (ID_AA64MMFR2_VA_RANGE(cpu_desc[cpu].id_aa64mmfr2)) {
|
||||
case ID_AA64MMFR2_VA_RANGE_48:
|
||||
printf("%s48b VA", SEP_STR);
|
||||
sbuf_printf(sb, "%s48b VA", SEP_STR);
|
||||
break;
|
||||
case ID_AA64MMFR2_VA_RANGE_52:
|
||||
printf("%s52b VA", SEP_STR);
|
||||
sbuf_printf(sb, "%s52b VA", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown VA Range", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown VA Range", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -852,10 +867,10 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64MMFR2_IESB_NONE:
|
||||
break;
|
||||
case ID_AA64MMFR2_IESB_IMPL:
|
||||
printf("%sIESB", SEP_STR);
|
||||
sbuf_printf(sb, "%sIESB", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown IESB", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown IESB", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -863,10 +878,10 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64MMFR2_LSM_NONE:
|
||||
break;
|
||||
case ID_AA64MMFR2_LSM_IMPL:
|
||||
printf("%sLSM", SEP_STR);
|
||||
sbuf_printf(sb, "%sLSM", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown LSM", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown LSM", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -874,10 +889,10 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64MMFR2_UAO_NONE:
|
||||
break;
|
||||
case ID_AA64MMFR2_UAO_IMPL:
|
||||
printf("%sUAO", SEP_STR);
|
||||
sbuf_printf(sb, "%sUAO", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown UAO", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown UAO", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -885,57 +900,59 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64MMFR2_CNP_NONE:
|
||||
break;
|
||||
case ID_AA64MMFR2_CNP_IMPL:
|
||||
printf("%sCnP", SEP_STR);
|
||||
sbuf_printf(sb, "%sCnP", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown CnP", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown CnP", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
if ((cpu_desc[cpu].id_aa64mmfr2 & ~ID_AA64MMFR2_MASK) != 0)
|
||||
printf("%s%#lx", SEP_STR,
|
||||
sbuf_printf(sb, "%s%#lx", SEP_STR,
|
||||
cpu_desc[cpu].id_aa64mmfr2 & ~ID_AA64MMFR2_MASK);
|
||||
printf(">\n");
|
||||
sbuf_finish(sb);
|
||||
printf("%s>\n", sbuf_data(sb));
|
||||
sbuf_clear(sb);
|
||||
}
|
||||
|
||||
/* AArch64 Debug Feature Register 0 */
|
||||
if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_DFR0) != 0) {
|
||||
printed = 0;
|
||||
printf(" Debug Features 0 = <");
|
||||
sbuf_printf(sb, " Debug Features 0 = <");
|
||||
switch(ID_AA64DFR0_PMS_VER(cpu_desc[cpu].id_aa64dfr0)) {
|
||||
case ID_AA64DFR0_PMS_VER_NONE:
|
||||
break;
|
||||
case ID_AA64DFR0_PMS_VER_V1:
|
||||
printf("%sSPE v1", SEP_STR);
|
||||
sbuf_printf(sb, "%sSPE v1", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown SPE", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown SPE", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
printf("%s%lu CTX Breakpoints", SEP_STR,
|
||||
sbuf_printf(sb, "%s%lu CTX Breakpoints", SEP_STR,
|
||||
ID_AA64DFR0_CTX_CMPS(cpu_desc[cpu].id_aa64dfr0));
|
||||
|
||||
printf("%s%lu Watchpoints", SEP_STR,
|
||||
sbuf_printf(sb, "%s%lu Watchpoints", SEP_STR,
|
||||
ID_AA64DFR0_WRPS(cpu_desc[cpu].id_aa64dfr0));
|
||||
|
||||
printf("%s%lu Breakpoints", SEP_STR,
|
||||
sbuf_printf(sb, "%s%lu Breakpoints", SEP_STR,
|
||||
ID_AA64DFR0_BRPS(cpu_desc[cpu].id_aa64dfr0));
|
||||
|
||||
switch (ID_AA64DFR0_PMU_VER(cpu_desc[cpu].id_aa64dfr0)) {
|
||||
case ID_AA64DFR0_PMU_VER_NONE:
|
||||
break;
|
||||
case ID_AA64DFR0_PMU_VER_3:
|
||||
printf("%sPMUv3", SEP_STR);
|
||||
sbuf_printf(sb, "%sPMUv3", SEP_STR);
|
||||
break;
|
||||
case ID_AA64DFR0_PMU_VER_3_1:
|
||||
printf("%sPMUv3+16 bit evtCount", SEP_STR);
|
||||
sbuf_printf(sb, "%sPMUv3+16 bit evtCount", SEP_STR);
|
||||
break;
|
||||
case ID_AA64DFR0_PMU_VER_IMPL:
|
||||
printf("%sImplementation defined PMU", SEP_STR);
|
||||
sbuf_printf(sb, "%sImplementation defined PMU", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown PMU", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown PMU", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -943,32 +960,34 @@ print_cpu_features(u_int cpu)
|
|||
case ID_AA64DFR0_TRACE_VER_NONE:
|
||||
break;
|
||||
case ID_AA64DFR0_TRACE_VER_IMPL:
|
||||
printf("%sTrace", SEP_STR);
|
||||
sbuf_printf(sb, "%sTrace", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown Trace", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown Trace", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
switch (ID_AA64DFR0_DEBUG_VER(cpu_desc[cpu].id_aa64dfr0)) {
|
||||
case ID_AA64DFR0_DEBUG_VER_8:
|
||||
printf("%sDebug v8", SEP_STR);
|
||||
sbuf_printf(sb, "%sDebug v8", SEP_STR);
|
||||
break;
|
||||
case ID_AA64DFR0_DEBUG_VER_8_VHE:
|
||||
printf("%sDebug v8+VHE", SEP_STR);
|
||||
sbuf_printf(sb, "%sDebug v8+VHE", SEP_STR);
|
||||
break;
|
||||
case ID_AA64DFR0_DEBUG_VER_8_2:
|
||||
printf("%sDebug v8.2", SEP_STR);
|
||||
sbuf_printf(sb, "%sDebug v8.2", SEP_STR);
|
||||
break;
|
||||
default:
|
||||
printf("%sUnknown Debug", SEP_STR);
|
||||
sbuf_printf(sb, "%sUnknown Debug", SEP_STR);
|
||||
break;
|
||||
}
|
||||
|
||||
if (cpu_desc[cpu].id_aa64dfr0 & ~ID_AA64DFR0_MASK)
|
||||
printf("%s%#lx", SEP_STR,
|
||||
sbuf_printf(sb, "%s%#lx", SEP_STR,
|
||||
cpu_desc[cpu].id_aa64dfr0 & ~ID_AA64DFR0_MASK);
|
||||
printf(">\n");
|
||||
sbuf_finish(sb);
|
||||
printf("%s>\n", sbuf_data(sb));
|
||||
sbuf_clear(sb);
|
||||
}
|
||||
|
||||
/* AArch64 Memory Model Feature Register 1 */
|
||||
|
|
@ -989,6 +1008,8 @@ print_cpu_features(u_int cpu)
|
|||
cpu_desc[cpu].id_aa64afr1);
|
||||
}
|
||||
|
||||
sbuf_delete(sb);
|
||||
sb = NULL;
|
||||
#undef SEP_STR
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue