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Use the method described in IA-32 Intel Architecture Software Developer's

Browse source 
Manual chapter 11.6.6 to get valid mxcsr bits, use the mxcsr mask to clear
invalid bits passed by user code.

Reviewed by: bde
This commit is contained in:
David Xu 2006-05-30 23:44:21 +00:00
parent 4e359f5ad1
commit afedf1a7f1
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=159087
6 changed files with 21 additions and 11 deletions
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1
sys/i386/i386/initcpu.c
View file

@ -87,6 +87,7 @@ char cpu_vendor[20] = ""; /* CPU Origin code */
#ifdef CPU_ENABLE_SSE
u_int cpu_fxsr; /* SSE enabled */
u_int cpu_mxcsr_mask; /* valid bits in mxcsr */
#endif
#ifdef I486_CPU

6
sys/i386/i386/machdep.c
View file

@ -2710,9 +2710,9 @@ set_fpcontext(struct thread *td, const mcontext_t *mcp)
bcopy(&mcp->mc_fpstate, addr, sizeof(mcp->mc_fpstate));
}
#ifdef DEV_NPX
/* clear high 16 bits of mxcsr to avoid security problem. */
if (cpu_fxsr)
addr->sv_xmm.sv_env.en_mxcsr &= 0xFFFF;
#ifdef CPU_ENABLE_SSE
addr->sv_xmm.sv_env.en_mxcsr &= cpu_mxcsr_mask;
#endif
/*
* XXX we violate the dubious requirement that npxsetregs()
* be called with interrupts disabled.

11
sys/i386/i386/ptrace_machdep.c
View file

@ -45,22 +45,21 @@ int
cpu_ptrace(struct thread *td, int req, void *addr, int data)
{
#ifdef CPU_ENABLE_SSE
struct savexmm *fpstate;
int error;
if (!cpu_fxsr)
return (EINVAL);
fpstate = &td->td_pcb->pcb_save.sv_xmm;
switch (req) {
case PT_GETXMMREGS:
error = copyout(&td->td_pcb->pcb_save.sv_xmm, addr,
sizeof(td->td_pcb->pcb_save.sv_xmm));
error = copyout(fpstate, addr, sizeof(*fpstate));
break;
case PT_SETXMMREGS:
error = copyin(addr, &td->td_pcb->pcb_save.sv_xmm,
sizeof(td->td_pcb->pcb_save.sv_xmm));
/* clear high 16 bits of mxcsr to avoid security problem. */
td->td_pcb->pcb_save.sv_xmm.sv_env.en_mxcsr &= 0xFFFF;
error = copyin(addr, fpstate, sizeof(*fpstate));
fpstate->sv_env.en_mxcsr &= cpu_mxcsr_mask;
break;
default:

1
sys/i386/include/md_var.h
View file

@ -52,6 +52,7 @@ extern u_int amd_feature2;
extern u_int cpu_fxsr;
extern u_int cpu_high;
extern u_int cpu_id;
extern u_int cpu_mxcsr_mask;
extern u_int cpu_procinfo;
extern u_int cpu_procinfo2;
extern char cpu_vendor[];

4
sys/i386/include/npx.h
View file

@ -92,8 +92,8 @@ struct envxmm {
u_int32_t en_foo; /* floating operand offset */
u_int16_t en_fos; /* floating operand segment selector */
u_int16_t en_pad1; /* padding */
u_int32_t en_mxcsr; /* SSE sontorol/status register */
u_int32_t en_pad2; /* padding */
u_int32_t en_mxcsr; /* SSE control/status register */
u_int32_t en_mxcsr_mask; /* valid bits in mxcsr */
};
/* Contents of each SSE extended accumulator */

9
sys/i386/isa/npx.c
View file

@ -417,6 +417,15 @@ npx_attach(dev)
stop_emulating();
fpusave(&npx_cleanstate);
start_emulating();
#ifdef CPU_ENABLE_SSE
if (cpu_fxsr) {
if (npx_cleanstate.sv_xmm.sv_env.en_mxcsr_mask)
cpu_mxcsr_mask =
npx_cleanstate.sv_xmm.sv_env.en_mxcsr_mask;
else
cpu_mxcsr_mask = 0xFFBF;
}
#endif
npx_cleanstate_ready = 1;
intr_restore(s);
}