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Import device-tree files from Linux 6.6

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Sponsored by:	Beckhoff Automation GmbH & Co. KG
This commit is contained in:
Emmanuel Vadot 2024-05-06 10:43:59 +02:00
parent c097967b9a dbacf41c97
commit aa1a8ff2d6
1671 changed files with 53945 additions and 12669 deletions
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5
sys/contrib/device-tree/Bindings/.yamllint
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@ -1,6 +1,11 @@
extends: relaxed
rules:
quoted-strings:
required: only-when-needed
extra-allowed:
- '[$^,[]'
- '^/$'
line-length:
# 80 chars should be enough, but don't fail if a line is longer
max: 110

8
sys/contrib/device-tree/Bindings/arm/amlogic.yaml
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@ -218,6 +218,14 @@ properties:
- amlogic,aq222
- const: amlogic,s4
- description: Boards with the Amlogic T7 A311D2 SoC
items:
- enum:
- amlogic,an400
- khadas,vim4
- const: amlogic,a311d2
- const: amlogic,t7
additionalProperties: true
...

2
sys/contrib/device-tree/Bindings/arm/arm,coresight-cti.yaml
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@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright 2019 Linaro Ltd.
%YAML 1.2
---

2
sys/contrib/device-tree/Bindings/arm/arm,coresight-dummy-sink.yaml
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@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-dummy-sink.yaml#

2
sys/contrib/device-tree/Bindings/arm/arm,coresight-dummy-source.yaml
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@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,coresight-dummy-source.yaml#

6
sys/contrib/device-tree/Bindings/arm/arm,embedded-trace-extension.yaml
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@ -1,9 +1,9 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright 2021, Arm Ltd
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Embedded Trace Extensions

9
sys/contrib/device-tree/Bindings/arm/arm,trace-buffer-extension.yaml
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@ -1,9 +1,9 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright 2021, Arm Ltd
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Trace Buffer Extensions
@ -19,7 +19,8 @@ description: |
properties:
$nodename:
const: "trbe"
const: trbe
compatible:
items:
- const: arm,trace-buffer-extension

2
sys/contrib/device-tree/Bindings/arm/arm,versatile-sysreg.yaml
View file

@ -1,4 +1,4 @@
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,versatile-sysreg.yaml#

2
sys/contrib/device-tree/Bindings/arm/arm,vexpress-juno.yaml
View file

@ -143,7 +143,7 @@ patternProperties:
"simple-bus". If the compatible is placed in the "motherboard-bus" node,
it is stricter and always has two compatibles.
type: object
$ref: '/schemas/simple-bus.yaml'
$ref: /schemas/simple-bus.yaml
unevaluatedProperties: false
properties:

4
sys/contrib/device-tree/Bindings/arm/aspeed/aspeed,sbc.yaml
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@ -2,8 +2,8 @@
# Copyright 2021 Joel Stanley, IBM Corp.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ASPEED Secure Boot Controller

4
sys/contrib/device-tree/Bindings/arm/aspeed/aspeed.yaml
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@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/aspeed/aspeed.yaml#
@ -79,9 +79,11 @@ properties:
- facebook,elbert-bmc
- facebook,fuji-bmc
- facebook,greatlakes-bmc
- facebook,yosemite4-bmc
- ibm,everest-bmc
- ibm,rainier-bmc
- ibm,tacoma-bmc
- inventec,starscream-bmc
- inventec,transformer-bmc
- jabil,rbp-bmc
- qcom,dc-scm-v1-bmc

1
sys/contrib/device-tree/Bindings/arm/bcm/brcm,bcm4708.yaml
View file

@ -66,6 +66,7 @@ properties:
- description: BCM47094 based boards
items:
- enum:
- asus,rt-ac3100
- asus,rt-ac88u
- dlink,dir-885l
- dlink,dir-890l

39
sys/contrib/device-tree/Bindings/arm/bcm/brcm,bcm53573.yaml Normal file
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@ -0,0 +1,39 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm53573.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom BCM53573 SoCs family
description:
Broadcom BCM53573 / BCM47189 Wi-Fi SoCs derived from Northstar.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: BCM53573 based boards
items:
- enum:
- tenda,ac6-v1
- tenda,w15e-v1
- const: brcm,bcm53573
- description: BCM47189 based boards
items:
- enum:
- brcm,bcm947189acdbmr
- luxul,xap-810-v1
- luxul,xap-1440-v1
- tenda,ac9
- const: brcm,bcm47189
- const: brcm,bcm53573
additionalProperties: true
...

3
sys/contrib/device-tree/Bindings/arm/cpus.yaml
View file

@ -143,8 +143,10 @@ properties:
- arm,cortex-a78ae
- arm,cortex-a78c
- arm,cortex-a510
- arm,cortex-a520
- arm,cortex-a710
- arm,cortex-a715
- arm,cortex-a720
- arm,cortex-m0
- arm,cortex-m0+
- arm,cortex-m1
@ -158,6 +160,7 @@ properties:
- arm,cortex-x1c
- arm,cortex-x2
- arm,cortex-x3
- arm,cortex-x4
- arm,neoverse-e1
- arm,neoverse-n1
- arm,neoverse-n2

4
sys/contrib/device-tree/Bindings/arm/firmware/tlm,trusted-foundations.yaml
View file

@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/firmware/tlm,trusted-foundations.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/firmware/tlm,trusted-foundations.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Trusted Foundations

53
sys/contrib/device-tree/Bindings/arm/fsl.yaml
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@ -909,6 +909,7 @@ properties:
- fsl,imx8mm-evk # i.MX8MM EVK Board
- fsl,imx8mm-evkb # i.MX8MM EVKB Board
- gateworks,imx8mm-gw7904
- gateworks,imx8mm-gw7905-0x # i.MX8MM Gateworks Board
- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
@ -1031,10 +1032,11 @@ properties:
- beacon,imx8mp-beacon-kit # i.MX8MP Beacon Development Kit
- dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
- fsl,imx8mp-evk # i.MX8MP EVK Board
- gateworks,imx8mp-gw71xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw7905-2x # i.MX8MP Gateworks Board
- polyhex,imx8mp-debix # Polyhex Debix boards
- polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
- toradex,verdin-imx8mp # Verdin iMX8M Plus Modules
- toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT
- toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules
@ -1068,6 +1070,20 @@ properties:
- const: phytec,imx8mp-phycore-som # phyCORE-i.MX8MP SoM
- const: fsl,imx8mp
- description: Polyhex DEBIX i.MX8MP based SBCs
items:
- enum:
- polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board
- const: polyhex,imx8mp-debix # Polyhex i.MX8MP Debix SBCs
- const: fsl,imx8mp
- description: Polyhex DEBIX i.MX8MP SOM A based boards
items:
- enum:
- polyhex,imx8mp-debix-som-a-bmb-08 # Polyhex Debix SOM A on SOM A I/O board
- const: polyhex,imx8mp-debix-som-a # Polyhex Debix SOM A
- const: fsl,imx8mp
- description: Toradex Boards with Verdin iMX8M Plus Modules
items:
- enum:
@ -1219,12 +1235,31 @@ properties:
- fsl,imxrt1170-evk # i.MXRT1170 EVK Board
- const: fsl,imxrt1170
- description:
TQMa93xxLA and TQMa93xxCA are two series of feature compatible SOM
using NXP i.MX93 SOC in 11x11 mm package.
TQMa93xxLA is designed to be soldered on different carrier boards.
TQMa93xxCA is a compatible variant using board to board connectors.
All SOM and CPU variants use the same device tree hence only one
compatible is needed. Bootloader disables all features not present
in the assembled SOC.
MBa93xxCA mainboard can be used as starterkit for the SOM
soldered on an adapter board or for the connector variant
MBa93xxLA mainboard is a single board computer using the solderable
SOM variant
items:
- enum:
- tq,imx93-tqma9352-mba93xxca # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM on MBa93xxCA
- tq,imx93-tqma9352-mba93xxla # TQ-Systems GmbH i.MX93 TQMa93xxLA SOM on MBa93xxLA SBC
- const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM
- const: fsl,imx93
- description:
Freescale Vybrid Platform Device Tree Bindings
For the Vybrid SoC familiy all variants with DDR controller are supported,
For the Vybrid SoC family all variants with DDR controller are supported,
which is the VF5xx and VF6xx series. Out of historical reasons, in most
places the kernel uses vf610 to refer to the whole familiy.
places the kernel uses vf610 to refer to the whole family.
The compatible string "fsl,vf610m4" is used for the secondary Cortex-M4
core support.
items:
@ -1289,6 +1324,16 @@ properties:
- fsl,ls1021a-twr
- const: fsl,ls1021a
- description:
TQ-Systems TQMLS102xA is a series of socketable SOM featuring
LS102x system-on-chip variants. MBLS102xA mainboard can be used as
starterkit.
items:
- enum:
- tq,ls1021a-tqmls1021a-mbls102xa
- const: tq,ls1021a-tqmls1021a
- const: fsl,ls1021a
- description: LS1028A based Boards
items:
- enum:

20
sys/contrib/device-tree/Bindings/arm/hisilicon/controller/cpuctrl.yaml
View file

@ -29,6 +29,26 @@ properties:
ranges: true
patternProperties:
"^clock@[0-9a-f]+$":
type: object
additionalProperties: false
properties:
compatible:
const: hisilicon,hix5hd2-clock
reg:
maxItems: 1
"#clock-cells":
const: 1
required:
- compatible
- reg
- "#clock-cells"
required:
- compatible
- reg

5
sys/contrib/device-tree/Bindings/arm/intel,socfpga.yaml
View file

@ -21,6 +21,11 @@ properties:
- intel,socfpga-agilex-n6000
- intel,socfpga-agilex-socdk
- const: intel,socfpga-agilex
- description: Agilex5 boards
items:
- enum:
- intel,socfpga-agilex5-socdk
- const: intel,socfpga-agilex5
additionalProperties: true

2
sys/contrib/device-tree/Bindings/arm/keystone/ti,k3-sci-common.yaml
View file

@ -1,4 +1,4 @@
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/keystone/ti,k3-sci-common.yaml#

2
sys/contrib/device-tree/Bindings/arm/keystone/ti,sci.yaml
View file

@ -1,4 +1,4 @@
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/keystone/ti,sci.yaml#

8
sys/contrib/device-tree/Bindings/arm/marvell/cp110-system-controller.txt
View file

@ -21,13 +21,13 @@ The Device Tree node representing this System Controller 0 provides a
number of clocks:
- a set of core clocks
- a set of gatable clocks
- a set of gateable clocks
Those clocks can be referenced by other Device Tree nodes using two
cells:
- The first cell must be 0 or 1. 0 for the core clocks and 1 for the
gatable clocks.
- The second cell identifies the particular core clock or gatable
gateable clocks.
- The second cell identifies the particular core clock or gateable
clocks.
The following clocks are available:
@ -38,7 +38,7 @@ The following clocks are available:
- 0 3 Core
- 0 4 NAND core
- 0 5 SDIO core
- Gatable clocks
- Gateable clocks
- 1 0 Audio
- 1 1 Comm Unit
- 1 2 NAND

2
sys/contrib/device-tree/Bindings/arm/mediatek/mediatek,mipi0a.txt
View file

@ -16,7 +16,7 @@ The available clocks are defined in dt-bindings/clock/mt*-clk.h.
The mipi0a controller also uses the common power domain from
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
The available power doamins are defined in dt-bindings/power/mt*-power.h.
The available power domains are defined in dt-bindings/power/mt*-power.h.
Example:

2
sys/contrib/device-tree/Bindings/arm/mediatek/mediatek,vcodecsys.txt
View file

@ -15,7 +15,7 @@ The available clocks are defined in dt-bindings/clock/mt*-clk.h.
The vcodecsys controller also uses the common power domain from
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
The available power doamins are defined in dt-bindings/power/mt*-power.h.
The available power domains are defined in dt-bindings/power/mt*-power.h.
Example:

4
sys/contrib/device-tree/Bindings/arm/mstar/mstar,l3bridge.yaml
View file

@ -2,8 +2,8 @@
# Copyright 2020 thingy.jp.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MStar/SigmaStar Armv7 SoC l3bridge

4
sys/contrib/device-tree/Bindings/arm/mstar/mstar,smpctrl.yaml
View file

@ -2,8 +2,8 @@
# Copyright 2020 thingy.jp.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/mstar/mstar,smpctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MStar/SigmaStar Armv7 SoC SMP control registers

2
sys/contrib/device-tree/Bindings/arm/omap/ctrl.txt
View file

@ -8,7 +8,7 @@ control module driver itself.
See [2] for documentation about clock/clockdomain nodes.
[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
[2] Documentation/devicetree/bindings/clock/ti/*
Required properties:

99
sys/contrib/device-tree/Bindings/arm/omap/omap.txt
View file

@ -41,14 +41,6 @@ SoC Type (optional):
SoC Families:
- OMAP2 generic - defaults to OMAP2420
compatible = "ti,omap2"
- OMAP3 generic
compatible = "ti,omap3"
- OMAP4 generic - defaults to OMAP4430
compatible = "ti,omap4"
- OMAP5 generic - defaults to OMAP5430
compatible = "ti,omap5"
- DRA7 generic - defaults to DRA742
compatible = "ti,dra7"
- AM33x generic
@ -58,32 +50,6 @@ SoC Families:
SoCs:
- OMAP2420
compatible = "ti,omap2420", "ti,omap2"
- OMAP2430
compatible = "ti,omap2430", "ti,omap2"
- OMAP3430
compatible = "ti,omap3430", "ti,omap3"
legacy: "ti,omap34xx" - please do not use any more
- AM3517
compatible = "ti,am3517", "ti,omap3"
- OMAP3630
compatible = "ti,omap3630", "ti,omap3"
legacy: "ti,omap36xx" - please do not use any more
- AM335x
compatible = "ti,am33xx"
- OMAP4430
compatible = "ti,omap4430", "ti,omap4"
- OMAP4460
compatible = "ti,omap4460", "ti,omap4"
- OMAP5430
compatible = "ti,omap5430", "ti,omap5"
- OMAP5432
compatible = "ti,omap5432", "ti,omap5"
- DRA762
compatible = "ti,dra762", "ti,dra7"
@ -116,65 +82,6 @@ SoCs:
Boards (incomplete list of examples):
- OMAP3 BeagleBoard : Low cost community board
compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3"
- OMAP3 BeagleBoard A to B4 : Early BeagleBoard revisions A to B4 with a timer quirk
compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3"
- OMAP3 Tobi with Overo : Commercial expansion board with daughter board
compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3"
- OMAP4 SDP : Software Development Board
compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4"
- OMAP4 PandaBoard : Low cost community board
compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"
- OMAP4 DuoVero with Parlor : Commercial expansion board with daughter board
compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4";
- OMAP4 VAR-STK-OM44 : Commercial dev kit with VAR-OM44CustomBoard and VAR-SOM-OM44 w/WLAN
compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
- OMAP4 VAR-DVK-OM44 : Commercial dev kit with VAR-OM44CustomBoard, VAR-SOM-OM44 w/WLAN and LCD touchscreen
compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
- OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x
compatible = "ti,omap3-evm", "ti,omap3630", "ti,omap3"
- AM335X EVM : Software Development Board for AM335x
compatible = "ti,am335x-evm", "ti,am33xx"
- AM335X Bone : Low cost community board
compatible = "ti,am335x-bone", "ti,am33xx"
- AM3359 ICEv2 : Low cost Industrial Communication Engine EVM.
compatible = "ti,am3359-icev2", "ti,am33xx"
- AM335X OrionLXm : Substation Automation Platform
compatible = "novatech,am335x-lxm", "ti,am33xx"
- AM335X phyBOARD-WEGA: Single Board Computer dev kit
compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"
- AM335X CM-T335 : System On Module, built around the Sitara AM3352/4
compatible = "compulab,cm-t335", "ti,am33xx"
- AM335X SBC-T335 : single board computer, built around the Sitara AM3352/4
compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx"
- AM335X phyCORE-AM335x: Development kit
compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx"
- AM335x phyBOARD-REGOR: Single Board Computer
compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx"
- AM335X UC-8100-ME-T: Communication-centric industrial computing platform
compatible = "moxa,uc-8100-me-t", "ti,am33xx";
- OMAP5 EVM : Evaluation Module
compatible = "ti,omap5-evm", "ti,omap5"
- AM437x CM-T43
compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43"
@ -217,9 +124,3 @@ Boards (incomplete list of examples):
- DRA718 EVM: Software Development Board for DRA718
compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7"
- DM3730 Logic PD Torpedo + Wireless: Commercial System on Module with WiFi and Bluetooth
compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3"
- DM3730 Logic PD SOM-LV: Commercial System on Module with WiFi and Bluetooth
compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3"

5
sys/contrib/device-tree/Bindings/arm/pmu.yaml
View file

@ -49,9 +49,14 @@ properties:
- arm,cortex-a77-pmu
- arm,cortex-a78-pmu
- arm,cortex-a510-pmu
- arm,cortex-a520-pmu
- arm,cortex-a710-pmu
- arm,cortex-a715-pmu
- arm,cortex-a720-pmu
- arm,cortex-x1-pmu
- arm,cortex-x2-pmu
- arm,cortex-x3-pmu
- arm,cortex-x4-pmu
- arm,neoverse-e1-pmu
- arm,neoverse-n1-pmu
- arm,neoverse-n2-pmu

2
sys/contrib/device-tree/Bindings/arm/qcom,coresight-tpda.yaml
View file

@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
%YAML 1.2
---

2
sys/contrib/device-tree/Bindings/arm/qcom,coresight-tpdm.yaml
View file

@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
# Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
%YAML 1.2
---

2
sys/contrib/device-tree/Bindings/arm/qcom-soc.yaml
View file

@ -31,7 +31,7 @@ properties:
compatible:
oneOf:
# Preferred naming style for compatibles of SoC components:
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+-.*$"
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+(pro)?-.*$"
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
# Legacy namings - variations of existing patterns/compatibles are OK,

14
sys/contrib/device-tree/Bindings/arm/qcom.yaml
View file

@ -30,6 +30,7 @@ description: |
apq8084
apq8096
ipq4018
ipq5018
ipq5332
ipq6018
ipq8074
@ -72,6 +73,7 @@ description: |
sdx65
sdx75
sm4250
sm4450
sm6115
sm6115p
sm6125
@ -104,6 +106,7 @@ description: |
hk10-c2
idp
liquid
rdp432-c2
mtp
qrd
rb2
@ -186,6 +189,7 @@ properties:
- items:
- enum:
- samsung,a7
- sony,kanuti-tulip
- square,apq8039-t2
- const: qcom,msm8939
@ -339,6 +343,11 @@ properties:
- qcom,ipq4019-dk04.1-c1
- const: qcom,ipq4019
- items:
- enum:
- qcom,ipq5018-rdp432-c2
- const: qcom,ipq5018
- items:
- enum:
- qcom,ipq5332-ap-mi01.2
@ -902,6 +911,11 @@ properties:
- const: qcom,qrb4210
- const: qcom,sm4250
- items:
- enum:
- qcom,sm4450-qrd
- const: qcom,sm4450
- items:
- enum:
- fxtec,pro1x

15
sys/contrib/device-tree/Bindings/arm/rockchip.yaml
View file

@ -196,6 +196,11 @@ properties:
- const: firefly,rk3566-roc-pc
- const: rockchip,rk3566
- description: Firefly Station P2
items:
- const: firefly,rk3568-roc-pc
- const: rockchip,rk3568
- description: FriendlyElec NanoPi R2 series boards
items:
- enum:
@ -222,6 +227,11 @@ properties:
- friendlyarm,nanopi-r5s
- const: rockchip,rk3568
- description: FriendlyElec NanoPC T6
items:
- const: friendlyarm,nanopc-t6
- const: rockchip,rk3588
- description: GeekBuying GeekBox
items:
- const: geekbuying,geekbox
@ -694,6 +704,11 @@ properties:
- const: radxa,rock-4c-plus
- const: rockchip,rk3399
- description: Radxa ROCK 4SE
items:
- const: radxa,rock-4se
- const: rockchip,rk3399
- description: Radxa ROCK Pi E
items:
- const: radxa,rockpi-e

4
sys/contrib/device-tree/Bindings/arm/stm32/st,mlahb.yaml
View file

@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/stm32/st,mlahb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32 ML-AHB interconnect

4
sys/contrib/device-tree/Bindings/arm/stm32/st,stm32-syscon.yaml
View file

@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/stm32/st,stm32-syscon.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/arm/stm32/st,stm32-syscon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32 Platforms System Controller

4
sys/contrib/device-tree/Bindings/arm/stm32/stm32.yaml
View file

@ -143,7 +143,9 @@ properties:
- description: Octavo OSD32MP15x System-in-Package based boards
items:
- enum:
- lxa,stm32mp157c-mc1 # Linux Automation MC-1
- lxa,stm32mp157c-mc1 # Linux Automation MC-1
- lxa,stm32mp157c-tac-gen1 # Linux Automation TAC (Generation 1)
- lxa,stm32mp157c-tac-gen2 # Linux Automation TAC (Generation 2)
- const: oct,stm32mp15xx-osd32
- enum:
- st,stm32mp157

9
sys/contrib/device-tree/Bindings/arm/sunxi.yaml
View file

@ -541,13 +541,13 @@ properties:
- const: msi,primo81
- const: allwinner,sun6i-a31s
- description: Emlid Neutis N5 Developper Board
- description: Emlid Neutis N5 Developer Board
items:
- const: emlid,neutis-n5-devboard
- const: emlid,neutis-n5
- const: allwinner,sun50i-h5
- description: Emlid Neutis N5H3 Developper Board
- description: Emlid Neutis N5H3 Developer Board
items:
- const: emlid,neutis-n5h3-devboard
- const: emlid,neutis-n5h3
@ -997,4 +997,9 @@ properties:
- const: xunlong,orangepi-zero2
- const: allwinner,sun50i-h616
- description: Xunlong OrangePi Zero 3
items:
- const: xunlong,orangepi-zero3
- const: allwinner,sun50i-h618
additionalProperties: true

13
sys/contrib/device-tree/Bindings/arm/ti/k3.yaml
View file

@ -25,6 +25,12 @@ properties:
- ti,am62a7-sk
- const: ti,am62a7
- description: K3 AM62P5 SoC and Boards
items:
- enum:
- ti,am62p5-sk
- const: ti,am62p5
- description: K3 AM625 SoC PHYTEC phyBOARD-Lyra
items:
- const: phytec,am625-phyboard-lyra-rdk
@ -72,6 +78,13 @@ properties:
- const: phytec,am64-phycore-som
- const: ti,am642
- description: K3 AM642 SoC on TQ-Systems TQMaX4XxL SoM
items:
- enum:
- tq,am642-tqma6442l-mbax4xxl # MBaX4XxL base board
- const: tq,am642-tqma6442l
- const: ti,am642
- description: K3 AM654 SoC
items:
- enum:

176
sys/contrib/device-tree/Bindings/arm/ti/omap.yaml Normal file
View file

@ -0,0 +1,176 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/ti/omap.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments OMAP SoC architecture
maintainers:
- Tony Lindgren <tony@atomide.com>
description: Platforms based on Texas Instruments OMAP SoC architecture.
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: TI OMAP2420 SoC based platforms
items:
- enum:
- nokia,n800
- nokia,n810
- nokia,n810-wimax
- ti,omap2420-h4
- const: ti,omap2420
- const: ti,omap2
- description: TI OMAP2430 SoC based platforms
items:
- enum:
- ti,omap2430-sdp # TI OMAP2430 SDP
- const: ti,omap2430
- const: ti,omap2
- description: TI OMAP3430 SoC based platforms
items:
- enum:
- compulab,omap3-cm-t3530
- logicpd,dm3730-som-lv-devkit # LogicPD Zoom OMAP35xx SOM-LV Development Kit
- logicpd,dm3730-torpedo-devkit # LogicPD Zoom OMAP35xx Torpedo Development Kit
- nokia,omap3-n900
- openpandora,omap3-pandora-600mhz
- ti,omap3430-sdp
- ti,omap3-beagle
- ti,omap3-evm # TI OMAP35XX EVM (TMDSEVM3530)
- ti,omap3-ldp # TI OMAP3430 LDP (Zoom1 Labrador)
- timll,omap3-devkit8000
- const: ti,omap3430
- const: ti,omap3
- description: Early BeagleBoard revisions A to B4 with a timer quirk
items:
- const: ti,omap3-beagle-ab4
- const: ti,omap3-beagle
- const: ti,omap3430
- const: ti,omap3
- description: Gumstix Overo TI OMAP 3430/3630 boards + expansion boards
items:
- enum:
- gumstix,omap3-overo-alto35
- gumstix,omap3-overo-chestnut43
- gumstix,omap3-overo-gallop43
- gumstix,omap3-overo-palo35
- gumstix,omap3-overo-palo43
- gumstix,omap3-overo-summit
- gumstix,omap3-overo-tobi
- gumstix,omap3-overo-tobiduo
- const: gumstix,omap3-overo
- enum:
- ti,omap3430
- ti,omap3630
- description: TI OMAP3630 SoC based platforms
items:
- enum:
- amazon,omap3-echo # Amazon Echo (first generation)
- compulab,omap3-cm-t3730
- goldelico,gta04
- lg,omap3-sniper # LG Optimus Black
- logicpd,dm3730-som-lv-devkit # LogicPD Zoom DM3730 SOM-LV Development Kit
- logicpd,dm3730-torpedo-devkit # LogicPD Zoom DM3730 Torpedo + Wireless Development Kit
- nokia,omap3-n9
- nokia,omap3-n950
- openpandora,omap3-pandora-1ghz
- ti,omap3-beagle-xm
- ti,omap3-evm-37xx # TI OMAP37XX EVM (TMDSEVM3730)
- ti,omap3-zoom3
- const: ti,omap3630
- const: ti,omap3
- description: TI AM35 SoC based platforms
items:
- enum:
- compulab,omap3-sbc-t3517 # CompuLab SBC-T3517 with CM-T3517
- teejet,mt_ventoux
- ti,am3517-craneboard # TI AM3517 CraneBoard (TMDSEVM3517)
- ti,am3517-evm # TI AM3517 EVM (AM3517/05 TMDSEVM3517)
- const: ti,am3517
- const: ti,omap3
- description: TI AM33 based platform
items:
- enum:
- compulab,cm-t335
- moxa,uc-8100-me-t
- novatech,am335x-lxm
- ti,am335x-bone
- ti,am335x-evm
- ti,am3359-icev2
- const: ti,am33xx
- description: Compulab board variants based on TI AM33
items:
- enum:
- compulab,sbc-t335
- const: compulab,cm-t335
- const: ti,am33xx
- description: Phytec boards based on TI AM33
items:
- enum:
- phytec,am335x-wega
- phytec,am335x-pcm-953
- phytec,am335x-regor
- const: phytec,am335x-phycore-som
- const: ti,am33xx
- description: TI OMAP4430 SoC based platforms
items:
- enum:
- amazon,omap4-kc1 # Amazon Kindle Fire (first generation)
- motorola,droid4 # Motorola Droid 4 XT894
- motorola,droid-bionic # Motorola Droid Bionic XT875
- ti,omap4-panda
- ti,omap4-sdp
- const: ti,omap4430
- const: ti,omap4
- description: OMAP4 DuoVero with Parlor expansion board/daughter board
items:
- const: gumstix,omap4-duovero-parlor
- const: gumstix,omap4-duovero
- const: ti,omap4430
- const: ti,omap4
- description: TI OMAP4460 SoC based platforms
items:
- enum:
- epson,embt2ws # Epson Moverio BT-200
- ti,omap4-panda-es
- const: ti,omap4460
- const: ti,omap4
- description: VAR-OM44 boards
items:
- enum:
- variscite,var-dvk-om44
- variscite,var-stk-om44
- const: variscite,var-som-om44
- const: ti,omap4460
- const: ti,omap4
- description: TI OMAP5 SoC based platforms
items:
- enum:
- compulab,omap5-cm-t54
- isee,omap5-igep0050
- ti,omap5-uevm
- const: ti,omap5
additionalProperties: true
...

3
sys/contrib/device-tree/Bindings/ata/pata-common.yaml
View file

@ -12,7 +12,7 @@ maintainers:
description: |
This document defines device tree properties common to most Parallel
ATA (PATA, also known as IDE) AT attachment storage devices.
It doesn't constitue a device tree binding specification by itself but is
It doesn't constitute a device tree binding specification by itself but is
meant to be referenced by device tree bindings.
The PATA (IDE) controller-specific device tree bindings are responsible for
@ -38,6 +38,7 @@ patternProperties:
ID number 0 and the slave drive will have ID number 1. The PATA port
nodes will be named "ide-port".
type: object
additionalProperties: false
properties:
reg:

2
sys/contrib/device-tree/Bindings/bus/brcm,gisb-arb.yaml
View file

@ -43,7 +43,7 @@ properties:
brcm,gisb-arb-master-names:
$ref: /schemas/types.yaml#/definitions/string-array
description: >
String list of the litteral name of the GISB masters. Should match the
String list of the literal name of the GISB masters. Should match the
number of bits set in brcm,gisb-master-mask and the order in which they
appear from MSB to LSB.

3
sys/contrib/device-tree/Bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml
View file

@ -73,9 +73,6 @@ patternProperties:
"^.*@[0-9a-f]+$":
description: Devices attached to the bus
type: object
properties:
reg:
maxItems: 1
required:
- reg

4
sys/contrib/device-tree/Bindings/bus/nvidia,tegra210-aconnect.yaml
View file

@ -7,10 +7,10 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra ACONNECT Bus
description: |
The Tegra ACONNECT bus is an AXI switch which is used to connnect various
The Tegra ACONNECT bus is an AXI switch which is used to connect various
components inside the Audio Processing Engine (APE). All CPU accesses to
the APE subsystem go through the ACONNECT via an APB to AXI wrapper. All
devices accessed via the ACONNNECT are described by child-nodes.
devices accessed via the ACONNECT are described by child-nodes.
maintainers:
- Jon Hunter <jonathanh@nvidia.com>

63
sys/contrib/device-tree/Bindings/bus/qcom,ssbi.yaml Normal file
View file

@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/qcom,ssbi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Single-wire Serial Bus Interface (SSBI)
description:
Some Qualcomm MSM devices contain a point-to-point serial bus used to
communicate with a limited range of devices (mostly power management
chips).
maintainers:
- Andy Gross <agross@kernel.org>
- Bjorn Andersson <andersson@kernel.org>
properties:
compatible:
const: qcom,ssbi
reg:
maxItems: 1
qcom,controller-type:
description:
Indicates the SSBI bus variant the controller should use to talk
with the slave device. The type chosen is determined by the attached
slave.
enum:
- ssbi
- ssbi2
- pmic-arbiter
pmic:
$ref: /schemas/mfd/qcom-pm8xxx.yaml#
required:
- compatible
- reg
- qcom,controller-type
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
ssbi@c00000 {
compatible = "qcom,ssbi";
reg = <0x00c00000 0x1000>;
qcom,controller-type = "pmic-arbiter";
pmic {
compatible = "qcom,pm8821";
interrupt-parent = <&msmgpio>;
interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
#interrupt-cells = <2>;
interrupt-controller;
#address-cells = <1>;
#size-cells = <0>;
};
};
...

81
sys/contrib/device-tree/Bindings/cache/andestech,ax45mp-cache.yaml vendored Normal file
View file

@ -0,0 +1,81 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright (C) 2023 Renesas Electronics Corp.
%YAML 1.2
---
$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Andestech AX45MP L2 Cache Controller
maintainers:
- Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
description:
A level-2 cache (L2C) is used to improve the system performance by providing
a large amount of cache line entries and reasonable access delays. The L2C
is shared between cores, and a non-inclusive non-exclusive policy is used.
select:
properties:
compatible:
contains:
enum:
- andestech,ax45mp-cache
required:
- compatible
properties:
compatible:
items:
- const: andestech,ax45mp-cache
- const: cache
reg:
maxItems: 1
interrupts:
maxItems: 1
cache-line-size:
const: 64
cache-level:
const: 2
cache-sets:
const: 1024
cache-size:
enum: [131072, 262144, 524288, 1048576, 2097152]
cache-unified: true
next-level-cache: true
additionalProperties: false
required:
- compatible
- reg
- interrupts
- cache-line-size
- cache-level
- cache-sets
- cache-size
- cache-unified
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
cache-controller@13400000 {
compatible = "andestech,ax45mp-cache", "cache";
reg = <0x13400000 0x100000>;
interrupts = <508 IRQ_TYPE_LEVEL_HIGH>;
cache-line-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
cache-size = <262144>;
cache-unified;
};

6
sys/contrib/device-tree/Bindings/chrome/google,cros-ec-typec.yaml
View file

@ -29,10 +29,8 @@ properties:
patternProperties:
'^connector@[0-9a-f]+$':
$ref: /schemas/connector/usb-connector.yaml#
unevaluatedProperties: false
properties:
reg:
maxItems: 1
required:
- reg
required:
- compatible

2
sys/contrib/device-tree/Bindings/clock/allwinner,sun4i-a10-osc-clk.yaml
View file

@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-osc-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 Gatable Oscillator Clock
title: Allwinner A10 Gateable Oscillator Clock
maintainers:
- Chen-Yu Tsai <wens@csie.org>

4
sys/contrib/device-tree/Bindings/clock/alphascale,acc.txt
View file

@ -1,7 +1,7 @@
Alphascale Clock Controller
The ACC (Alphascale Clock Controller) is responsible of choising proper
clock source, setting deviders and clock gates.
The ACC (Alphascale Clock Controller) is responsible for choosing proper
clock source, setting dividers and clock gates.
Required properties for the ACC node:
- compatible: must be "alphascale,asm9260-clock-controller"

85
sys/contrib/device-tree/Bindings/clock/amlogic,gxbb-aoclkc.yaml Normal file
View file

@ -0,0 +1,85 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,gxbb-aoclkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Always-On Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
properties:
compatible:
oneOf:
- items:
- enum:
- amlogic,meson-gxbb-aoclkc
- amlogic,meson-gxl-aoclkc
- amlogic,meson-gxm-aoclkc
- amlogic,meson-axg-aoclkc
- const: amlogic,meson-gx-aoclkc
- enum:
- amlogic,meson-axg-aoclkc
- amlogic,meson-g12a-aoclkc
clocks:
minItems: 2
maxItems: 5
clock-names:
minItems: 2
items:
- const: xtal
- const: mpeg-clk
- const: ext-32k-0
- const: ext-32k-1
- const: ext-32k-2
'#clock-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
allOf:
- if:
properties:
compatible:
enum:
- amlogic,meson-g12a-aoclkc
then:
properties:
clocks:
minItems: 2
maxItems: 3
clock-names:
minItems: 2
maxItems: 3
- if:
properties:
compatible:
enum:
- amlogic,meson-gxl-aoclkc
- amlogic,meson-gxm-aoclkc
- amlogic,meson-axg-aoclkc
then:
properties:
clocks:
maxItems: 2
clock-names:
maxItems: 2
additionalProperties: false

37
sys/contrib/device-tree/Bindings/clock/amlogic,gxbb-clkc.yaml Normal file
View file

@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,gxbb-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
properties:
compatible:
enum:
- amlogic,gxbb-clkc
- amlogic,gxl-clkc
- amlogic,axg-clkc
- amlogic,g12a-clkc
- amlogic,g12b-clkc
- amlogic,sm1-clkc
clocks:
maxItems: 1
clock-names:
const: xtal
'#clock-cells':
const: 1
required:
- compatible
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false

282
sys/contrib/device-tree/Bindings/clock/fsl,imx8-acm.yaml Normal file
View file

@ -0,0 +1,282 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8 Audio Clock Mux
maintainers:
- Shengjiu Wang <shengjiu.wang@nxp.com>
description: |
NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP
used to control Audio related clock on the SoC.
properties:
compatible:
enum:
- fsl,imx8dxl-acm
- fsl,imx8qm-acm
- fsl,imx8qxp-acm
reg:
maxItems: 1
power-domains:
minItems: 13
maxItems: 21
'#clock-cells':
const: 1
description:
The clock consumer should specify the desired clock by having the clock
ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h
for the full list of i.MX8 ACM clock IDs.
clocks:
minItems: 13
maxItems: 27
clock-names:
minItems: 13
maxItems: 27
required:
- compatible
- reg
- power-domains
- '#clock-cells'
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qxp-acm
then:
properties:
power-domains:
items:
- description: power domain of IMX_SC_R_AUDIO_CLK_0
- description: power domain of IMX_SC_R_AUDIO_CLK_1
- description: power domain of IMX_SC_R_MCLK_OUT_0
- description: power domain of IMX_SC_R_MCLK_OUT_1
- description: power domain of IMX_SC_R_AUDIO_PLL_0
- description: power domain of IMX_SC_R_AUDIO_PLL_1
- description: power domain of IMX_SC_R_ASRC_0
- description: power domain of IMX_SC_R_ASRC_1
- description: power domain of IMX_SC_R_ESAI_0
- description: power domain of IMX_SC_R_SAI_0
- description: power domain of IMX_SC_R_SAI_1
- description: power domain of IMX_SC_R_SAI_2
- description: power domain of IMX_SC_R_SAI_3
- description: power domain of IMX_SC_R_SAI_4
- description: power domain of IMX_SC_R_SAI_5
- description: power domain of IMX_SC_R_SPDIF_0
- description: power domain of IMX_SC_R_MQS_0
clocks:
minItems: 18
maxItems: 18
clock-names:
items:
- const: aud_rec_clk0_lpcg_clk
- const: aud_rec_clk1_lpcg_clk
- const: aud_pll_div_clk0_lpcg_clk
- const: aud_pll_div_clk1_lpcg_clk
- const: ext_aud_mclk0
- const: ext_aud_mclk1
- const: esai0_rx_clk
- const: esai0_rx_hf_clk
- const: esai0_tx_clk
- const: esai0_tx_hf_clk
- const: spdif0_rx
- const: sai0_rx_bclk
- const: sai0_tx_bclk
- const: sai1_rx_bclk
- const: sai1_tx_bclk
- const: sai2_rx_bclk
- const: sai3_rx_bclk
- const: sai4_rx_bclk
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8qm-acm
then:
properties:
power-domains:
items:
- description: power domain of IMX_SC_R_AUDIO_CLK_0
- description: power domain of IMX_SC_R_AUDIO_CLK_1
- description: power domain of IMX_SC_R_MCLK_OUT_0
- description: power domain of IMX_SC_R_MCLK_OUT_1
- description: power domain of IMX_SC_R_AUDIO_PLL_0
- description: power domain of IMX_SC_R_AUDIO_PLL_1
- description: power domain of IMX_SC_R_ASRC_0
- description: power domain of IMX_SC_R_ASRC_1
- description: power domain of IMX_SC_R_ESAI_0
- description: power domain of IMX_SC_R_ESAI_1
- description: power domain of IMX_SC_R_SAI_0
- description: power domain of IMX_SC_R_SAI_1
- description: power domain of IMX_SC_R_SAI_2
- description: power domain of IMX_SC_R_SAI_3
- description: power domain of IMX_SC_R_SAI_4
- description: power domain of IMX_SC_R_SAI_5
- description: power domain of IMX_SC_R_SAI_6
- description: power domain of IMX_SC_R_SAI_7
- description: power domain of IMX_SC_R_SPDIF_0
- description: power domain of IMX_SC_R_SPDIF_1
- description: power domain of IMX_SC_R_MQS_0
clocks:
minItems: 27
maxItems: 27
clock-names:
items:
- const: aud_rec_clk0_lpcg_clk
- const: aud_rec_clk1_lpcg_clk
- const: aud_pll_div_clk0_lpcg_clk
- const: aud_pll_div_clk1_lpcg_clk
- const: mlb_clk
- const: hdmi_rx_mclk
- const: ext_aud_mclk0
- const: ext_aud_mclk1
- const: esai0_rx_clk
- const: esai0_rx_hf_clk
- const: esai0_tx_clk
- const: esai0_tx_hf_clk
- const: esai1_rx_clk
- const: esai1_rx_hf_clk
- const: esai1_tx_clk
- const: esai1_tx_hf_clk
- const: spdif0_rx
- const: spdif1_rx
- const: sai0_rx_bclk
- const: sai0_tx_bclk
- const: sai1_rx_bclk
- const: sai1_tx_bclk
- const: sai2_rx_bclk
- const: sai3_rx_bclk
- const: sai4_rx_bclk
- const: sai5_tx_bclk
- const: sai6_rx_bclk
- if:
properties:
compatible:
contains:
enum:
- fsl,imx8dxl-acm
then:
properties:
power-domains:
items:
- description: power domain of IMX_SC_R_AUDIO_CLK_0
- description: power domain of IMX_SC_R_AUDIO_CLK_1
- description: power domain of IMX_SC_R_MCLK_OUT_0
- description: power domain of IMX_SC_R_MCLK_OUT_1
- description: power domain of IMX_SC_R_AUDIO_PLL_0
- description: power domain of IMX_SC_R_AUDIO_PLL_1
- description: power domain of IMX_SC_R_ASRC_0
- description: power domain of IMX_SC_R_SAI_0
- description: power domain of IMX_SC_R_SAI_1
- description: power domain of IMX_SC_R_SAI_2
- description: power domain of IMX_SC_R_SAI_3
- description: power domain of IMX_SC_R_SPDIF_0
- description: power domain of IMX_SC_R_MQS_0
clocks:
minItems: 13
maxItems: 13
clock-names:
items:
- const: aud_rec_clk0_lpcg_clk
- const: aud_rec_clk1_lpcg_clk
- const: aud_pll_div_clk0_lpcg_clk
- const: aud_pll_div_clk1_lpcg_clk
- const: ext_aud_mclk0
- const: ext_aud_mclk1
- const: spdif0_rx
- const: sai0_rx_bclk
- const: sai0_tx_bclk
- const: sai1_rx_bclk
- const: sai1_tx_bclk
- const: sai2_rx_bclk
- const: sai3_rx_bclk
additionalProperties: false
examples:
# Clock Control Module node:
- |
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
clock-controller@59e00000 {
compatible = "fsl,imx8qxp-acm";
reg = <0x59e00000 0x1d0000>;
#clock-cells = <1>;
power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
<&pd IMX_SC_R_AUDIO_CLK_1>,
<&pd IMX_SC_R_MCLK_OUT_0>,
<&pd IMX_SC_R_MCLK_OUT_1>,
<&pd IMX_SC_R_AUDIO_PLL_0>,
<&pd IMX_SC_R_AUDIO_PLL_1>,
<&pd IMX_SC_R_ASRC_0>,
<&pd IMX_SC_R_ASRC_1>,
<&pd IMX_SC_R_ESAI_0>,
<&pd IMX_SC_R_SAI_0>,
<&pd IMX_SC_R_SAI_1>,
<&pd IMX_SC_R_SAI_2>,
<&pd IMX_SC_R_SAI_3>,
<&pd IMX_SC_R_SAI_4>,
<&pd IMX_SC_R_SAI_5>,
<&pd IMX_SC_R_SPDIF_0>,
<&pd IMX_SC_R_MQS_0>;
clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>,
<&aud_rec1_lpcg IMX_LPCG_CLK_0>,
<&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
<&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
<&clk_ext_aud_mclk0>,
<&clk_ext_aud_mclk1>,
<&clk_esai0_rx_clk>,
<&clk_esai0_rx_hf_clk>,
<&clk_esai0_tx_clk>,
<&clk_esai0_tx_hf_clk>,
<&clk_spdif0_rx>,
<&clk_sai0_rx_bclk>,
<&clk_sai0_tx_bclk>,
<&clk_sai1_rx_bclk>,
<&clk_sai1_tx_bclk>,
<&clk_sai2_rx_bclk>,
<&clk_sai3_rx_bclk>,
<&clk_sai4_rx_bclk>;
clock-names = "aud_rec_clk0_lpcg_clk",
"aud_rec_clk1_lpcg_clk",
"aud_pll_div_clk0_lpcg_clk",
"aud_pll_div_clk1_lpcg_clk",
"ext_aud_mclk0",
"ext_aud_mclk1",
"esai0_rx_clk",
"esai0_rx_hf_clk",
"esai0_tx_clk",
"esai0_tx_hf_clk",
"spdif0_rx",
"sai0_rx_bclk",
"sai0_tx_bclk",
"sai1_rx_bclk",
"sai1_tx_bclk",
"sai2_rx_bclk",
"sai3_rx_bclk",
"sai4_rx_bclk";
};

40
sys/contrib/device-tree/Bindings/clock/intel,agilex5-clkmgr.yaml Normal file
View file

@ -0,0 +1,40 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel SoCFPGA Agilex5 clock manager
maintainers:
- Dinh Nguyen <dinguyen@kernel.org>
description:
The Intel Agilex5 Clock Manager is an integrated clock controller, which
generates and supplies clock to all the modules.
properties:
compatible:
const: intel,agilex5-clkmgr
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clkmgr: clock-controller@10d10000 {
compatible = "intel,agilex5-clkmgr";
reg = <0x10d10000 0x1000>;
#clock-cells = <1>;
};
...

2
sys/contrib/device-tree/Bindings/clock/keystone-pll.txt
View file

@ -14,7 +14,7 @@ Required properties:
- #clock-cells : from common clock binding; shall be set to 0.
- compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
- clocks : parent clock phandle
- reg - pll control0 and pll multipler registers
- reg - pll control0 and pll multiplier registers
- reg-names : control, multiplier and post-divider. The multiplier and
post-divider registers are applicable only for main pll clock
- fixed-postdiv : fixed post divider value. If absent, use clkod register bits

2
sys/contrib/device-tree/Bindings/clock/lpc1850-ccu.txt
View file

@ -68,7 +68,7 @@ soc {
"base_ssp0_clk", "base_sdio_clk";
};
/* A user of CCU brach clocks */
/* A user of CCU branch clocks */
uart1: serial@40082000 {
...
clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;

4
sys/contrib/device-tree/Bindings/clock/lpc1850-creg-clk.txt
View file

@ -5,8 +5,8 @@ control registers for two low speed clocks. One of the clocks is a
32 kHz oscillator driver with power up/down and clock gating. Next
is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
These clocks are used by the RTC and the Event Router peripherials.
The 32 kHz can also be routed to other peripherials to enable low
These clocks are used by the RTC and the Event Router peripherals.
The 32 kHz can also be routed to other peripherals to enable low
power modes.
This binding uses the common clock binding:

2
sys/contrib/device-tree/Bindings/clock/maxim,max9485.txt
View file

@ -12,7 +12,7 @@ requests.
Required properties:
- compatible: "maxim,max9485"
- clocks: Input clock, must provice 27.000 MHz
- clocks: Input clock, must provide 27.000 MHz
- clock-names: Must be set to "xclk"
- #clock-cells: From common clock binding; shall be set to 1

4
sys/contrib/device-tree/Bindings/clock/nvidia,tegra124-car.yaml
View file

@ -27,7 +27,9 @@ description: |
properties:
compatible:
const: nvidia,tegra124-car
enum:
- nvidia,tegra124-car
- nvidia,tegra132-car
reg:
maxItems: 1

24
sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm6125.yaml
View file

@ -29,6 +29,7 @@ properties:
- description: Link clock from DP PHY
- description: VCO DIV clock from DP PHY
- description: AHB config clock from GCC
- description: GPLL0 div source from GCC
clock-names:
items:
@ -39,6 +40,7 @@ properties:
- const: dp_phy_pll_link_clk
- const: dp_phy_pll_vco_div_clk
- const: cfg_ahb_clk
- const: gcc_disp_gpll0_div_clk_src
'#clock-cells':
const: 1
@ -46,6 +48,16 @@ properties:
'#power-domain-cells':
const: 1
power-domains:
description:
A phandle and PM domain specifier for the CX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing the power domain's performance point.
maxItems: 1
reg:
maxItems: 1
@ -63,23 +75,31 @@ examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@5f00000 {
compatible = "qcom,sm6125-dispcc";
reg = <0x5f00000 0x20000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
<&dsi1_phy 1>,
<&dp_phy 0>,
<&dp_phy 1>,
<&gcc GCC_DISP_AHB_CLK>;
<&gcc GCC_DISP_AHB_CLK>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
clock-names = "bi_tcxo",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
"dsi1_phy_pll_out_dsiclk",
"dp_phy_pll_link_clk",
"dp_phy_pll_vco_div_clk",
"cfg_ahb_clk";
"cfg_ahb_clk",
"gcc_disp_gpll0_div_clk_src";
required-opps = <&rpmhpd_opp_ret>;
power-domains = <&rpmpd SM6125_VDDCX>;
#clock-cells = <1>;
#power-domain-cells = <1>;
};

4
sys/contrib/device-tree/Bindings/clock/qcom,dispcc-sm8x50.yaml
View file

@ -82,7 +82,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,sm8250-dispcc";
reg = <0x0af00000 0x10000>;
@ -103,7 +103,7 @@ examples:
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8250_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

2
sys/contrib/device-tree/Bindings/clock/qcom,gcc-apq8064.yaml
View file

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on APQ8064/MSM8960
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
sys/contrib/device-tree/Bindings/clock/qcom,gcc-ipq4019.yaml
View file

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on IPQ4019
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
- Robert Marko <robert.markoo@sartura.hr>
description: |

2
sys/contrib/device-tree/Bindings/clock/qcom,gcc-ipq8074.yaml
View file

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on IPQ8074
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8976.yaml
View file

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on MSM8976
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8996.yaml
View file

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on MSM8996
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module which provides the clocks, resets and

2
sys/contrib/device-tree/Bindings/clock/qcom,gcc-msm8998.yaml
View file

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on MSM8998
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

5
sys/contrib/device-tree/Bindings/clock/qcom,gcc-other.yaml
View file

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
@ -19,8 +19,6 @@ description: |
include/dt-bindings/reset/qcom,gcc-ipq6018.h
include/dt-bindings/clock/qcom,gcc-msm8953.h
include/dt-bindings/clock/qcom,gcc-mdm9607.h
include/dt-bindings/clock/qcom,gcc-mdm9615.h
include/dt-bindings/reset/qcom,gcc-mdm9615.h
allOf:
- $ref: qcom,gcc.yaml#
@ -30,7 +28,6 @@ properties:
enum:
- qcom,gcc-ipq6018
- qcom,gcc-mdm9607
- qcom,gcc-mdm9615
required:
- compatible

2
sys/contrib/device-tree/Bindings/clock/qcom,gcc-qcs404.yaml
View file

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on QCS404
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc7180.yaml
View file

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on SC7180
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sc7280.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sdm845.yaml
View file

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on SDM670 and SDM845
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8150.yaml
View file

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on SM8150
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8250.yaml
View file

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller on SM8250
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power

2
sys/contrib/device-tree/Bindings/clock/qcom,gcc-sm8450.yaml
View file

@ -25,7 +25,7 @@ properties:
- description: Sleep clock source
- description: PCIE 0 Pipe clock source (Optional clock)
- description: PCIE 1 Pipe clock source (Optional clock)
- description: PCIE 1 Phy Auxillary clock source (Optional clock)
- description: PCIE 1 Phy Auxiliary clock source (Optional clock)
- description: UFS Phy Rx symbol 0 clock source (Optional clock)
- description: UFS Phy Rx symbol 1 clock source (Optional clock)
- description: UFS Phy Tx symbol 0 clock source (Optional clock)

2
sys/contrib/device-tree/Bindings/clock/qcom,gcc.yaml
View file

@ -8,7 +8,7 @@ title: Qualcomm Global Clock & Reset Controller Common Properties
maintainers:
- Stephen Boyd <sboyd@kernel.org>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Common bindings for Qualcomm global clock control module providing the

2
sys/contrib/device-tree/Bindings/clock/qcom,gpucc.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm graphics clock control module provides the clocks, resets and power

63
sys/contrib/device-tree/Bindings/clock/qcom,ipq5018-gcc.yaml Normal file
View file

@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ5018
maintainers:
- Sricharan Ramabadhran <quic_srichara@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ5018
See also::
include/dt-bindings/clock/qcom,ipq5018-gcc.h
include/dt-bindings/reset/qcom,ipq5018-gcc.h
properties:
compatible:
const: qcom,gcc-ipq5018
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: PCIE20 PHY0 pipe clock source
- description: PCIE20 PHY1 pipe clock source
- description: USB3 PHY pipe clock source
- description: GEPHY RX clock source
- description: GEPHY TX clock source
- description: UNIPHY RX clock source
- description: UNIPHY TX clk source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
clock-controller@1800000 {
compatible = "qcom,gcc-ipq5018";
reg = <0x01800000 0x80000>;
clocks = <&xo_board_clk>,
<&sleep_clk>,
<&pcie20_phy0_pipe_clk>,
<&pcie20_phy1_pipe_clk>,
<&usb3_phy0_pipe_clk>,
<&gephy_rx_clk>,
<&gephy_tx_clk>,
<&uniphy_rx_clk>,
<&uniphy_tx_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

2
sys/contrib/device-tree/Bindings/clock/qcom,kpss-acc-v1.yaml
View file

@ -14,7 +14,7 @@ description:
There is one ACC register region per CPU within the KPSS remapped region as
well as an alias register region that remaps accesses to the ACC associated
with the CPU accessing the region. ACC v1 is currently used as a
clock-controller for enabling the cpu and hanling the aux clocks.
clock-controller for enabling the cpu and handling the aux clocks.
properties:
compatible:

34
sys/contrib/device-tree/Bindings/clock/qcom,lcc.yaml
View file

@ -76,6 +76,40 @@ allOf:
- clocks
- clock-names
- if:
properties:
compatible:
contains:
enum:
- qcom,lcc-mdm9615
then:
properties:
clocks:
items:
- description: Board CXO source
- description: PLL 4 Vote clock
- description: MI2S codec clock
- description: Mic I2S codec clock
- description: Mic I2S spare clock
- description: Speaker I2S codec clock
- description: Speaker I2S spare clock
- description: PCM codec clock
clock-names:
items:
- const: cxo
- const: pll4_vote
- const: mi2s_codec_clk
- const: codec_i2s_mic_codec_clk
- const: spare_i2s_mic_codec_clk
- const: codec_i2s_spkr_codec_clk
- const: spare_i2s_spkr_codec_clk
- const: pcm_codec_clk
required:
- clocks
- clock-names
examples:
- |
clock-controller@28000000 {

4
sys/contrib/device-tree/Bindings/clock/qcom,mmcc.yaml
View file

@ -8,7 +8,7 @@ title: Qualcomm Multimedia Clock & Reset Controller
maintainers:
- Jeffrey Hugo <quic_jhugo@quicinc.com>
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm multimedia clock control module provides the clocks, resets and
@ -297,6 +297,7 @@ allOf:
- description: HDMI phy PLL clock
- description: DisplayPort phy PLL link clock
- description: DisplayPort phy PLL vco clock
- description: Global PLL 0 DIV clock
clock-names:
items:
@ -309,6 +310,7 @@ allOf:
- const: hdmipll
- const: dplink
- const: dpvco
- const: gpll0_div
- if:
properties:

4
sys/contrib/device-tree/Bindings/clock/qcom,msm8996-cbf.yaml
View file

@ -15,7 +15,9 @@ description: >
properties:
compatible:
const: qcom,msm8996-cbf
enum:
- qcom,msm8996-cbf
- qcom,msm8996pro-cbf
reg:
maxItems: 1

2
sys/contrib/device-tree/Bindings/clock/qcom,msm8998-gpucc.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on MSM8998
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm graphics clock control module provides the clocks, resets and power

3
sys/contrib/device-tree/Bindings/clock/qcom,qdu1000-gcc.yaml
View file

@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000
maintainers:
- Melody Olvera <quic_molvera@quicinc.com>
- Taniya Das <quic_tdas@quicinc.com>
- Imran Shaik <quic_imrashai@quicinc.com>
description: |
Qualcomm global clock control module which supports the clocks, resets and

2
sys/contrib/device-tree/Bindings/clock/qcom,rpmhcc.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. RPMh Clocks
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Resource Power Manager Hardened (RPMh) manages shared resources on

2
sys/contrib/device-tree/Bindings/clock/qcom,sc7180-camcc.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SC7180
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power

2
sys/contrib/device-tree/Bindings/clock/qcom,sc7180-dispcc.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on SC7180
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm display clock control module provides the clocks, resets and power

2
sys/contrib/device-tree/Bindings/clock/qcom,sc7180-lpasscorecc.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Core Clock Controller on SC7180
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm LPASS core clock control module provides the clocks and power

2
sys/contrib/device-tree/Bindings/clock/qcom,sc7180-mss.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Modem Clock Controller on SC7180
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm modem clock control module provides the clocks on SC7180.

2
sys/contrib/device-tree/Bindings/clock/qcom,sc7280-camcc.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Camera Clock & Reset Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and

2
sys/contrib/device-tree/Bindings/clock/qcom,sc7280-dispcc.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm display clock control module provides the clocks, resets and power

2
sys/contrib/device-tree/Bindings/clock/qcom,sc7280-lpasscc.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Core Clock Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm LPASS core clock control module provides the clocks and power

2
sys/contrib/device-tree/Bindings/clock/qcom,sc7280-lpasscorecc.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm LPASS Core & Audio Clock Controller on SC7280
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm LPASS core and audio clock control module provides the clocks and

2
sys/contrib/device-tree/Bindings/clock/qcom,sdm845-dispcc.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on SDM845
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm display clock control module provides the clocks, resets and power

8
sys/contrib/device-tree/Bindings/clock/qcom,sm8350-videocc.yaml
View file

@ -19,7 +19,9 @@ description: |
properties:
compatible:
const: qcom,sm8350-videocc
enum:
- qcom,sc8280xp-videocc
- qcom,sm8350-videocc
clocks:
items:
@ -51,7 +53,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@abf0000 {
compatible = "qcom,sm8350-videocc";
@ -59,7 +61,7 @@ examples:
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd SM8350_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;

4
sys/contrib/device-tree/Bindings/clock/qcom,sm8450-camcc.yaml
View file

@ -64,7 +64,7 @@ examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@ade0000 {
compatible = "qcom,sm8450-camcc";
reg = <0xade0000 0x20000>;
@ -72,7 +72,7 @@ examples:
<&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
power-domains = <&rpmhpd SM8450_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;

4
sys/contrib/device-tree/Bindings/clock/qcom,sm8450-dispcc.yaml
View file

@ -76,7 +76,7 @@ examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,sm8450-dispcc";
reg = <0x0af00000 0x10000>;
@ -91,7 +91,7 @@ examples:
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8450_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

4
sys/contrib/device-tree/Bindings/clock/qcom,sm8450-videocc.yaml
View file

@ -64,13 +64,13 @@ examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
videocc: clock-controller@aaf0000 {
compatible = "qcom,sm8450-videocc";
reg = <0x0aaf0000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_VIDEO_AHB_CLK>;
power-domains = <&rpmhpd SM8450_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;

4
sys/contrib/device-tree/Bindings/clock/qcom,sm8550-dispcc.yaml
View file

@ -76,7 +76,7 @@ examples:
- |
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,sm8550-dispcc";
reg = <0x0af00000 0x10000>;
@ -99,7 +99,7 @@ examples:
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8550_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

6
sys/contrib/device-tree/Bindings/clock/qcom,videocc.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Video Clock & Reset Controller
maintainers:
- Taniya Das <tdas@codeaurora.org>
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm video clock control module provides the clocks, resets and power
@ -124,7 +124,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@ab00000 {
compatible = "qcom,sdm845-videocc";
reg = <0x0ab00000 0x10000>;
@ -133,7 +133,7 @@ examples:
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd SM8250_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...

89
sys/contrib/device-tree/Bindings/clock/renesas,5p35023.yaml Normal file
View file

@ -0,0 +1,89 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator
maintainers:
- Biju Das <biju.das.jz@bp.renesas.com>
description: |
The 5P35023 is a VersaClock programmable clock generator and
is designed for low-power, consumer, and high-performance PCI
express applications. The 5P35023 device is a three PLL
architecture design, and each PLL is individually programmable
and allowing for up to 6 unique frequency outputs.
An internal OTP memory allows the user to store the configuration
in the device. After power up, the user can change the device register
settings through the I2C interface when I2C mode is selected.
The driver can read a full register map from the DT, and will use that
register map to initialize the attached part (via I2C) when the system
boots. Any configuration not supported by the common clock framework
must be done via the full register map, including optimized settings.
Link to datasheet:
https://www.renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator
properties:
compatible:
enum:
- renesas,5p35023
reg:
maxItems: 1
'#clock-cells':
description:
The index in the assigned-clocks is mapped to the output clock as below
0 - REF, 1 - SE1, 2 - SE2, 3 - SE3, 4 - DIFF1, 5 - DIFF2.
const: 1
clocks:
maxItems: 1
renesas,settings:
description: Optional, complete register map of the device.
Optimized settings for the device must be provided in full
and are written during initialization.
$ref: /schemas/types.yaml#/definitions/uint8-array
maxItems: 37
required:
- compatible
- reg
- '#clock-cells'
- clocks
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
versa3: clock-generator@68 {
compatible = "renesas,5p35023";
reg = <0x68>;
#clock-cells = <1>;
clocks = <&x1>;
renesas,settings = [
80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
80 b0 45 c4 95
];
assigned-clocks = <&versa3 0>, <&versa3 1>,
<&versa3 2>, <&versa3 3>,
<&versa3 4>, <&versa3 5>;
assigned-clock-rates = <24000000>, <11289600>,
<11289600>, <12000000>,
<25000000>, <12288000>;
};
};

2
sys/contrib/device-tree/Bindings/clock/sprd,sc9863a-clk.yaml
View file

@ -66,7 +66,7 @@ then:
else:
description: |
Other SC9863a clock nodes should be the child of a syscon node in
which compatible string shoule be:
which compatible string should be:
"sprd,sc9863a-glbregs", "syscon", "simple-mfd"
The 'reg' property for the clock node is also required if there is a sub

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