Mark arm64 mair_el1 fields as unsigned long

The register is 64-bit so the upper bits could be shifted past the
signed 32-bit size of an int the values were before.

Sponsored by:	Arm Ltd
This commit is contained in:
Andrew Turner 2023-03-16 16:19:21 +00:00
parent 3473f28322
commit a671f96d93

View file

@ -1155,13 +1155,13 @@
#define ID_ISAR5_VCMA_IMPL (UL(0x1) << ID_ISAR5_VCMA_SHIFT)
/* MAIR_EL1 - Memory Attribute Indirection Register */
#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8))
#define MAIR_ATTR_MASK(idx) (UL(0xff) << ((n)* 8))
#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
#define MAIR_DEVICE_nGnRnE 0x00
#define MAIR_DEVICE_nGnRE 0x04
#define MAIR_NORMAL_NC 0x44
#define MAIR_NORMAL_WT 0xbb
#define MAIR_NORMAL_WB 0xff
#define MAIR_DEVICE_nGnRnE UL(0x00)
#define MAIR_DEVICE_nGnRE UL(0x04)
#define MAIR_NORMAL_NC UL(0x44)
#define MAIR_NORMAL_WT UL(0xbb)
#define MAIR_NORMAL_WB UL(0xff)
/* MDCCINT_EL1 */
#define MDCCINT_EL1 MRS_REG(MDCCINT_EL1)