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Mark arm64 mair_el1 fields as unsigned long
The register is 64-bit so the upper bits could be shifted past the signed 32-bit size of an int the values were before. Sponsored by: Arm Ltd
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@ -1155,13 +1155,13 @@
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#define ID_ISAR5_VCMA_IMPL (UL(0x1) << ID_ISAR5_VCMA_SHIFT)
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/* MAIR_EL1 - Memory Attribute Indirection Register */
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#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8))
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#define MAIR_ATTR_MASK(idx) (UL(0xff) << ((n)* 8))
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#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
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#define MAIR_DEVICE_nGnRnE 0x00
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#define MAIR_DEVICE_nGnRE 0x04
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#define MAIR_NORMAL_NC 0x44
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#define MAIR_NORMAL_WT 0xbb
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#define MAIR_NORMAL_WB 0xff
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#define MAIR_DEVICE_nGnRnE UL(0x00)
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#define MAIR_DEVICE_nGnRE UL(0x04)
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#define MAIR_NORMAL_NC UL(0x44)
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#define MAIR_NORMAL_WT UL(0xbb)
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#define MAIR_NORMAL_WB UL(0xff)
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/* MDCCINT_EL1 */
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#define MDCCINT_EL1 MRS_REG(MDCCINT_EL1)
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